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1. 发明授权

US07982273B2 Masking of repeated overlay and alignment marks to allow reuse of photomasks in a vertical structure 有权
标题翻译：掩盖重复的覆盖和对准标记，以允许在垂直结构中重复使用光掩模
公开(公告)号：US07982273B2
公开(公告)日：2011-07-19
申请号：US12470886
申请日：2009-05-22
申请人： Yung-Tin Chen , Christopher J. Petti , Steven J. Radigan , Tanmay Kumar
发明人： Yung-Tin Chen , Christopher J. Petti , Steven J. Radigan , Tanmay Kumar
IPC分类号： H01L29/76
CPC分类号： H01L27/0688 , G03F7/70633 , G03F9/7084 , H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/5446
摘要： A monolithic three dimensional semiconductor device structure includes a first layer including a first occurrence of a first reference mark at a first location, and a second layer including a second occurrence of the first reference mark at a second location, wherein the second location is substantially directly above the first location. The device structure also includes an intermediate layer between the first layer and the second layer, the intermediate layer including a blocking structure, wherein the blocking structure is vertically interposed between the first occurrence of the first reference mark and the second occurrence of the first reference mark. Other aspects are also described.
摘要翻译：单片三维半导体器件结构包括第一层，其包括在第一位置处的第一参考标记的第一次出现，以及包括在第二位置处的第二参考标记的第二次出现的第二层，其中第二位置基本上直接在第一个位置以上。所述器件结构还包括在所述第一层和所述第二层之间的中间层，所述中间层包括阻挡结构，其中所述阻挡结构垂直插入所述第一参考标记的第一次出现和所述第一参考标记的第二次出现之间。还描述了其他方面。

2. 发明申请

US20090230571A1 MASKING OF REPEATED OVERLAY AND ALIGNMENT MARKS TO ALLOW REUSE OF PHOTOMASKS IN A VERTICAL STRUCTURE 有权
标题翻译：重复覆盖和对准标记的掩蔽以允许在垂直结构中重新使用光刻胶
公开(公告)号：US20090230571A1
公开(公告)日：2009-09-17
申请号：US12470886
申请日：2009-05-22
申请人： Yung-Tin Chen , Christopher J. Petti , Steven J. Radigan , Tanmay Kumar
发明人： Yung-Tin Chen , Christopher J. Petti , Steven J. Radigan , Tanmay Kumar
IPC分类号： H01L23/544 , G03F7/20
CPC分类号： H01L27/0688 , G03F7/70633 , G03F9/7084 , H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/5446
摘要： A monolithic three dimensional semiconductor device structure includes a first layer including a first occurrence of a first reference mark at a first location, and a second layer including a second occurrence of the first reference mark at a second location, wherein the second location is substantially directly above the first location. The device structure also includes an intermediate layer between the first layer and the second layer, the intermediate layer including a blocking structure, wherein the blocking structure is vertically interposed between the first occurrence of the first reference mark and the second occurrence of the first reference mark. Other aspects are also described.
摘要翻译：单片三维半导体器件结构包括第一层，其包括在第一位置处的第一参考标记的第一次出现，以及包括在第二位置处的第二参考标记的第二次出现的第二层，其中第二位置基本上直接在第一个位置以上。所述器件结构还包括在所述第一层和所述第二层之间的中间层，所述中间层包括阻挡结构，其中所述阻挡结构垂直插入在所述第一参考标记的第一次出现和所述第一参考标记的第二次出现之间。还描述了其他方面。

3. 发明授权

US07786015B2 Method for fabricating self-aligned complementary pillar structures and wiring 有权
标题翻译：自对准互补柱结构和布线的制造方法
公开(公告)号：US07786015B2
公开(公告)日：2010-08-31
申请号：US12149151
申请日：2008-04-28
申请人： Yung-Tin Chen , Chun-Ming Wang , Steven J. Radigan , Christopher J. Petti , Steven Maxwell
发明人： Yung-Tin Chen , Chun-Ming Wang , Steven J. Radigan , Christopher J. Petti , Steven Maxwell
IPC分类号： H01L21/311
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/31144 , H01L21/32139 , H01L27/1021
摘要： A method of making a semiconductor device includes forming at least one device layer over a substrate, forming at least two spaced apart features over the at least one device layer, forming sidewall spacers on the at least two features, selectively removing the spaced apart features, filling a space between a first sidewall spacer and a second sidewall spacer with a filler feature, selectively removing the sidewall spacers to leave a plurality of the filler features spaced apart from each other, and etching the at least one device layer using the filler feature as a mask.
摘要翻译：制造半导体器件的方法包括在衬底上形成至少一个器件层，在所述至少一个器件层上形成至少两个间隔的特征，在所述至少两个特征上形成侧壁间隔物，选择性地去除间隔开的特征，用填料特征填充第一侧壁间隔物和第二侧壁间隔物之间的空间，选择性地去除侧壁间隔物以留下彼此间隔开的多个填料特征，并使用填料特征来蚀刻至少一个器件层，如一个面具

4. 发明申请

US20090269932A1 Method for fabricating self-aligned complimentary pillar structures and wiring 有权
标题翻译：自对准互补柱结构和布线的制造方法
公开(公告)号：US20090269932A1
公开(公告)日：2009-10-29
申请号：US12149151
申请日：2008-04-28
申请人： Yung-Tin Chen , Chun-Ming Wang , Steven J. Radigan , Christopher J. Petti , Steven Maxwell
发明人： Yung-Tin Chen , Chun-Ming Wang , Steven J. Radigan , Christopher J. Petti , Steven Maxwell
IPC分类号： H01L21/311
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/31144 , H01L21/32139 , H01L27/1021
摘要： A method of making a semiconductor device includes forming at least one device layer over a substrate, forming at least two spaced apart features over the at least one device layer, forming sidewall spacers on the at least two features, selectively removing the spaced apart features, filling a space between a first sidewall spacer and a second sidewall spacer with a filler feature, selectively removing the sidewall spacers to leave a plurality of the filler features spaced apart from each other, and etching the at least one device layer using the filler feature as a mask.
摘要翻译：制造半导体器件的方法包括在衬底上形成至少一个器件层，在所述至少一个器件层上形成至少两个间隔的特征，在所述至少两个特征上形成侧壁间隔物，选择性地去除间隔开的特征，用填料特征填充第一侧壁间隔物和第二侧壁间隔物之间的空间，选择性地去除侧壁间隔物以留下彼此间隔开的多个填料特征，并使用填料特征来蚀刻至少一个器件层，如一个面具

5. 发明授权

US07759201B2 Method for fabricating pitch-doubling pillar structures 有权
标题翻译：制造俯仰倍增柱结构的方法
公开(公告)号：US07759201B2
公开(公告)日：2010-07-20
申请号：US12000758
申请日：2007-12-17
申请人： Christopher J. Petti , Steven J. Radigan
发明人： Christopher J. Petti , Steven J. Radigan
IPC分类号： H01L21/8234
CPC分类号： H01L27/102 , H01L21/0337
摘要： A method of making a semiconductor device includes forming at least one device layer over a substrate, forming at least two spaced apart features over the at least one device layer, forming sidewall spacers on the at least two features, filling a space between a first sidewall spacer on a first feature and a second sidewall spacer on a second feature with a filler feature, selectively removing the sidewall spacers to leave the first feature, the filler feature and the second feature spaced apart from each other, and etching the at least one device layer using the first feature, the filler feature and the second feature as a mask.
摘要翻译：制造半导体器件的方法包括在衬底上形成至少一个器件层，在所述至少一个器件层上形成至少两个间隔开的特征，在所述至少两个特征上形成侧壁间隔物，填充第一侧壁第一特征上的间隔物和具有填充物特征的第二特征上的第二侧壁间隔物，选择性地移除侧壁间隔物以留下第一特征，填料特征和第二特征彼此间隔开，并且蚀刻至少一个装置层，使用第一特征，填充特征和第二特征作为掩模。

6. 发明申请

US20090155962A1 Method for fabricating pitch-doubling pillar structures 有权
标题翻译：制造俯仰倍增柱结构的方法
公开(公告)号：US20090155962A1
公开(公告)日：2009-06-18
申请号：US12000758
申请日：2007-12-17
申请人： Christopher J. Petti , Steven J. Radigan
发明人： Christopher J. Petti , Steven J. Radigan
IPC分类号： H01L21/82
CPC分类号： H01L27/102 , H01L21/0337
摘要： A method of making a semiconductor device includes forming at least one device layer over a substrate, forming at least two spaced apart features over the at least one device layer, forming sidewall spacers on the at least two features, filling a space between a first sidewall spacer on a first feature and a second sidewall spacer on a second feature with a filler feature, selectively removing the sidewall spacers to leave the first feature, the filler feature and the second feature spaced apart from each other, and etching the at least one device layer using the first feature, the filler feature and the second feature as a mask.
摘要翻译：制造半导体器件的方法包括在衬底上形成至少一个器件层，在所述至少一个器件层上形成至少两个间隔开的特征，在所述至少两个特征上形成侧壁间隔物，填充第一侧壁第一特征上的间隔物和具有填充物特征的第二特征上的第二侧壁间隔物，选择性地移除侧壁间隔物以留下第一特征，填料特征和第二特征彼此间隔开，并且蚀刻至少一个装置层，使用第一特征，填充特征和第二特征作为掩模。

7. 发明申请

US20100302836A1 NONVOLATILE MEMORY CELL COMPRISING A DIODE AND A RESISTANCE-SWITCHING MATERIAL 有权
标题翻译：包含二极管和电阻切换材料的非易失性存储单元
公开(公告)号：US20100302836A1
公开(公告)日：2010-12-02
申请号：US12855462
申请日：2010-08-12
申请人： S. Brad Herner , Tanmay Kumar , Christopher J. Petti
发明人： S. Brad Herner , Tanmay Kumar , Christopher J. Petti
IPC分类号： G11C11/00 , H01L21/16
CPC分类号： H01L27/249 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/009 , G11C2213/15 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/72 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146
摘要： In a novel nonvolatile memory cell formed above a substrate, a diode is paired with a reversible resistance-switching material, preferably a metal oxide or nitride such as, for example, NixOy, NbxOy, TixOy, HfxOy, AlxOy, MgxOy, CoxOy, CrxOy, VxOy, ZnxOy, ZrxOy, BxNy, and AlxNy. In preferred embodiments, the diode is formed as a vertical pillar disposed between conductors. Multiple memory levels can be stacked to form a monolithic three dimensional memory array. In some embodiments, the diode comprises germanium or a germanium alloy, which can be deposited and crystallized at relatively low temperatures, allowing use of aluminum or copper in the conductors. The memory cell of the present invention can be used as a rewriteable memory cell or a one-time-programmable memory cell, and can store two or more data states.
摘要翻译：在形成于衬底上方的新型非易失性存储单元中，二极管与可逆电阻切换材料配对，优选为金属氧化物或氮化物，例如NixOy，NbxOy，TixOy，HfxOy，AlxOy，MgxOy，CoxOy，CrxOy ，VxOy，ZnxOy，ZrxOy，BxNy和AlxNy。在优选实施例中，二极管形成为设置在导体之间的垂直支柱。可以堆叠多个存储器级别以形成单片三维存储器阵列。在一些实施例中，二极管包括锗或锗合金，其可以在相对低的温度下沉积和结晶，从而允许在导体中使用铝或铜。本发明的存储单元可以用作可重写存储单元或一次可编程存储单元，并且可以存储两个或多个数据状态。

8. 发明授权

US07800934B2 Programming methods to increase window for reverse write 3D cell 有权
标题翻译：编程方法增加反向写入3D单元格的窗口
公开(公告)号：US07800934B2
公开(公告)日：2010-09-21
申请号：US11819077
申请日：2007-06-25
申请人： Tanmay Kumar , S. Brad Herner , Christopher J. Petti
发明人： Tanmay Kumar , S. Brad Herner , Christopher J. Petti
IPC分类号： G11C11/00 , G11C11/36
CPC分类号： G11C13/00 , G11C11/5692 , G11C13/0069 , G11C17/14 , G11C17/16 , G11C17/165 , G11C2013/009 , G11C2213/33 , H01L27/101
摘要： A method of operating a nonvolatile memory cell includes providing the nonvolatile memory cell comprising a diode which is fabricated in a first resistivity, unprogrammed state, and applying a forward bias to the diode having a magnitude greater than a minimum voltage required for programming the diode to switch the diode to a second resistivity, programmed state. The second resistivity state is lower than the first resistivity state.
摘要翻译：一种操作非易失性存储单元的方法包括提供非易失性存储单元，该非易失性存储单元包括以第一电阻率，未编程状态制造的二极管，以及将正向偏压施加到具有大于将二极管编程所需的最小电压的二极管的幅度将二极管切换到第二电阻率，编程状态。第二电阻率状态低于第一电阻率状态。

9. 发明授权

US08349664B2 Nonvolatile memory cell comprising a diode and a resistance-switching material 有权
标题翻译：包括二极管和电阻切换材料的非易失性存储单元
公开(公告)号：US08349664B2
公开(公告)日：2013-01-08
申请号：US12855462
申请日：2010-08-12
申请人： Scott Brad Herner , Christopher J. Petti , Tanmay Kumar
发明人： Scott Brad Herner , Christopher J. Petti , Tanmay Kumar
IPC分类号： H01L21/82
CPC分类号： H01L27/249 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/009 , G11C2213/15 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/72 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146
摘要： In a novel nonvolatile memory cell formed above a substrate, a diode is paired with a reversible resistance-switching material, preferably a metal oxide or nitride such as, for example, NixOy, NbxOy, TixOy, HfxOy, AlxOy, MgxOy, CoxOy, CrxOy, VxOy, ZnxOy, ZrxOy, BxNy, and AlxNy. In preferred embodiments, the diode is formed as a vertical pillar disposed between conductors. Multiple memory levels can be stacked to form a monolithic three dimensional memory array. In some embodiments, the diode comprises germanium or a germanium alloy, which can be deposited and crystallized at relatively low temperatures, allowing use of aluminum or copper in the conductors. The memory cell of the present invention can be used as a rewriteable memory cell or a one-time-programmable memory cell, and can store two or more data states.
摘要翻译：在形成在衬底上方的新型非易失性存储单元中，二极管与可逆电阻切换材料配对，优选为金属氧化物或氮化物，例如NixOy，NbxOy，TixOy，HfxOy，AlxOy，MgxOy，CoxOy，CrxOy ，VxOy，ZnxOy，ZrxOy，BxNy和AlxNy。在优选实施例中，二极管形成为设置在导体之间的垂直支柱。可以堆叠多个存储器级别以形成单片三维存储器阵列。在一些实施例中，二极管包括锗或锗合金，其可以在相对低的温度下沉积和结晶，从而允许在导体中使用铝或铜。本发明的存储单元可以用作可重写存储单元或一次可编程存储单元，并且可以存储两个或多个数据状态。

10. 发明授权

US07759666B2 3D R/W cell with reduced reverse leakage 有权
标题翻译： 3D R / W电池减少反向泄漏
公开(公告)号：US07759666B2
公开(公告)日：2010-07-20
申请号：US11819989
申请日：2007-06-29
申请人： Tanmay Kumar , Christopher J. Petti
发明人： Tanmay Kumar , Christopher J. Petti
IPC分类号： H01L29/02
CPC分类号： H01L27/24 , G11C13/0004
摘要： A nonvolatile memory device includes a semiconductor diode steering element, and a semiconductor read/write switching element.
摘要翻译：非易失性存储器件包括半导体二极管操作元件和半导体读/写开关元件。

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