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1. 发明授权

US5136348A Structure and manufacturing method for thin-film semiconductor diode device 失效
标题翻译：薄膜半导体二极管器件的结构和制造方法
公开(公告)号：US5136348A
公开(公告)日：1992-08-04
申请号：US647194
申请日：1991-01-28
申请人： Yukio Tsuzuki , Masami Yamaoka , Hiroshi Muto
发明人： Yukio Tsuzuki , Masami Yamaoka , Hiroshi Muto
IPC分类号： H01L27/06 , H01L27/12 , H01L29/04 , H01L29/78 , H01L29/861
CPC分类号： H01L29/7804 , H01L27/0688 , H01L27/12 , H01L29/04 , H01L29/861 , Y10S257/926
摘要： A structure and manufacturing method for a thin film semiconductor device consisting of a single diode or a plurality of diodes connected in series, the device being formed of at least one pair of mutually adjacent P-type (23a) and N-type (23b) regions formed in a layer of polycrystalline silicon (23) deposited on an insulating film (22) upon a substrate (21), to thereby define at least one PN junction. Each of the p-type regions and N-type regions is shaped as a rectangle, with opposite ends of each PN junction formed between these regions being respectively defined by two opposing sides of the polycrystalline silicon layer. Since each of the PN junctions is substantially rectilinear, an even distribution of current flow through each PN junction is attained, whereby a high resistance to destruction and an extremely stable value of reverse bias breakdown voltage are achieved.
摘要翻译：一种由串联连接的单个二极管或多个二极管组成的薄膜半导体器件的结构和制造方法，该器件由至少一对相互相邻的P型（23a）和N型（23b）形成，在衬底（21）上沉积在绝缘膜（22）上的多晶硅层（23）中形成的区域，从而限定至少一个PN结。每个p型区域和N型区域被成形为矩形，其中形成在这些区域之间的每个PN结的相对端分别由多晶硅层的两个相对侧限定。由于每个PN结基本上都是直线的，所以能够获得通过每个PN结的电流的平均分布，从而实现了高的抗破坏性和非常稳定的反向偏压击穿电压值。

2. 发明授权

US4896199A Semiconductor device with protective means against overheating 失效
标题翻译：具有防止过热的保护装置的半导体器件
公开(公告)号：US4896199A
公开(公告)日：1990-01-23
申请号：US169001
申请日：1988-03-16
申请人： Yukio Tsuzuki , Masami Yamaoka
发明人： Yukio Tsuzuki , Masami Yamaoka
IPC分类号： H01L23/58 , H01L21/822 , H01L23/34 , H01L27/02 , H01L27/04 , H01L29/78
CPC分类号： H01L29/7803 , H01L23/34 , H01L27/0248 , H01L29/7804 , H01L29/7808 , H01L2924/0002
摘要： A semiconductor substrate has a power region and a control region. The control region is located in the center portion of the substrate, and the power region surrounds the control region and is separated therefrom. A vertical type, MOS transistor, i.e., an active semiconductor element, is formed on the power region. An insulation film is formed on part of the control region. A polycrystalline silicon diode, which functions as a heat-sensitive element, is formed on the insulation film. A control section comprising a lateral type, MOS transistor is also formed on the control region. The lateral type, MOS transistor is connected to receive a signal form the polycrystalline silicon diode. Further, a polycrystalline silicon resistor, which determines a circuit constant, is formed on the insulation film. The MOS transistor protects the active semiconductor element in response to a signal supplied from the heat-sensitive element showing that the temperature of the semiconductor substrate has risen above a predetermined value. For example, the active semiconductor element may be disabled until the detected temperature drops below a predetermined value.

3. 发明授权

US4760434A Semiconductor device with protective means against overheating 失效
标题翻译：具有防止过热的保护装置的半导体器件
公开(公告)号：US4760434A
公开(公告)日：1988-07-26
申请号：US935718
申请日：1986-11-28
申请人： Yukio Tsuzuki , Masami Yamaoka
发明人： Yukio Tsuzuki , Masami Yamaoka
IPC分类号： H01L23/58 , H01L21/822 , H01L23/34 , H01L27/02 , H01L27/04 , H01L29/78 , G05F1/40 , H01L23/56 , H01L31/00
CPC分类号： H01L29/7803 , H01L23/34 , H01L27/0248 , H01L29/7804 , H01L29/7808 , H01L2924/0002
摘要： A semiconductor substrate has a power region and a control region. The control region is located in the center portion of the substrate, and the power region surrounds the control region and is separated therefrom. A vertical type, MOS transistor, i.e., an active semiconductor element, is formed on the power region. An insulation film is formed on part of the control region. A polycrystalline silicon diode, which functions as a heat-sensitive element, is formed on the insulation film. A control section comprising a lateral type, MOS transistor is also formed on the control region. The lateral type, MOS transistor is connected to receive a signal form the polycrystalline silicon diode. Further, a polycrystalline silicon resistor, which determines a circuit constant, is formed on the insulation film. The MOS transistor protects the active semiconductor element in response to a signal supplied from the heat-sensitive element showing that the temperature of the semiconductor substrate has risen above a predetermined value. For example, the active semiconductor element may be disabled until the detected temperature drops below a predetermined value.
摘要翻译：半导体衬底具有功率区域和控制区域。控制区域位于基板的中心部分，功率区域围绕控制区域并与之分离。在功率区域上形成垂直型MOS晶体管即有源半导体元件。在控制区域的一部分上形成绝缘膜。在绝缘膜上形成用作热敏元件的多晶硅二极管。在控制区域上还形成有包括横向型MOS晶体管的控制部。横向型MOS晶体管被连接以从多晶硅二极管接收信号。此外，在绝缘膜上形成确定电路常数的多晶硅电阻器。 MOS晶体管响应于来自热敏元件的信号保护有源半导体元件，表明半导体衬底的温度已经升高到预定值以上。例如，可以禁用活性半导体元件，直到检测到的温度下降到预定值以下。

4. 发明授权

US4680608A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US4680608A
公开(公告)日：1987-07-14
申请号：US697571
申请日：1985-02-01
申请人： Yukio Tsuzuki , Masami Yamaoka , Shoji Toyoshima
发明人： Yukio Tsuzuki , Masami Yamaoka , Shoji Toyoshima
IPC分类号： H01L29/73 , H01L21/331 , H01L29/08 , H01L29/732 , H01L29/72
CPC分类号： H01L29/0813
摘要： This application describes a semiconductor device having a power amplifier pattern consisting of a plurality of parallel-connected transistor unit cells with emitters thereof being arrayed like meshes, wherein the width of the emitter of each transistor unit cell is not in excess of 50 microns. The limitation of the emitter width contributes to enhancement of the reverse-bias breakdown endurance.
摘要翻译：本申请描述了一种具有功率放大器模式的半导体器件，该功率放大器模式由多个并联的晶体管单元电池组成，其发射极像网格一样排列，其中每个晶体管单电池的发射极的宽度不超过50微米。发射极宽度的限制有助于提高反向偏压击穿耐力。

5. 发明授权

US5128823A Power semiconductor apparatus 失效
标题翻译：功率半导体装置
公开(公告)号：US5128823A
公开(公告)日：1992-07-07
申请号：US365765
申请日：1989-06-14
申请人： Hiroshi Fujimoto , Masami Yamaoka , Yukio Tsuzuki
发明人： Hiroshi Fujimoto , Masami Yamaoka , Yukio Tsuzuki
IPC分类号： H03K17/08
CPC分类号： H03K17/08
摘要： A power MOS transistor and a current sensing MOS transistor have a common drain electrode connected to a load. The gates of these MOS transistors are commonly controlled in response to an input control signal. A load current sensing resistor element is connected between the source electrodes of these transistors. A voltage signal sensed by the load sensing resistor element is amplified by a differential amplifier constituted by a pair of depletion type MOS transistors. The amplified output controls the MOS transistors, and the MOS transistors variably control a voltage of the input control signal to be supplied to the power and current sensing MOS transistors. The power MOS transistor, the current sensing MOS transistor, the depletion MOS transistor, the current control MOS transistor, and the like have the same conductivity type.
摘要翻译：功率MOS晶体管和电流感测MOS晶体管具有连接到负载的公共漏电极。这些MOS晶体管的栅极通常响应于输入控制信号来控制。负载电流检测电阻元件连接在这些晶体管的源电极之间。由负载感测电阻元件感测的电压信号由由一对耗尽型MOS晶体管构成的差分放大器放大。放大的输出控制MOS晶体管，并且MOS晶体管可变地控制要提供给功率和电流感测MOS晶体管的输入控制信号的电压。功率MOS晶体管，电流感测MOS晶体管，耗尽型MOS晶体管，电流控制MOS晶体管等具有相同的导电类型。

6. 发明授权

US4879254A Method of manufacturing a DMOS 失效
标题翻译：制造DMOS的方法
公开(公告)号：US4879254A
公开(公告)日：1989-11-07
申请号：US204375
申请日：1988-06-09
申请人： Yukio Tsuzuki , Masami Yamaoka
发明人： Yukio Tsuzuki , Masami Yamaoka
IPC分类号： H01L21/336 , H01L29/10 , H01L29/45 , H01L29/78
CPC分类号： H01L29/66712 , H01L29/7802 , H01L29/1095 , H01L29/41766 , H01L29/456 , Y10S148/103 , Y10S148/111 , Y10S148/126 , Y10S148/131
摘要： A method for manufacturing a DMOS which comprises forming a first conductive type layer on a substrate, forming a gate oxide layer thereon, forming a gate electrode layer and a second insulating layer successively on the gate oxide layer, forming a second conductive type body region and a first conductive type source region having a narrower width by implanting impurities utilizing the second insulating layer as a mask, forming a side wall spacer of an insulating material on at least a side portion of the gate electrode, forming a conductive passage penetrating the source region and extending into the body region while utilizing the second insulating layer and the side wall spacer as mask, optionally implanting the exposed body region, further excessively etching the sidewall spacer, the masking layer overlying the gate, and the gate oxide prior to providing an electrode connecting the source and body regions.
摘要翻译：一种DMOS的制造方法，其特征在于，在基板上形成第一导电型层，在其上形成栅极氧化层，在所述栅极氧化层上依次形成栅电极层和第二绝缘层，形成第二导电型体区域，通过使用第二绝缘层作为掩模注入杂质而具有较窄宽度的第一导电类型源极区域，在栅电极的至少一个侧部分上形成绝缘材料的侧壁隔离物，形成穿透源极区域的导电通路并且在利用第二绝缘层和侧壁间隔物作为掩模的同时延伸到身体区域中，任选地植入暴露的身体区域，在提供电极之前进一步过度蚀刻侧壁间隔物，覆盖栅极的掩模层和栅极氧化物连接源和身体区域。

7. 发明授权

US4672402A Semiconductor circuit device including an overvoltage protection element 失效
标题翻译：包括过电压保护元件的半导体电路装置
公开(公告)号：US4672402A
公开(公告)日：1987-06-09
申请号：US912673
申请日：1986-09-25
申请人： Masami Yamaoka , Yukio Tsuzuki , Shoji Toyoshima
发明人： Masami Yamaoka , Yukio Tsuzuki , Shoji Toyoshima
IPC分类号： H01L29/73 , H01L21/331 , H01L29/866 , H01L29/868 , H01L29/90
CPC分类号： H01L29/868
摘要： In a semiconductor circuit device having a diode as an overvoltage protection element, a semiconductor substrate is comprised of an N-type collector substrate integral with a transistor. An N.sup.+ type collector diffusion layer is formed on the rear surface of the substrate. A P-type anode region and a N.sup.+ cathode region are formed in the major surface of the substrate so that they are spaced apart from each other and the N.sup.+ cathode region has the same type of impurity, but at a higher impurity concentration level than, the semiconductor substrate. An insulating film is formed on the surface of the resultant structure. A gate electrode is formed in an overlapping relation to the anode region and cathode region with an insulating film therebetween. A gate potential is established between the gate electrode and the underlying substrate.
摘要翻译：在具有二极管作为过电压保护元件的半导体电路器件中，半导体衬底由与晶体管集成的N型集电极基板构成。在基板的背面形成有N +型集电极扩散层。在基板的主表面上形成P型阳极区域和N +阴极区域，使得它们彼此间隔开，并且N +阴极区域具有相同类型的杂质，但是在较高的杂质浓度水平下，半导体衬底。在所得结构的表面上形成绝缘膜。与阳极区域和阴极区域之间具有绝缘膜的重叠关系形成栅电极。在栅极电极和下面的衬底之间建立栅极电位。

8. 发明授权

US08102025B2 Semiconductor device having IGBT and diode 有权
标题翻译：具有IGBT和二极管的半导体器件
公开(公告)号：US08102025B2
公开(公告)日：2012-01-24
申请号：US11709272
申请日：2007-02-22
申请人： Yoshihiko Ozeki , Norihito Tokura , Yukio Tsuzuki
发明人： Yoshihiko Ozeki , Norihito Tokura , Yukio Tsuzuki
IPC分类号： H01L29/66
CPC分类号： H01L27/0611 , H01L29/7395 , H01L29/8611
摘要： A semiconductor device includes: a semiconductor substrate; a IGBT region including a first region on a first surface of the substrate and providing a channel-forming region and a second region on a second surface of the substrate and providing a collector; a diode region including a third region on the first surface and providing an anode or a cathode and a fourth region on the second surface and providing the anode or the cathode; a periphery region including a fifth region on the first surface and a sixth region on the second surface. The first, third and fifth regions are commonly and electrically coupled, and the second, fourth and sixth regions are commonly and electrically coupled with one another.
摘要翻译：半导体器件包括：半导体衬底; IGBT区域，包括在所述基板的第一表面上的第一区域，并且在所述基板的第二表面上提供沟道形成区域和第二区域，并提供集电体; 二极管区域，包括在第一表面上的第三区域，并在第二表面上提供阳极或阴极和第四区域，并提供阳极或阴极; 外围区域，包括在第一表面上的第五区域和第二表面上的第六区域。第一，第三和第五区域通常和电耦合，并且第二，第四和第六区域彼此通常电耦合。

9. 发明授权

US07728382B2 Semiconductor device having diode and IGBT 有权
标题翻译：具有二极管和IGBT的半导体器件
公开(公告)号：US07728382B2
公开(公告)日：2010-06-01
申请号：US12222557
申请日：2008-08-12
申请人： Yukio Tsuzuki , Kenji Kouno
发明人： Yukio Tsuzuki , Kenji Kouno
IPC分类号： H01L29/76
CPC分类号： H01L27/0676 , H01L29/0623 , H01L29/7395 , H01L29/872
摘要： A semiconductor device includes: a semiconductor substrate including a first conductive type layer; a plurality of IGBT regions, each of which provides an IGBT element; and a plurality of diode regions, each of which provides a diode element. The plurality of IGBT regions and the plurality of diode regions are alternately arranged in the substrate. Each diode region includes a Schottky contact region having a second conductive type. The Schottky contact region is configured to retrieve a minority carrier from the first conductive type layer. The Schottky contact region is disposed in a first surface portion of the first conductive type layer, and adjacent to the IGBT region.
摘要翻译：半导体器件包括：包括第一导电类型层的半导体衬底; 多个IGBT区域，每个IGBT区域提供IGBT元件; 以及多个二极管区域，每个二极管区域提供二极管元件。多个IGBT区域和多个二极管区域交替地布置在基板中。每个二极管区域包括具有第二导电类型的肖特基接触区域。肖特基接触区域被配置为从第一导电类型层检索少数载流子。肖特基接触区域设置在第一导电类型层的第一表面部分中，并且与IGBT区域相邻。

10. 发明申请

US20090283798A1 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20090283798A1
公开(公告)日：2009-11-19
申请号：US12213469
申请日：2008-06-19
申请人： Yukio Tsuzuki , Makoto Asai
发明人： Yukio Tsuzuki , Makoto Asai
IPC分类号： H01L29/739 , H01L27/06 , H01L21/8232 , H01L21/331
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0619 , H01L29/0696 , H01L29/1095 , H01L29/41766 , H01L29/66727 , H01L29/66734 , H01L29/7397 , H01L29/7806
摘要： A semiconductor device includes an n-conductive type semiconductor substrate having a main side and a rear side, a p-conductive type layer arranged over the main side of the substrate, a main side n-conductive type region arranged in the p-conductive type layer, a rear side n-conductive type layer arranged over the rear side of the substrate, a first trench which reaches the substrate and penetrates the main side n-conductive type region and the p-conductive type layer, a second trench which reaches an inside of the p-conductive type layer, a second electrode layer, which is embedded in the second trench and connected to the p-conductive type layer. Hereby, the semiconductor device, in which the recovery property of a diode cell can be improved without damaging the property of a MOS transistor cell or an IGBT cell and the surge withstand property does not deteriorate, can be obtained.
摘要翻译：半导体器件包括具有主侧和后侧的n导电型半导体衬底，布置在衬底的主侧上的p导电型层，布置在p导电型中的主侧n导电型区域层，布置在基板的后侧上的后侧n导电型层，到达基板并穿透主侧n导电型区域和p导电型层的第一沟槽，到达基板的第二沟槽在p导电型层的内部，嵌入在第二沟槽中并连接到p导电型层的第二电极层。因此，可以获得其中二极管电池的恢复特性可以在不损害MOS晶体管单元或IGBT单元的性能而不损坏浪涌耐受性的情况下得到的半导体器件。

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