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1. 发明授权

US08847276B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08847276B2
公开(公告)日：2014-09-30
申请号：US13805740
申请日：2011-06-29
申请人： Hiromitsu Tanabe , Kenji Kouno , Yukio Tsuzuki
发明人： Hiromitsu Tanabe , Kenji Kouno , Yukio Tsuzuki
IPC分类号： H01L29/739 , H01L27/07 , H01L29/66 , H01L29/861 , H01L29/06
CPC分类号： H01L27/0664 , H01L27/0722 , H01L29/0696 , H01L29/4236 , H01L29/66348 , H01L29/7395 , H01L29/7397 , H01L29/861
摘要： In a semiconductor device including an IGBT and a freewheeling diode (FWD), W1, W2, and W3 satisfy predetermined formulas. W1 denotes a distance from a boundary between a cathode region and a collector region to a position, where a peripheral-region-side end of the well layer is projected, on a back side of the drift layer. W2 denotes a distance from a boundary between the IGBT and the FWD in a base region to the peripheral-region-side end of the well layer. W3 denotes a distance from the boundary between the cathode region and the collector region to a position, where a boundary between the base region and the well layer is projected, on the back side.
摘要翻译：在包括IGBT和续流二极管（FWD）的半导体器件中，W1，W2和W3满足预定的公式。 W1表示从阴极区域和集电极区域之间的边界到阱层的周边区域侧端部投射在位于漂移层的背面的位置的距离。 W2表示从基极区域到阱区域的周边区域侧的IGBT与FWD之间的边界的距离。 W3表示从阴极区域和集电极区域之间的边界到背面侧的基底区域和阱层之间的边界的位置的距离。

2. 发明申请

US20130009205A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130009205A1
公开(公告)日：2013-01-10
申请号：US13534530
申请日：2012-06-27
申请人： Yukio TSUZUKI , Kenji Kouno , Hiromitsu Tanabe
发明人： Yukio TSUZUKI , Kenji Kouno , Hiromitsu Tanabe
IPC分类号： H01L29/739
CPC分类号： H01L29/7397 , H01L29/0696 , H01L29/0834 , H01L29/1095 , H01L29/32 , H01L29/36 , H01L29/861
摘要： A semiconductor device has a first conductivity-type semiconductor substrate, second conductivity-type channel regions, and second conductivity-type thinning-out regions. The channel regions and the thinning-out regions are formed adjacent to a substrate surface of the semiconductor substrate. Further, a hole stopper layer is formed in each of the thinning-out regions to divide the thinning-out region into a first part adjacent to the substrate surface and a second part adjacent to a bottom of the thinning-out region. The hole stopper layer has an area density of equal to or less than 4.0×1012 cm−2 to permit a depletion layer to punch through the hole stopper layer, thereby to restrict breakdown properties from being decreased.
摘要翻译：半导体器件具有第一导电型半导体衬底，第二导电型沟道区和第二导电型稀疏区。沟道区域和稀疏区域形成为与半导体衬底的衬底表面相邻。此外，在每个稀疏区域中形成孔阻挡层，以将稀疏区域划分成与衬底表面相邻的第一部分和与稀疏区域的底部相邻的第二部分。该孔阻挡层的面积密度为4.0×10 12 cm -2以下，能够使耗尽层穿过该阻挡层，从而能够抑制击穿性的降低。

3. 发明申请

US20120146091A1 INSULATED GATE SEMICONDUCTOR DEVICE 有权
标题翻译：绝缘栅半导体器件
公开(公告)号：US20120146091A1
公开(公告)日：2012-06-14
申请号：US13313050
申请日：2011-12-07
申请人： Hiromitsu Tanabe , Yukio Tsuzuki , Kenji Kouno , Tomofusa Shiga
发明人： Hiromitsu Tanabe , Yukio Tsuzuki , Kenji Kouno , Tomofusa Shiga
IPC分类号： H01L29/739
CPC分类号： H01L29/7397 , H01L29/0696 , H01L29/1095 , H01L29/36 , H01L29/4236 , H01L29/66348
摘要： An insulated gate semiconductor device includes a first conductivity-type semiconductor substrate, a second conductivity-type base layer on a first surface side of the substrate, a trench dividing the base layer into channel and floating layers, and a first conductivity-type emitter region that is formed in the channel layer and in contact with the trench. The semiconductor device includes a gate insulation layer in the trench, a gate electrode on the insulation layer, an emitter electrode electrically connected to the emitter region and the floating layer, a second conductivity-type collector layer in the substrate, and a collector electrode on the collector layer. The floating layer has a lower impurity concentration than the channel layer. The floating layer has a first conductivity-type hole stopper layer located at a predetermined depth from the first surface of the substrate and at least partially spaced from the insulation layer.
摘要翻译：绝缘栅半导体器件包括第一导电型半导体衬底，在衬底的第一表面侧上的第二导电型基极层，将基极层分为沟道和浮动层的沟槽，以及第一导电型发射极区域其形成在沟道层中并与沟槽接触。半导体器件包括沟槽中的栅极绝缘层，绝缘层上的栅极电极，电连接到发射极区域和浮置层的发射极电极，衬底中的第二导电型集电极层，以及集电极电极集电极层。浮置层的杂质浓度低于沟道层。浮动层具有位于距离基板的第一表面预定深度并且至少部分地与绝缘层间隔开的第一导电型孔阻挡层。

4. 发明申请

US20110254051A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20110254051A1
公开(公告)日：2011-10-20
申请号：US13171115
申请日：2011-06-28
申请人： Yukio Tsuzuki , Makoto Asai
发明人： Yukio Tsuzuki , Makoto Asai
IPC分类号： H01L27/06 , H01L21/82
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0619 , H01L29/0696 , H01L29/1095 , H01L29/41766 , H01L29/66727 , H01L29/66734 , H01L29/7397 , H01L29/7806
摘要： A semiconductor device includes an n-conductive type semiconductor substrate having a main side and a rear side, a p-conductive type layer arranged over the main side of the substrate, a main side n-conductive type region arranged in the p-conductive type layer, a rear side n-conductive type layer arranged over the rear side of the substrate, a first trench which reaches the substrate and penetrates the main side n-conductive type region and the p-conductive type layer, a second trench which reaches an inside of the p-conductive type layer, a second electrode layer, which is embedded in the second trench and connected to the p-conductive type layer. Hereby, the semiconductor device, in which the recovery property of a diode cell can be improved without damaging the property of a MOS transistor cell or an IGBT cell and the surge withstand property does not deteriorate, can be obtained.
摘要翻译：半导体器件包括具有主侧和后侧的n导电型半导体衬底，布置在衬底的主侧上的p导电型层，以p导电型布置的主侧n导电型区域层，布置在基板的后侧上的后侧n导电型层，到达基板并穿透主侧n导电型区域和p导电型层的第一沟槽，到达基板的第二沟槽在p导电型层的内部，嵌入在第二沟槽中并连接到p导电型层的第二电极层。因此，可以获得其中二极管电池的恢复特性可以在不损害MOS晶体管单元或IGBT单元的性能而不损坏浪涌耐受性的情况下得到的半导体器件。

5. 发明申请

US20110193132A1 INSULATED GATE SEMICONDUCTOR DEVICE 有权
标题翻译：绝缘栅半导体器件
公开(公告)号：US20110193132A1
公开(公告)日：2011-08-11
申请号：US13010307
申请日：2011-01-20
申请人： Kenji Kouno , Yukio Tsuzuki
发明人： Kenji Kouno , Yukio Tsuzuki
IPC分类号： H01L29/739
CPC分类号： H01L29/7397 , H01L29/0619 , H01L29/0696 , H01L29/7391 , H01L29/7393 , H01L29/7394
摘要： An insulated gate semiconductor device includes a semiconductor substrate, channel regions, floating regions, an emitter region, a body region, a hole stopper layer, and an emitter electrode. The channel regions and the floating regions are repeatedly arranged such that at least one floating region is located between adjacent channel regions. The emitter region and the body region are located in a surface portion of each channel region. The body region is deeper than the emitter region. The hole stopper layer is located in each floating region to divide the floating region into a first region and a second region. The emitter electrode is electrically connected to the emitter region and the first region.
摘要翻译：绝缘栅半导体器件包括半导体衬底，沟道区，浮置区，发射区，体区，空穴阻挡层和发射极。沟道区域和浮置区域被重复布置，使得至少一个浮动区域位于相邻沟道区域之间。发射极区域和体区域位于每个沟道区域的表面部分中。身体区域比发射极区域更深。空穴阻挡层位于每个浮动区域中，以将浮动区域划分成第一区域和第二区域。发射极电极与发射极区域和第一区域电连接。

6. 发明申请

US20070215898A1 Semiconductor device having IGBT element 有权
标题翻译：具有IGBT元件的半导体器件
公开(公告)号：US20070215898A1
公开(公告)日：2007-09-20
申请号：US11714201
申请日：2007-03-06
申请人： Yoshihiko Ozeki , Yukio Tsuzuki
发明人： Yoshihiko Ozeki , Yukio Tsuzuki
IPC分类号： H01L29/74
CPC分类号： H01L29/0619 , H01L29/7397
摘要： A semiconductor device having an insulated gate bipolar transistor (IGBT) is formed on a semiconductor substrate. Abase region and an emitter are formed on a first surface of the substrate while a collector layer is formed on second surface of the substrate. A region having a low breakdown voltage is formed on the first surface around the IGBT, and a carrier collecting region is formed in the vicinity of the region having the low breakdown voltage. The IGBT is prevented from being broken down due to an avalanche phenomenon, because the breakdown occurs in the region having the low breakdown voltage, and carriers of the breakdown current are collected through the carrier collecting region. The breakdown of the IGBT is further effectively prevented by forming a guard ring for suppressing electric field concentration around the region having the low breakdown voltage.
摘要翻译：在半导体衬底上形成具有绝缘栅双极晶体管（IGBT）的半导体器件。在衬底的第一表面上形成有发光二极管和发射极，同时在衬底的第二表面上形成集电极层。在IGBT周围的第一表面上形成具有低击穿电压的区域，并且在具有低击穿电压的区域附近形成载流子收集区域。由于在具有低击穿电压的区域中发生击穿，因此防止IGBT由于雪崩现象而分解，并且通过载流子收集区域收集击穿电流的载流子。通过形成用于抑制具有低击穿电压的区域周围的电场浓度的保护环，进一步有效地防止了IGBT的击穿。

7. 发明申请

US20060244053A1 Trench gate type semiconductor device 有权
标题翻译：沟槽型半导体器件
公开(公告)号：US20060244053A1
公开(公告)日：2006-11-02
申请号：US11398551
申请日：2006-04-06
申请人： Yukio Tsuzuki , Norihito Tokura , Yoshihiko Ozeki , Kensaku Yamamoto
发明人： Yukio Tsuzuki , Norihito Tokura , Yoshihiko Ozeki , Kensaku Yamamoto
IPC分类号： H01L29/76
CPC分类号： H01L29/7397 , H01L29/1095 , H01L29/42376 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: a first semiconductor layer; a second semiconductor layer on the first semiconductor layer; a third semiconductor layer on the second semiconductor layer; a fourth semiconductor layer in a part of the third semiconductor layer; a trench penetrating the fourth semiconductor layer and the third semiconductor layer and reaching the second semiconductor layer; a gate insulation film on an inner wall of the trench; a gate electrode on the gate insulation film in the trench; a first electrode; and a second electrode. The trench includes a bottom with a curved surface having a curvature radius equal to or smaller than 0.5 μm.
摘要翻译：一种半导体器件包括：第一半导体层; 在所述第一半导体层上的第二半导体层; 第二半导体层上的第三半导体层; 在所述第三半导体层的一部分中的第四半导体层; 穿过第四半导体层和第三半导体层并到达第二半导体层的沟槽; 沟槽内壁上的栅极绝缘膜; 在沟槽中的栅极绝缘膜上的栅电极; 第一电极; 和第二电极。沟槽包括具有曲率半径等于或小于0.5μm的曲面的底部。

8. 发明授权

US07126187B2 Semiconductor device and a method of producing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07126187B2
公开(公告)日：2006-10-24
申请号：US10635490
申请日：2003-08-07
申请人： Takaaki Aoki , Yukio Tsuzuki
发明人： Takaaki Aoki , Yukio Tsuzuki
IPC分类号： H01L29/76
CPC分类号： H01L29/7811 , H01L21/28194 , H01L21/28202 , H01L29/045 , H01L29/0696 , H01L29/1095 , H01L29/4238 , H01L29/513 , H01L29/518 , H01L29/7397 , H01L29/7813
摘要： A semiconductor device includes a semiconductor substrate, a cell region in a surface portion of the substrate for operating as a transistor, a gate lead wiring region having a gate lead pattern on the substrate, a trench in the surface portion of the substrate extending from the cell region to the gate lead wiring region, an oxide film on an inner surface of the trench, and a gate electrode in the trench insulated with at least the oxide film from the substrate. A speed of formation of a main portion of the sidewalls of the trench at the gate lead wiring region is greater than that of a main portion of the sidewalls of the trench at the cell region, so that a thickness of the oxide film at the gate lead wiring region is greater than that at the cell region.
摘要翻译：半导体器件包括半导体衬底，用于作为晶体管操作的衬底的表面部分中的单元区域，在衬底上具有栅极引线图案的栅极引线布线区域，从衬底的表面部分延伸的沟槽沟槽的内表面上的氧化膜，以及沟槽中的栅电极，至少与衬底的氧化膜绝缘。在栅极引线布线区域处沟槽的侧壁的主要部分的形成速度大于在单元区域处的沟槽的侧壁的主要部分的速度，使得栅极处的氧化物膜的厚度引线布线区域大于单元区域。

9. 发明申请

US20060128100A1 Semiconductor device and a method of producing the same 有权
公开(公告)号：US20060128100A1
公开(公告)日：2006-06-15
申请号：US11345310
申请日：2006-02-02
申请人： Takaaki Aoki , Yukio Tsuzuki
发明人： Takaaki Aoki , Yukio Tsuzuki
IPC分类号： H01L21/336
CPC分类号： H01L29/7811 , H01L21/28194 , H01L21/28202 , H01L29/045 , H01L29/0696 , H01L29/1095 , H01L29/4238 , H01L29/513 , H01L29/518 , H01L29/7397 , H01L29/7813
摘要： A semiconductor device includes a semiconductor substrate, a cell region in a surface portion of the substrate for operating as a transistor, a gate lead wiring region having a gate lead pattern on the substrate, a trench in the surface portion of the substrate extending from the cell region to the gate lead wiring region, an oxide film on an inner surface of the trench, and a gate electrode in the trench insulated with at least the oxide film from the substrate. A speed of formation of a main portion of the sidewalls of the trench at the gate lead wiring region is greater than that of a main portion of the sidewalls of the trench at the cell region, so that a thickness of the oxide film at the gate lead wiring region is greater than that at the cell region.

10. 发明申请

US20050161735A1 Method of producing a semiconductor device 有权
标题翻译：半导体装置的制造方法
公开(公告)号：US20050161735A1
公开(公告)日：2005-07-28
申请号：US11087758
申请日：2005-03-24
申请人： Takaaki Aoki , Yukio Tsuzuki
发明人： Takaaki Aoki , Yukio Tsuzuki
IPC分类号： H01L29/78 , H01L21/28 , H01L29/06 , H01L29/12 , H01L29/51 , H01L29/739 , H01L29/76 , H01L21/336
CPC分类号： H01L29/7811 , H01L21/28194 , H01L21/28202 , H01L29/045 , H01L29/0696 , H01L29/1095 , H01L29/4238 , H01L29/513 , H01L29/518 , H01L29/7397 , H01L29/7813
摘要： A semiconductor device includes a semiconductor substrate, a cell region in a surface portion of the substrate for operating as a transistor, a gate lead wiring region having a gate lead pattern on the substrate, a trench in the surface portion of the substrate extending from the cell region to the gate lead wiring region, an oxide film on an inner surface of the trench, and a gate electrode in the trench insulated with at least the oxide film from the substrate. A speed of formation of a main portion of the sidewalls of the trench at the gate lead wiring region is greater than that of a main portion of the sidewalls of the trench at the cell region, so that a thickness of the oxide film at the gate lead wiring region is greater than that at the cell region.
摘要翻译：半导体器件包括半导体衬底，用于作为晶体管操作的衬底的表面部分中的单元区域，在衬底上具有栅极引线图案的栅极引线布线区域，从衬底的表面部分延伸的沟槽沟槽的内表面上的氧化膜，以及沟槽中的栅电极，至少与衬底的氧化膜绝缘。在栅极引线布线区域处沟槽的侧壁的主要部分的形成速度大于在单元区域处的沟槽的侧壁的主要部分的速度，使得栅极处的氧化物膜的厚度引线布线区域大于单元区域。

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