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    • 1. 发明授权
    • Structure and manufacturing method for thin-film semiconductor diode
device
    • 薄膜半导体二极管器件的结构和制造方法
    • US5136348A
    • 1992-08-04
    • US647194
    • 1991-01-28
    • Yukio TsuzukiMasami YamaokaHiroshi Muto
    • Yukio TsuzukiMasami YamaokaHiroshi Muto
    • H01L27/06H01L27/12H01L29/04H01L29/78H01L29/861
    • H01L29/7804H01L27/0688H01L27/12H01L29/04H01L29/861Y10S257/926
    • A structure and manufacturing method for a thin film semiconductor device consisting of a single diode or a plurality of diodes connected in series, the device being formed of at least one pair of mutually adjacent P-type (23a) and N-type (23b) regions formed in a layer of polycrystalline silicon (23) deposited on an insulating film (22) upon a substrate (21), to thereby define at least one PN junction. Each of the p-type regions and N-type regions is shaped as a rectangle, with opposite ends of each PN junction formed between these regions being respectively defined by two opposing sides of the polycrystalline silicon layer. Since each of the PN junctions is substantially rectilinear, an even distribution of current flow through each PN junction is attained, whereby a high resistance to destruction and an extremely stable value of reverse bias breakdown voltage are achieved.
    • 一种由串联连接的单个二极管或多个二极管组成的薄膜半导体器件的结构和制造方法,该器件由至少一对相互相邻的P型(23a)和N型(23b)形成, 在衬底(21)上沉积在绝缘膜(22)上的多晶硅层(23)中形成的区域,从而限定至少一个PN结。 每个p型区域和N型区域被成形为矩形,其中形成在这些区域之间的每个PN结的相对端分别由多晶硅层的两个相对侧限定。 由于每个PN结基本上都是直线的,所以能够获得通过每个PN结的电流的平均分布,从而实现了高的抗破坏性和非常稳定的反向偏压击穿电压值。
    • 2. 发明授权
    • High withstanding voltage transistor
    • 高耐压晶体管
    • US5264720A
    • 1993-11-23
    • US879550
    • 1992-05-04
    • Hiroshi MutoMasami Yamaoka
    • Hiroshi MutoMasami Yamaoka
    • H01L27/12H01L27/01H01L29/76
    • H01L27/1203
    • A high withstanding voltage transistor is provided with a substrate with its main surface at least part of which is electrically insulated, and a plurality of MOS type field effect transistors of the same channel type that are formed on the insulated main surface of the substrate, the channel regions of the number of MOS type field effect transistors are electrically separated respectively, the gates of the plurality of MOS type field effect transistors are mutually connected electrically, between and among the plurality of MOS type field effect transistors, the source of one transistor is connected to the drain of another transistor, and connecting in series the plurality of MOS type field effect transistors, they are made into a single transistor, thereby dividing the voltage applied in between the drain and the source of this high withstanding voltage transistor with depletion layer of the respective transistors and in turn improving the withstanding voltage of the whole.
    • 高耐压晶体管设置有其主表面的至少一部分是电绝缘的基板,以及形成在基板的绝缘主表面上的多个相同沟道类型的MOS型场效应晶体管, 多个MOS型场效应晶体管的通道区分别电分离,多个MOS型场效应晶体管的栅极电连接,在多个MOS型场效应晶体管之间和之间相互连接,一个晶体管的源极 连接到另一个晶体管的漏极,并串联连接多个MOS型场效应晶体管,将它们制成单个晶体管,从而将施加在该耐高压晶体管的漏极和源极之间的电压除以耗尽层 并进而改善整体的耐受电压。
    • 3. 发明授权
    • Method for making a polycrystalline diode having high breakdown
    • 制造具有高击穿的多晶二极管的方法
    • US5248623A
    • 1993-09-28
    • US772472
    • 1991-10-07
    • Hiroshi MutoMasami Yamaoka
    • Hiroshi MutoMasami Yamaoka
    • H01L27/06H01L29/861
    • H01L27/0688H01L29/861Y10S148/013
    • A diode which includes a first region formed in a polycrystalline silicon layer formed on a substrate. The diode has a predetermined width W and is one of an intrinsic region and a region including impurities at a low concentration therein, a second region and a third region including P-type impurities and N-type impurities therein respectively and both being oppositely arranged from each other with the first region therebetween in the polycrystalline silicon layer. Electrodes are electrically connected to the second region and the third region respectively, and further the film characteristic of the polycrystalline silicon layer and the predetermined width W thereof are determined in such a manner as to fulfill the following equation:W.sub.D .ltoreq.W.ltoreq.LL represents a carrier diffusion length and W.sub.D represents a width of the depletion layer created in the polycrystalline silicon layer when the voltage corresponding to the withstand voltage required by the polycrystalline diode as mentioned above, is applied thereto.
    • 一种二极管,其包括形成在形成于基板上的多晶硅层中的第一区域。 二极管具有预定的宽度W,并且是本征区域和包括其中低浓度的杂质的区域中的一个,第二区域和分别包括P型杂质和N型杂质的第三区域,并且两者分别从 在多晶硅层中彼此具有第一区域。 电极分别电连接到第二区域和第三区域,并且进一步确定多晶硅层的膜特性和其预定宽度W,以便满足以下等式:WD
    • 4. 发明授权
    • Polycrystalline diode and a method for making the same
    • 多晶二极管及其制造方法
    • US5168337A
    • 1992-12-01
    • US865690
    • 1992-04-08
    • Hiroshi MutoMasami Yamaoka
    • Hiroshi MutoMasami Yamaoka
    • H01L27/06H01L29/861
    • H01L29/861H01L27/0688
    • A diode which includes a first region formed in a polycrystalline silicon layer formed on a substrate. The diode has a predetermined width W and is one of an intrinsic region and a region including impurities at a low concentration therein, a second region and a third region including P-type impurities and N-type impurities therein respectively and both being oppositely arranged from each other with the first region therebetween in the polycrystalline silicon layer. Electrodes are electrically connected to the second region and the third region respectively, and further the film characteristic of the polycrystalline silicon layer and the predetermined width W thereof are determined in such a manner as to fulfill the following equation:W.sub.D .ltoreq.W.ltoreq.LL represents a carrier diffusion length and W.sub.D represents a width of the depletion layer created in the polycrystalline silicon layer when the voltage corresponding to the withstand voltage required by the polycrystalline diode as mentioned above, is applied thereto.
    • 一种二极管,其包括形成在形成于基板上的多晶硅层中的第一区域。 二极管具有预定的宽度W,并且是本征区域和包括其中低浓度的杂质的区域中的一个,第二区域和分别包括P型杂质和N型杂质的第三区域,并且两者分别从 在多晶硅层中彼此具有第一区域。 电极分别电连接到第二区域和第三区域,并且进一步确定多晶硅层的膜特性和其预定宽度W,以便满足以下等式:WD