专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06483737B2 Ferroelectric memory device 有权
公开(公告)号：US06483737B2
公开(公告)日：2002-11-19
申请号：US09956938
申请日：2001-09-21
申请人： Yoshiaki Takeuchi , Sumiko Doumae , Yukihito Oowaki
发明人： Yoshiaki Takeuchi , Sumiko Doumae , Yukihito Oowaki
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A ferroelectric memory device comprises a word line, first and second bit lines cross to the word line, a memory cell including a first transistor a gate of which is coupled to the word line and one of source and drain of which is coupled to the first bit line, a second transistor a gate of which is coupled to the word line and one of source and drain of which is coupled to the second bit line, and a ferroelectric cell capacitor coupled to the other of source and drain of the first and second transistor, and first and second capacitors each coupled via a switching transistor to a respective one of the first and second bit lines, wherein first and second voltages complementary to each other are applied to the first and second bit lines, via the first and second capacitors, respectively.

2. 发明授权

US06611450B2 Ferroelectric random access memory 有权
公开(公告)号：US06611450B2
公开(公告)日：2003-08-26
申请号：US10087837
申请日：2002-03-05
申请人： Yukihito Oowaki , Sumiko Doumae
发明人： Yukihito Oowaki , Sumiko Doumae
IPC分类号： G11C700
CPC分类号： G11C11/22
摘要： A ferroelectric random access memory is disclosed, which comprises a cell array including a plurality of memory cells each having a ferroelectric memory device and a cell selecting transistor connected in series to the ferroelectric storage device, and imprint restricting circuit configured to restrict generation of an imprint by setting a polarization amount of a ferroelectric film of the ferroelectric memory device in the memory cell to an amount smaller than a polarization amount generated at a normal write time.

3. 发明申请

US20060271799A1 Semiconductor device and system 有权
标题翻译：半导体器件和系统
公开(公告)号：US20060271799A1
公开(公告)日：2006-11-30
申请号：US11216018
申请日：2005-09-01
申请人： Shinichiro Shiratake , Yukihito Oowaki , Hiroyuki Hara , Tetsuya Fujita , Fumitoshi Hatori , Masataka Matsui
发明人： Shinichiro Shiratake , Yukihito Oowaki , Hiroyuki Hara , Tetsuya Fujita , Fumitoshi Hatori , Masataka Matsui
IPC分类号： G06F1/26
CPC分类号： G06F1/26 , G06F1/3203 , G06F1/3296 , Y02D10/172
摘要： According to the present invention, there is provided a semiconductor device comprising: a power supply circuit which receives an external power supply voltage supplied, and outputs an internal power supply voltage not higher than the external power supply voltage; a system module which receives the internal power supply voltage, and performs a predetermined operation; and a performance monitor circuit which measures a processing speed of said system module when the internal power supply voltage is applied, and, on the basis of the processing speed, outputs a first control signal which requests to set the external power supply voltage at a first level, and a second control signal which requests said power supply circuit to set the internal power supply voltage at a second level, wherein said power supply circuit outputs the internal power supply voltage having the second level on the basis of the second control signal applied thereto.
摘要翻译：根据本发明，提供了一种半导体器件，包括：电源电路，接收所提供的外部电源电压，并输出不高于外部电源电压的内部电源电压; 接收内部电源电压并执行预定操作的系统模块; 以及性能监视电路，其在施加所述内部电源电压时测量所述系统模块的处理速度，并且基于所述处理速度，输出请求将所述外部电源电压设置为第一的第一控制信号电平和第二控制信号，其请求所述电源电路将内部电源电压设定在第二电平，其中所述电源电路基于施加到其的第二控制信号输出具有第二电平的内部电源电压。

4. 发明授权

US07057917B2 Ferroelectric memory with an intrinsic access transistor coupled to a capacitor 失效
标题翻译：具有耦合到电容器的本征存取晶体管的铁电存储器
公开(公告)号：US07057917B2
公开(公告)日：2006-06-06
申请号：US10743906
申请日：2003-12-24
申请人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
发明人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.
摘要翻译：链式铁电随机存取存储器具有包括彼此串联电连接的铁电存储单元的存储单元单元，连接到存储单元单元的电极的板线，连接到存储单元单元的另一个电极的位线通过开关晶体管，放大该位线及其互补位线的电压的读出放大器，以及插在开关晶体管和读出放大器之间的晶体管。作为板线电压和比较放大的升压期间获得的晶体管中的栅极电压的最小值的值小于在板线掉电期间获得的晶体管中的栅极电压的最大值电压和比较放大。利用这些特征，存储单元中的累积电荷的减小减少，并且在读/写操作期间阻止了干扰的发生。

5. 发明授权

US06643162B2 Ferroelectric memory having a device responsive to current lowering 有权
标题翻译：铁电存储器具有响应于电流降低的装置
公开(公告)号：US06643162B2
公开(公告)日：2003-11-04
申请号：US09799694
申请日：2001-03-07
申请人： Yoshiaki Takeuchi , Yukihito Oowaki
发明人： Yoshiaki Takeuchi , Yukihito Oowaki
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A ferroelectric memory has a memory cell array of memory cells having ferroelectric capacitors, which is divided into a plurality of blocks, a boost power circuit provided in each block of the memory cell array to generate a boost voltage required for operation of the memory, a boost power switch provided between a power line connected to an external power terminal and a power supply terminal of each boost power circuit, and remaining ON during normal operation of the memory, a voltage detector circuit for detecting a drop of voltage level of the power line, and a switch control circuit for turning off the boost power switches in the blocks of the memory cell array excluding the boost power switch in a currently selected block in response to the voltage detector circuit.
摘要翻译：铁电存储器具有具有铁电电容器的存储单元阵列，其被分成多个块，设置在存储单元阵列的每个块中的升压功率电路，以产生存储器的操作所需的升压电压，升压电源开关，其设置在连接到外部电源端子的电力线与每个升压电力电路的电源端子之间，并且在正常操作期间保持ON;电压检测器电路，用于检测电力线的电压水平的下降以及开关控制电路，用于响应于电压检测器电路，关闭当前选择的块中除了升压功率开关之外的存储单元阵列的块中的升压功率开关。

6. 发明授权

US06545323B2 Semiconductor memory device including a pair of MOS transistors forming a detection circuit 失效
标题翻译：半导体存储器件包括形成检测电路的一对MOS晶体管
公开(公告)号：US06545323B2
公开(公告)日：2003-04-08
申请号：US10014662
申请日：2001-12-14
申请人： Yukihito Oowaki , Masako Yoshida , Makoto Yoshimi
发明人： Yukihito Oowaki , Masako Yoshida , Makoto Yoshimi
IPC分类号： H01L2976
CPC分类号： G11C11/4091 , H01L27/10897 , H01L27/12
摘要： A semiconductor device includes a semiconductor layer used as a substrate formed on an insulating film, a plurality of MOS transistors arranged on the semiconductor layer and each having a gate, a source, and a drain, a pair of MOS transistors of the plurality of MOS transistors constituting a detection circuit for detecting magnitudes of potentials applied to the gates as a difference between conductances of the pair of transistors, and a diffusion layer region of the same conductivity type as that of the semiconductor layer, arranged on one of portions of the sources and drains of the pair of MOS transistors constituting the detection circuit, for connecting portions serving as the substrates of the pair of MOS transistors to each other.
摘要翻译：半导体器件包括用作形成在绝缘膜上的衬底的半导体层，布置在半导体层上并且各自具有栅极，源极和漏极的多个MOS晶体管，多个MOS的一对MOS晶体管构成检测电路的晶体管，用于检测施加到栅极的电位的大小，作为一对晶体管的电导率差，以及与半导体层的导电类型相同的导电类型的扩散层区域，布置在源的一部分以及构成检测电路的一对MOS晶体管的漏极，用于将用作一对MOS晶体管的基板的部分彼此连接。

7. 发明授权

US06211686B1 Evaluation apparatus and fabrication system for semiconductor 失效
标题翻译：半导体评估装置及制造系统
公开(公告)号：US06211686B1
公开(公告)日：2001-04-03
申请号：US09126133
申请日：1998-07-30
申请人： Kazuya Matsuzawa , Yukihito Oowaki
发明人： Kazuya Matsuzawa , Yukihito Oowaki
IPC分类号： G01R3126
CPC分类号： G01Q40/00 , H01L22/14 , H01L22/20 , Y10S977/854
摘要： The present invention comprises a SCM measuring apparatus and a control section. A control section adjusts shape data of a probe tip initially inputted based on SCM measurement for a standard specimen and a simulated result by the measuring apparatus, and then performs the SCM measurement by a standard specimen, and then on the basis of the measuring result, a impurity distribution is assumed. Next, the impurity distribution is adjusted so that the CV property calculated by the SCM simulation coincides with the CV property measured by the SCM measuring apparatus, and then the CV property is calculated again. The impurity distribution in case both of the CV properties coincide with each other is determined as a definitive impurity distribution. The definitive impurity distribution is outputted to a display apparatus, a printer, and so on. Therefore, it is possible to analyze the impurity distribution with accuracy smaller than a width of the probe tip.
摘要翻译：本发明包括一个SCM测量装置和一个控制部分。控制部根据标准样本的基于SCM测量的最初输入的探针尖端的形状数据和由测量装置的模拟结果进行调整，然后通过标准样本进行SCM测量，然后基于测量结果，假定杂质分布。接下来，调整杂质分布，使得通过SCM模拟计算的CV性质与由SCM测量装置测量的CV性质一致，然后再次计算CV性质。在两种CV性质彼此一致的情况下的杂质分布被确定为确定的杂质分布。确定的杂质分布被输出到显示装置，打印机等。因此，可以精度小于探针尖端的宽度来分析杂质分布。

8. 发明授权

US06177811B1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US06177811B1
公开(公告)日：2001-01-23
申请号：US09348623
申请日：1999-07-06
申请人： Tsuneaki Fuse , Yukihito Oowaki , Yoko Shuto
发明人： Tsuneaki Fuse , Yukihito Oowaki , Yoko Shuto
IPC分类号： H03K190944
CPC分类号： H03K19/215 , H01L27/1203 , H03K19/09441 , H03K19/0948
摘要： A semiconductor integrated circuit device includes a semiconductor substrate, a MOS transistor formed on the semiconductor substrate and having a first gate, wherein a first signal supplied to the first gate and a second signal supplied to a substrate region corresponding to the semiconductor substrate are combined with each other so that one logical signal is transmitted.
摘要翻译：半导体集成电路器件包括半导体衬底，形成在半导体衬底上并具有第一栅极的MOS晶体管，其中提供给第一栅极的第一信号和提供给对应于半导体衬底的衬底区域的第二信号与使得一个逻辑信号被发送。

9. 发明授权

US5838038A Dynamic random access memory device with the combined open/folded bit-line pair arrangement 失效
标题翻译：具有组合打开/折叠位线对布置的动态随机存取存储器件
公开(公告)号：US5838038A
公开(公告)日：1998-11-17
申请号：US478620
申请日：1995-06-07
申请人： Daisaburo Takashima , Shigeyoshi Watanabe , Tohru Ozaki , Takeshi Hamamoto , Yukihito Oowaki
发明人： Daisaburo Takashima , Shigeyoshi Watanabe , Tohru Ozaki , Takeshi Hamamoto , Yukihito Oowaki
IPC分类号： G11C7/18 , H01L27/108
CPC分类号： G11C7/18 , G11C2211/4013
摘要： A semiconductor memory device includes active regions arranged on a semiconductor substrate such that those of the active regions which are adjacent in the word line direction deviate in the bit line direction, MOS transistors respectively formed in the active regions and each having a source and a drain one of which is connected to the bit line, a plurality of trenches each arranged to another set of source an drain regions and arranged to deviate in the word line direction in the respective active regions, those of the trenches which are adjacent with a through word line disposed therebetween being arranged to deviate in the bit line direction so as to be set closer to each other, a plurality of storage electrodes respectively formed in the trenches with capacitor insulative films disposed therebetween, and connection electrodes arranged between the word lines and each connecting the other of the source and drain to the storage electrode.
摘要翻译：半导体存储器件包括布置在半导体衬底上的有源区域，使得在字线方向上相邻的有源区域在位线方向偏离的有源区域分别形成在有源区域中并且各自具有源极和漏极其中一个连接到位线，多个沟槽，每个沟槽被布置成另一组源极漏极区域，并且被布置成在相应的有源区域中的字线方向偏离，与通过字相邻的沟槽的那些沟槽配置在它们之间的线被布置为在位线方向上偏离以使得彼此更靠近，分别形成在沟槽中的多个存储电极，其中设置有电容器绝缘膜，以及布置在字线和每个连接之间的连接电极另一个源极和漏极到存储电极。

10. 发明授权

US5831928A Semiconductor memory device including a plurality of dynamic memory cells connected in series 失效
标题翻译：半导体存储器件包括串联连接的多个动态存储单元
公开(公告)号：US5831928A
公开(公告)日：1998-11-03
申请号：US744455
申请日：1996-11-07
申请人： Hiroaki Nakano , Takehiro Hasegawa , Yukihito Oowaki
发明人： Hiroaki Nakano , Takehiro Hasegawa , Yukihito Oowaki
IPC分类号： G11C11/401 , G11C7/10 , G11C11/407 , G11C11/409 , G11C11/4096 , G11C8/00
CPC分类号： G11C7/10 , G11C11/4096
摘要： A semiconductor device includes a memory cell array having memory cells arranged in a matrix form, a plurality of bit lines for communicating information to the memory cells, and a plurality of word lines crossing the bit lines to select among the memory cells, a plurality of sense amplifiers for amplifying data read out onto the bit lines, a plurality of data lines for transferring data amplified by the sense amplifiers to the outside of the cell array, the plurality of data lines including first and second wiring layers, a plurality of column select circuits for controlling connections of the plurality of data lines and the plurality of sense amplifiers, and a plurality of control signal lines connected to the plurality of column select circuits, the plurality of control lines including third and fourth wiring layers.
摘要翻译：半导体器件包括具有以矩阵形式布置的存储单元的存储单元阵列，用于向存储单元传送信息的多个位线以及与位线交叉的多条字线以便在存储单元之间进行选择，用于放大读取到位线上的数据的读出放大器，用于将由读出放大器放大的数据传送到单元阵列外部的多条数据线，多条数据线包括第一和第二布线层，多列列选择用于控制多个数据线和多个读出放大器的连接的电路以及连接到多个列选择电路的多个控制信号线，所述多个控制线包括第三和第四布线层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式