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1. 发明授权

US5838038A Dynamic random access memory device with the combined open/folded bit-line pair arrangement 失效
标题翻译：具有组合打开/折叠位线对布置的动态随机存取存储器件
公开(公告)号：US5838038A
公开(公告)日：1998-11-17
申请号：US478620
申请日：1995-06-07
申请人： Daisaburo Takashima , Shigeyoshi Watanabe , Tohru Ozaki , Takeshi Hamamoto , Yukihito Oowaki
发明人： Daisaburo Takashima , Shigeyoshi Watanabe , Tohru Ozaki , Takeshi Hamamoto , Yukihito Oowaki
IPC分类号： G11C7/18 , H01L27/108
CPC分类号： G11C7/18 , G11C2211/4013
摘要： A semiconductor memory device includes active regions arranged on a semiconductor substrate such that those of the active regions which are adjacent in the word line direction deviate in the bit line direction, MOS transistors respectively formed in the active regions and each having a source and a drain one of which is connected to the bit line, a plurality of trenches each arranged to another set of source an drain regions and arranged to deviate in the word line direction in the respective active regions, those of the trenches which are adjacent with a through word line disposed therebetween being arranged to deviate in the bit line direction so as to be set closer to each other, a plurality of storage electrodes respectively formed in the trenches with capacitor insulative films disposed therebetween, and connection electrodes arranged between the word lines and each connecting the other of the source and drain to the storage electrode.
摘要翻译：半导体存储器件包括布置在半导体衬底上的有源区域，使得在字线方向上相邻的有源区域在位线方向偏离的有源区域分别形成在有源区域中并且各自具有源极和漏极其中一个连接到位线，多个沟槽，每个沟槽被布置成另一组源极漏极区域，并且被布置成在相应的有源区域中的字线方向偏离，与通过字相邻的沟槽的那些沟槽配置在它们之间的线被布置为在位线方向上偏离以使得彼此更靠近，分别形成在沟槽中的多个存储电极，其中设置有电容器绝缘膜，以及布置在字线和每个连接之间的连接电极另一个源极和漏极到存储电极。

2. 发明授权

US06993691B2 Series connected TC unit type ferroelectric RAM and test method thereof 失效
公开(公告)号：US06993691B2
公开(公告)日：2006-01-31
申请号：US10120146
申请日：2002-04-11
申请人： Ryu Ogiwara , Daisaburo Takashima , Yukihito Oowaki , Katsuhiko Hoya , Takeshi Watanabe
发明人： Ryu Ogiwara , Daisaburo Takashima , Yukihito Oowaki , Katsuhiko Hoya , Takeshi Watanabe
IPC分类号： G11C29/00
CPC分类号： G11C8/08 , G11C11/22
摘要： Potential of a word line connected to any selected one of memory cells is lowered and potential of word lines connected to non-selected memory cells are raised. The potential of the plate line is raised and lowered. The potential of the bit line is raised and lowered. After this, reading data from the memory cells after potential raising and lowering of the plate line and potential raising and lowering of the bit line have been alternately performed at least one time, thereby to determine attenuation of polarization in the ferroelectric capacitor.

3. 发明授权

US5969998A MOS semiconductor device with memory cells each having storage capacitor and transfer transistor 有权
公开(公告)号：US5969998A
公开(公告)日：1999-10-19
申请号：US213773
申请日：1998-12-17
申请人： Yukihito Oowaki , Daisuke Kato , Daisaburo Takashima
发明人： Yukihito Oowaki , Daisuke Kato , Daisaburo Takashima
IPC分类号： G11C11/407 , G11C7/06 , G11C11/401 , G11C11/409 , G11C11/4091 , G11C11/4096 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C7/00 , G11C11/24
CPC分类号： G11C11/4096 , G11C11/4091 , G11C7/065
摘要： A MOS dynamic random access memory includes a plurality of pairs of bit lines, and word lines transverse to the bit lines to define cross points, at which an array of memory cells are arranged. Each cell has a storage capacitor and a transfer gate MOS transistor having a gate electrode coupled to a word line and being connected between the capacitor and a bit line. Sense amplifier circuits are connected to the bit line pairs, and have a first and a second common source line. A decoder and a word line driver are connected to the word lines. A MOS transistor is connected between the power supply voltage and the first common source line, for selectively supplying it with a first voltage which potentially defines a high-level voltage for the bit line pairs. A voltage generator is connected through a MOS transistor to the second common source line, for generating a second voltage which potentially defines a low-level voltage for the bit line pairs, and which is selectively supplied to the second common source line. The second voltage is greater in potential than the ground potential, which is employed as a source voltage.

4. 发明授权

US07057917B2 Ferroelectric memory with an intrinsic access transistor coupled to a capacitor 失效
标题翻译：具有耦合到电容器的本征存取晶体管的铁电存储器
公开(公告)号：US07057917B2
公开(公告)日：2006-06-06
申请号：US10743906
申请日：2003-12-24
申请人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
发明人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.
摘要翻译：链式铁电随机存取存储器具有包括彼此串联电连接的铁电存储单元的存储单元单元，连接到存储单元单元的电极的板线，连接到存储单元单元的另一个电极的位线通过开关晶体管，放大该位线及其互补位线的电压的读出放大器，以及插在开关晶体管和读出放大器之间的晶体管。作为板线电压和比较放大的升压期间获得的晶体管中的栅极电压的最小值的值小于在板线掉电期间获得的晶体管中的栅极电压的最大值电压和比较放大。利用这些特征，存储单元中的累积电荷的减小减少，并且在读/写操作期间阻止了干扰的发生。

5. 发明授权

US5499209A Integrated semiconductor memory with internal voltage booster of lesser dependency on power supply voltage 失效
标题翻译：具有内部电压增强器的集成半导体存储器对电源电压的依赖性较小
公开(公告)号：US5499209A
公开(公告)日：1996-03-12
申请号：US457738
申请日：1995-06-01
申请人： Yukihito Oowaki , Daisaburo Takashima , Masako Ohta
发明人： Yukihito Oowaki , Daisaburo Takashima , Masako Ohta
IPC分类号： G11C11/407 , G11C11/408 , G11C7/00 , H03K17/687
CPC分类号： G11C11/4085
摘要： A word-line drive voltage generation circuit for use in a dynamic random-access memory is disclosed which is connected to a word line via a row decoder including MOS transistors. The circuit includes a charge-bootstrap capacitor having insulated electrodes, one of which is connected to a first reference voltage generator via a switching MOS transistor, and the other of which is connected via a MOS transistor to a second reference voltage generator. These voltage generators provide the capacitor with the constant d.c. voltage that are essentially insensitive to variation in the power supply voltage for the memory. The resultant word-line drive voltage may thus be free from variation in the power supply voltage during the operation modes of the memory. This enables the word-line voltage to be high enough to allow successful "H" level writing at a selected memory cell without creation of any unwantedly increased dielectric breakdown therein, in the entire allowable range of the power supply voltage.
摘要翻译：公开了一种用于动态随机存取存储器的字线驱动电压产生电路，其通过包括MOS晶体管的行解码器连接到字线。该电路包括具有绝缘电极的电荷自举电容器，其中一个经由开关MOS晶体管连接到第一参考电压发生器，另一个经由MOS晶体管连接到第二参考电压发生器。这些电压发生器为电容器提供恒定的直流电压。对于存储器的电源电压的变化基本上不敏感的电压。因此，在存储器的操作模式期间，所得到的字线驱动电压可能没有电源电压的变化。这使得字线电压足够高，以允许在所选择的存储器单元中成功地“H”电平写入，而不会在电源电压的整个允许范围内产生不必要的增加的电介质击穿。

6. 发明授权

US5084842A Dynamic random access memory with enhanced sense-amplifier circuit 失效
标题翻译：具有增强型SENSE放大器电路的动态随机存取存储器
公开(公告)号：US5084842A
公开(公告)日：1992-01-28
申请号：US536718
申请日：1990-06-12
申请人： Kenji Tsuchida , Yukihito Oowaki , Daisaburo Takashima
发明人： Kenji Tsuchida , Yukihito Oowaki , Daisaburo Takashima
IPC分类号： G11C11/409 , G11C11/401 , G11C11/4091 , G11C11/4094 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10805 , G11C11/4091 , G11C11/4094
摘要： A dynamic random access memory has a substrate, plural pairs of parallel bit lines provided on the substrate, parallel word lines insulatively crossing the parallel bit lines to define cross points therebetween, and memory cells provided at the cross points. Each memory cell has a data storage capacitor and a transistor. Sense amplifiers are provided at bit line pairs, respectively, to sense a data voltage. A discharge control section, which is associated with the sense amplifiers, forms discharge paths branched between the bit line pairs and the substrate grounded to progress the discharging of charges, when a certain word line is designated and a memory cell is selected from those memory cells which are connected to the certain word line, whereby the operational speed of the memory is increased.
摘要翻译：动态随机存取存储器具有衬底，设置在衬底上的多对并行位线，并行字线绝对地穿过并行位线以限定它们之间的交叉点，以及设置在交叉点处的存储单元。每个存储单元具有数据存储电容器和晶体管。分别在位线对处提供感测放大器以感测数据电压。与读出放大器相关联的放电控制部分在指定某个字线并且从那些存储器单元中选择存储器单元时，形成在位线对和衬底之间分支的放电路径，从而导致电荷的放电其连接到某个字线，由此增加存储器的操作速度。

7. 发明授权

US5062077A Dynamic type semiconductor memory device 失效
标题翻译：动态型半导体存储器件
公开(公告)号：US5062077A
公开(公告)日：1991-10-29
申请号：US556470
申请日：1990-07-24
申请人： Daisaburo Takashima , Yukihito Oowaki , Kenji Tsuchida
发明人： Daisaburo Takashima , Yukihito Oowaki , Kenji Tsuchida
IPC分类号： G11C7/02 , G11C7/18 , G11C11/4097 , H01L27/108
CPC分类号： G11C7/18 , G11C11/4097 , H01L27/10805
摘要： A dynamic-type semiconductor memory device comprises bit lines, every two bit lines forming a folded bit line pair, every two pairs forming a bit-line unit such that one of the bit lines of the first pair extends between the bit lines of the second pair, and the bit lines of the second pair are twisted at middle portion, word lines intersecting with the bit lines, dummy word lines, extending parallel to the word lines, two of the dummy word lines being arranged on one side of the crossing portions of the bit lines of the second pair, and the other two of the dummy word lines being arranged on the other side of the crossing portions of the bit lines of the second pair, memory cells connected to selected ones of the intersections of the bit lines and the word lines, such that any adjacent memory cells connected to the same word line form a group which is arranged every two bit lines, and any adjacent two memory cells connected to the same bit line are shifted by half-pitch distance with respect to the corresponding two adjacent memory cells connected to either adjacent bit line, a plurality of dummy cells connected to selected ones of the intersections of the bit lines and the word lines, such that at least one dummy cell is connected to each bit line, and sense amplifiers provided for the pairs of bit lines, respectively.
摘要翻译：动态型半导体存储器件包括位线，每两条位线形成折叠位线对，每两对形成位线单元，使得第一对的位线中的一条在第二对的位线之间延伸并且第二对的位线在中间部分被扭曲，与位线相交的字线，与字线平行延伸的虚拟字线，两个虚拟字线被布置在交叉部分的一侧并且另外两个虚拟字线被布置在第二对的位线的交叉部分的另一侧上，连接到位线的所选交叉点中的所选位置的存储器单元和字线，使得连接到相同字线的任何相邻的存储单元形成每两位排布置的组，并且连接到同一位线的任何相邻的两个存储单元偏移半间距距离，相对于连接到相邻位线的相应的两个相邻存储单元，连接到位线和字线的所选交叉的多个虚拟单元，使得至少一个虚设单元连接到每个位线，以及分别为位线对提供的读出放大器。

8. 发明申请

US20080285327A1 Ferroelectric Memory and Semiconductor Memory 审中-公开
标题翻译：铁电存储器和半导体存储器
公开(公告)号：US20080285327A1
公开(公告)日：2008-11-20
申请号：US11934399
申请日：2007-11-02
申请人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
发明人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
IPC分类号： G11C11/22 , G11C11/401
CPC分类号： G11C11/22
摘要： A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.
摘要翻译：链式铁电随机存取存储器具有包括彼此串联电连接的铁电存储单元的存储单元单元，连接到存储单元单元的电极的板线，连接到存储单元单元的另一个电极的位线通过开关晶体管，放大该位线及其互补位线的电压的读出放大器以及插在开关晶体管和读出放大器之间的晶体管。作为板线电压和比较放大的升压期间获得的晶体管中的栅极电压的最小值的值小于在板线掉电期间获得的晶体管中的栅极电压的最大值电压和比较放大。利用这些特征，存储单元中的累积电荷的减小减少，并且在读/写操作期间阻止了干扰的发生。

9. 发明授权

US07303965B2 MIS transistor and method for producing same 失效
标题翻译： MIS晶体管及其制造方法
公开(公告)号：US07303965B2
公开(公告)日：2007-12-04
申请号：US09879208
申请日：2001-06-13
申请人： Yukihito Oowaki , Mizuki Ono , Mitsuhiro Noguchi , Daisaburo Takashima , Akira Nishiyama
发明人： Yukihito Oowaki , Mizuki Ono , Mitsuhiro Noguchi , Daisaburo Takashima , Akira Nishiyama
IPC分类号： H01L21/33 , H01L21/3205 , H01L31/00
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/66621 , H01L29/78
摘要： In a MIS transistor, the top surfaces of source/drain regions (S/D diffusion layers) formed on a semiconductor substrate 1 are arranged nearer to a gate electrode than a channel plane on the semiconductor substrate, and the top surfaces of the source/drain regions are arranged nearer than the channel plane than the interface between a gate insulator film provided on the upper side of the channel plane and the gate electrode. In this transistor, a groove is selectively formed in the surface of the semiconductor substrate, and a polycrystalline silicon deposited in the groove may be used as a mask to form impurity diffusion layers serving as source/drain regions to laminate and form a gate insulator film of a high dielectric film and a gate electrode. Alternatively, the polycrystalline silicon may be selectively formed to be used as a mask to elevate and form the impurity diffusion layer to laminate and form the gate insulator film and the gate electrode. Thus, it is possible to achieve both of the reduction of the resistance of the S/D diffusion layers and the reduction of the gate parasitic capacitance.
摘要翻译：在MIS晶体管中，形成在半导体基板1上的源极/漏极区域（S / D扩散层）的上表面布置成比半导体衬底上的沟道平面更靠近栅电极，源极/漏极区域的顶表面漏区比布置在沟道平面上侧的栅极绝缘膜与栅电极之间的界面更靠近沟道平面。在该晶体管中，在半导体衬底的表面中选择性地形成沟槽，并且可以将沉积在沟槽中的多晶硅用作掩模，以形成用作源极/漏极区域的杂质扩散层，以层压并形成栅极绝缘膜的高介电膜和栅电极。或者，可以选择性地形成多晶硅以用作掩模以升高和形成杂质扩散层以层压并形成栅极绝缘膜和栅电极。因此，可以实现S / D扩散层的电阻的降低和栅极寄生电容的降低。

10. 发明授权

US06671200B2 Ferroelectric random access memory with isolation transistors coupled between a sense amplifier and an equalization circuit 有权
标题翻译：铁电随机存取存储器，其隔离晶体管耦合在读出放大器和均衡电路之间
公开(公告)号：US06671200B2
公开(公告)日：2003-12-30
申请号：US10372886
申请日：2003-02-26
申请人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
发明人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A chain type ferroelectric random access memory has a memory cell unit comprising ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier, and that a value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.
摘要翻译：链式铁电随机存取存储器具有包括彼此串联电连接的铁电存储单元的存储单元单元，连接到存储单元单元的电极的板线，连接到存储单元单元的另一个电极的位线通过开关晶体管，放大该位线及其互补位线的电压的读出放大器以及插在开关晶体管和读出放大器之间的晶体管，并且作为栅极电压的最小值在板线电压升高和比较放大期间获得的晶体管的晶体管小于作为板线电压下降期间获得的晶体管中的栅极电压的最大值和比较放大的值。利用这些特征，存储单元中的累积电荷的减小减少，并且在读/写操作期间阻止了干扰的发生。

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