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1. 发明授权

US5188073A Fluid control valve, valve support member therefor and idling air amount control apparatus for automobile using the fluid control valve 失效
标题翻译：流体控制阀，阀支撑构件和用于使用流体控制阀的汽车的空转空气量控制装置
公开(公告)号：US5188073A
公开(公告)日：1993-02-23
申请号：US909682
申请日：1992-07-07
申请人： Yuki Ejiri , Tsutomu Okazaki , Koichiro Yamada , Chiaki Niida , Hiroaki Saeki , Hideki Honma
发明人： Yuki Ejiri , Tsutomu Okazaki , Koichiro Yamada , Chiaki Niida , Hiroaki Saeki , Hideki Honma
IPC分类号： F02M3/07
CPC分类号： F02M3/075
摘要： A fluid control valve which regulates a flow rate of a liquid and, more particularly, which controls a fluid by axially moving a valve body fixed to a valve shaft. The fluid control valve comprises a device for absorbing vibrations of the valve shaft in a direction perpendicular to the axis thereof. More specifically, there is provided a device for exerting a pressing force to lightly press the valve shaft against the inner walls of bearings. Alternatively, the valve shaft may be held between a plurality of elastic plates fixed on the inner surface of a valve casing. A support member for such a valve shaft used in the fluid control valve comprises a disk having a center hole through which the valve shaft is inserted, an annular member formed around the disk, and an elastic piece one end of which is secured to the disk or the annular member, while the other end of the elastic piece is extended to the vicinity of the center of the hole, so that the annular member is fixed on the inner surface of the valve casing, and that the distal end of the elastic piece is pressed against the valve shaft which is extended through the hole. According to the invention, vibrations of the center shaft in radial directions can be suppressed to prevent unstable movements of the valve.
摘要翻译：一种流体控制阀，其调节液体的流速，更具体地，其通过轴向移动固定到阀轴的阀体来控制流体。流体控制阀包括用于吸收阀轴在垂直于其轴线的方向上的振动的装置。更具体地，提供了一种用于施加按压力以轻轻地将阀轴压靠在轴承的内壁上的装置。或者，阀轴可以保持在固定在阀壳体的内表面上的多个弹性板之间。用于流体控制阀中的这种阀轴的支撑构件包括具有中心孔的盘，阀轴穿过该中心孔，形成在盘周围的环形构件，弹性件的一端固定在盘或环形构件，而弹性片的另一端延伸到孔的中心附近，使得环形构件固定在阀壳的内表面上，并且弹性片的远端被压在通过孔延伸的阀轴上。根据本发明，可以抑制中心轴在径向上的振动，以防止阀的不稳定运动。

2. 发明授权

US08618804B2 Chuck mechanism of charge/discharge testing device for flat-rechargeable batteries 有权
标题翻译：用于平板充电电池的充放电测试装置的卡盘机构
公开(公告)号：US08618804B2
公开(公告)日：2013-12-31
申请号：US13161928
申请日：2011-06-16
申请人： Takashi Nishihara , Takahiro Kawasaki , Tsutomu Okazaki , Takeshi Yasooka , Hiroaki Habe , Yoshikazu Niwa
发明人： Takashi Nishihara , Takahiro Kawasaki , Tsutomu Okazaki , Takeshi Yasooka , Hiroaki Habe , Yoshikazu Niwa
IPC分类号： G01N27/416
CPC分类号： H01M10/4285 , G01R31/3641 , H01M2/1061 , H01M2/20 , H01M10/4207
摘要： The present invention relates to a chuck mechanism of a charge/discharge testing device for flat-rechargeable batteries and has a proposition to provide a chuck mechanism that makes it possible to lighten conventionally needed troublesome works, that is, for example, works of storing and fixing a large number of flat-rechargeable batteries in a container, and that is capable of surely chucking the flat-rechargeable batteries (electrodes). The chuck mechanism includes a first guide engageable with a battery pressing member of a battery storage which moves according to a battery storage width of a plurality of flat-rechargeable batteries stored in parallel in the battery storage, a plurality of chuck units arranged in parallel by being resiliently and continuously joined and having the first guide on one end side, and a second guide mounted on each of the chuck units, wherein a chuck width of all of the chuck units resiliently arranged in parallel is adjusted according to the battery storage width of the flat-rechargeable batteries by an engagement of the first guide and the battery pressing member, and the second guide positions each of the chuck units being adjusted according to the battery storage width with corresponding flat-rechargeable batteries in the battery storage.
摘要翻译：本发明涉及一种用于平面可再充电电池的充电/放电测试装置的卡盘机构，并且具有提供一种卡盘机构的命题，该卡盘机构能够减轻常规需要的麻烦的作品，例如存储和将大量的可再充电电池固定在容器中，并且能够可靠地夹持可再充电电池（电极）。卡盘机构包括：第一引导件，其与电池存储器的电池按压部件接合，该电池按压部件根据电池存储器中并联存储的多个平面可再充电电池的电池存储宽度而移动;多个卡盘单元，弹性地连续地连接并且在一端侧具有第一引导件，以及安装在每个卡盘单元上的第二引导件，其中平行地弹性布置的所有卡盘单元的卡盘宽度根据电池存储宽度通过第一引导件和电池按压构件的接合，可再充电电池，以及第二引导位置，每个卡盘单元根据电池存储宽度被调整，并且电池存储器中的相应的可平面可再充电电池。

3. 发明申请

US20130113494A1 CHUCK MECHANISM OF CHARGE-DISCHARGE TEST DEVICE FOR THIN SECONDARY BATTERY 有权
标题翻译：用于二次电池充电放电测试装置的机构
公开(公告)号：US20130113494A1
公开(公告)日：2013-05-09
申请号：US13809770
申请日：2011-06-20
申请人： Takashi Nishihara , Takahiro Kawasaki , Tsutomu Okazaki , Takeshi Yasooka , Yoshikazu Niwa
发明人： Takashi Nishihara , Takahiro Kawasaki , Tsutomu Okazaki , Takeshi Yasooka , Yoshikazu Niwa
IPC分类号： G01R31/36
CPC分类号： H01M10/482 , G01R31/3627 , H01M10/4285
摘要： The present invention relates to a chuck mechanism of a charge-discharge test device for a thin secondary battery, and aims to provide a chuck mechanism having excellent action controllability. The chuck mechanism includes: a chuck drive part which is movable in a direction toward a battery container housing a thin secondary battery; and a chuck activation part which is located away from the chuck drive part in the direction toward the battery container and whose movement in the same direction is restricted. In the chuck mechanism, when the chuck unit is moved in the direction toward the battery container, the chuck drive part activates a chuck member of the chuck activation part whose movement in the same direction is restricted.
摘要翻译：本发明涉及一种用于薄型二次电池的充放电试验装置的卡盘机构，其目的在于提供一种具有优异动作可控性的卡盘机构。卡盘机构包括：卡盘驱动部，其能够朝向容纳薄二次电池的电池容器的方向移动; 以及卡盘驱动部，其朝向电池容器的方向远离卡盘驱动部，并且其相同方向的移动受到限制。在卡盘机构中，当卡盘单元沿着朝向电池容器的方向移动时，卡盘驱动部件启动卡盘活动部件的相同方向的运动被限制的卡盘部件。

4. 发明授权

US07371631B2 Method of manufacturing a nonvolatile semiconductor memory device, and a nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件的制造方法以及非易失性半导体存储器件
公开(公告)号：US07371631B2
公开(公告)日：2008-05-13
申请号：US11168639
申请日：2005-06-29
申请人： Takeshi Sakai , Yasushi Ishii , Tsutomu Okazaki , Masaru Nakamichi , Toshikazu Matsui , Kyoya Nitta , Satoru Machida , Munekatsu Nakagawa , Yuichi Tsukada
发明人： Takeshi Sakai , Yasushi Ishii , Tsutomu Okazaki , Masaru Nakamichi , Toshikazu Matsui , Kyoya Nitta , Satoru Machida , Munekatsu Nakagawa , Yuichi Tsukada
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L21/823842 , H01L21/82385 , H01L21/823857 , H01L21/823864 , H01L27/105 , H01L27/1052 , H01L27/11573
摘要： For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.
摘要翻译：为了增强具有MONOS型晶体管的非易失性半导体存储器件的高性能，非易失性半导体存储器件被提供有具有改进性能的MONOS型晶体管，其中MONOS非易失性存储器的存储单元包括控制晶体管和存储晶体管。控制晶体管的控制栅极包括n型多晶硅膜，并且形成在包括氧化硅膜的栅极绝缘膜上。存储晶体管的存储栅极包括n型多晶硅膜，并设置在控制栅极的一个侧壁上。存储器栅极包括具有低于控制栅极的薄层电阻的掺杂多晶硅膜，其包括通过将杂质离子注入未掺杂的硅膜形成的多晶硅膜。

5. 发明申请

US20070164342A1 Semiconductor memory device and method of manufacturing the same 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20070164342A1
公开(公告)日：2007-07-19
申请号：US11651965
申请日：2007-01-11
申请人： Tsutomu Okazaki , Motoi Ashida , Hiroji Ozaki , Tsuyoshi Koga , Daisuke Okada , Masamichi Matsuoka
发明人： Tsutomu Okazaki , Motoi Ashida , Hiroji Ozaki , Tsuyoshi Koga , Daisuke Okada , Masamichi Matsuoka
IPC分类号： H01L29/76
CPC分类号： H01L29/42324 , H01L27/115 , H01L27/11521 , H01L29/40114
摘要： A polysilicon film forming a memory gate interconnection and the like includes a part extending from a part positioned on one side surface of a control gate interconnection to a side opposite to a side where the control gate interconnection is positioned, and that part serves as a pad portion. A contact hole is formed to expose the pad portion. The height of a part of the polysilicon film that is positioned on one side surface of the control gate interconnection is set equal to or lower than the height of the control gate interconnection so that the polysilicon film forming a memory gate interconnection and the like does not two-dimensionally overlap the control gate interconnection. Therefore, a semiconductor memory device with increased process margin can be obtained.
摘要翻译：形成存储器栅互连等的多晶硅膜包括从位于控制栅互连的一个侧表面上的部分延伸到与控制栅互连的一侧相对的一侧的部分，并且该部分用作焊盘一部分。形成接触孔以露出焊盘部分。位于控制栅极互连的一个侧面上的多晶硅膜的一部分的高度设定为等于或低于控制栅极互连的高度，使得形成存储器栅互连等的多晶硅膜不会二维重叠控制门互连。因此，可以获得具有增加的工艺裕量的半导体存储器件。

6. 发明授权

US07095074B2 Semiconductor device with reduced memory leakage current 有权
标题翻译：具有减少内存泄漏电流的半导体器件
公开(公告)号：US07095074B2
公开(公告)日：2006-08-22
申请号：US10196166
申请日：2002-07-17
申请人： Keisuke Tsukamoto , Yoshihiro Ikeda , Tsutomu Okazaki , Daisuke Okada , Hiroshi Yanagita
发明人： Keisuke Tsukamoto , Yoshihiro Ikeda , Tsutomu Okazaki , Daisuke Okada , Hiroshi Yanagita
IPC分类号： H01L29/76 , H01L29/788
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11543
摘要： Defects in element forming regions on which memory cells of a non-volatile memory are formed are to be diminished to reduce leakage current. End portions of element forming regions with non-volatile memory cells formed thereon are extended a length D by utilizing the region which underlies a dummy conductive film, whereby a stress induced from an insulating film which surrounds the element forming regions is concentrated on the extended region. As a result, defects do not extend up to the regions where memory cells are formed and therefore it is possible to reduce leakage current in the memory cells.
摘要翻译：在其上形成非易失性存储器的存储单元的元件形成区域中的缺陷将被减小以减少泄漏电流。在其上形成有非易失性存储单元的元件形成区域的端部通过利用虚设导电膜下面的区域而延伸长度D，由此围绕元件形成区域的绝缘膜引起的应力集中在延伸区域上。结果，缺陷不延伸到形成存储单元的区域，因此可以减少存储单元中的漏电流。

7. 发明授权

US07636253B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07636253B2
公开(公告)日：2009-12-22
申请号：US12354867
申请日：2009-01-16
申请人： Tsutomu Okazaki , Daisuke Okada , Kyoya Nitta , Toshihiro Tanaka , Akira Kato , Toshikazu Matsui , Yasushi Ishii , Digh Hisamoto , Kan Yasui
发明人： Tsutomu Okazaki , Daisuke Okada , Kyoya Nitta , Toshihiro Tanaka , Akira Kato , Toshikazu Matsui , Yasushi Ishii , Digh Hisamoto , Kan Yasui
IPC分类号： G11C11/34
CPC分类号： H01L27/1157 , G11C16/0425 , H01L21/28282 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L29/0649 , H01L29/4234 , H01L29/42344 , H01L29/518 , H01L29/66833 , H01L29/792
摘要： A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.
摘要翻译：半导体存储器阵列包括具有第一电荷存储层和第一非易失性存储单元的第一非易失性存储单元，第一非易失性存储单元与第一存储单元相邻，具有第二电荷存储层和第二栅电极。第一电极和第二电极在垂直于第一方向的第二方向上延伸，第一电极具有在第一方向上朝向第二电极延伸的第一接触部分，并且第二电极具有朝向第一电极的第二接触部分第一个方向第一和第二接触位置分别沿第二方向移动，第一电极和第一接触部分与第二电极和第二接触部分电气分离。

8. 发明申请

US20070201272A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20070201272A1
公开(公告)日：2007-08-30
申请号：US11797164
申请日：2007-05-01
申请人： Tsutomu Okazaki , Daisuke Okada , Kyoya Nitta , Toshihiro Tanaka , Akira Kato , Toshikazu Matsui , Yasushi Ishii , Digh Hisamoto , Kan Yasui
发明人： Tsutomu Okazaki , Daisuke Okada , Kyoya Nitta , Toshihiro Tanaka , Akira Kato , Toshikazu Matsui , Yasushi Ishii , Digh Hisamoto , Kan Yasui
IPC分类号： G11C16/04
CPC分类号： H01L27/1157 , G11C16/0425 , H01L21/28282 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L29/0649 , H01L29/4234 , H01L29/42344 , H01L29/518 , H01L29/66833 , H01L29/792
摘要： A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.
摘要翻译：半导体存储器阵列包括具有第一电荷存储层和第一非易失性存储单元的第一非易失性存储单元，第一非易失性存储单元与第一存储单元相邻，具有第二电荷存储层和第二栅电极。第一电极和第二电极在垂直于第一方向的第二方向上延伸，第一电极具有在第一方向上朝向第二电极延伸的第一接触部分，并且第二电极具有朝向第一电极的第二接触部分第一个方向第一和第二接触位置分别沿第二方向移动，第一电极和第一接触部分与第二电极和第二接触部分电气分离。

9. 发明申请

US20070155153A1 Semiconductor device having electrode and manufacturing method thereof 失效
标题翻译：具有电极的半导体装置及其制造方法
公开(公告)号：US20070155153A1
公开(公告)日：2007-07-05
申请号：US11649208
申请日：2007-01-04
申请人： Tsutomu Okazaki , Motoi Ashida , Hiroji Ozaki , Tsuyoshi Koga , Daisuke Okada
发明人： Tsutomu Okazaki , Motoi Ashida , Hiroji Ozaki , Tsuyoshi Koga , Daisuke Okada
IPC分类号： H01L21/44
CPC分类号： H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/66833 , H01L29/792
摘要： A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.
摘要翻译：半导体器件的制造方法包括：第一电极形成步骤，在控制栅电极和半导体衬底之间形成控制栅极电极，该控制栅电极在半导体衬底的表面上方，控制栅绝缘膜，形成存储节点绝缘膜，以及在存储节点绝缘膜的表面上形成存储栅电极的第二电极形成步骤。第二电极形成步骤包括在存储节点绝缘膜的表面上形成存储栅极电极层的步骤，在表面上形成蚀刻速率慢于存储栅电极层的蚀刻速率的辅助膜的步骤的存储栅电极层和对存储栅电极层和辅助膜进行各向异性蚀刻的步骤。

10. 发明授权

US07015090B2 Method of manufacturing a semiconductor device having trenches for isolation and capacitor formation trenches 有权
标题翻译：制造具有用于隔离沟槽和电容器形成沟槽的半导体器件的方法
公开(公告)号：US07015090B2
公开(公告)日：2006-03-21
申请号：US10408353
申请日：2003-04-08
申请人： Tsutomu Okazaki , Daisuke Okada , Yoshihiro Ikeda , Keisuke Tsukamoto , Tatsuya Fukumura , Shoji Shukuri , Keiichi Haraguchi , Koji Kishi
发明人： Tsutomu Okazaki , Daisuke Okada , Yoshihiro Ikeda , Keisuke Tsukamoto , Tatsuya Fukumura , Shoji Shukuri , Keiichi Haraguchi , Koji Kishi
IPC分类号： H01L21/8248
CPC分类号： H01L27/11536 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L29/66181 , H01L29/7833
摘要： At least not less than one capacitor formation trench providing an uneven surface is formed on the surface of a capacitor formation region. Thus, the surface area of a capacitor is increased, which enables improvement of the capacitance of the capacitor per unit area. Further, by forming the capacitor formation trench and an element formation trench that are formed in the surface of the semiconductor substrate by the same step, it is possible to simplify the manufacturing process. Whereas, a dielectric film of the capacitor in the capacitor formation region and a high-voltage gate insulating film in a MISFET formation region are formed by the same step; alternatively, the dielectric film of the capacitor in the capacitor formation region and a memory gate interlayer film between a polysilicon layer and a polysilicon layer in the memory cell formation region are formed by the same step.
摘要翻译：在电容器形成区域的表面上形成至少不少于一个形成凹凸表面的电容器形成沟槽。因此，电容器的表面积增加，这能够提高每单位面积的电容器的电容。此外，通过形成通过相同的步骤形成在半导体衬底的表面中的电容器形成沟槽和元件形成沟槽，可以简化制造工艺。而电容器形成区域中的电容器的电介质膜和MISFET形成区域中的高压栅极绝缘膜通过相同的步骤形成; 或者，电容器形成区域中的电容器的电介质膜和存储单元形成区域中的多晶硅层和多晶硅层之间的存储器栅极层间膜通过相同的步骤形成。

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