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1. 发明申请

US20070164342A1 Semiconductor memory device and method of manufacturing the same 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20070164342A1
公开(公告)日：2007-07-19
申请号：US11651965
申请日：2007-01-11
申请人： Tsutomu Okazaki , Motoi Ashida , Hiroji Ozaki , Tsuyoshi Koga , Daisuke Okada , Masamichi Matsuoka
发明人： Tsutomu Okazaki , Motoi Ashida , Hiroji Ozaki , Tsuyoshi Koga , Daisuke Okada , Masamichi Matsuoka
IPC分类号： H01L29/76
CPC分类号： H01L29/42324 , H01L27/115 , H01L27/11521 , H01L29/40114
摘要： A polysilicon film forming a memory gate interconnection and the like includes a part extending from a part positioned on one side surface of a control gate interconnection to a side opposite to a side where the control gate interconnection is positioned, and that part serves as a pad portion. A contact hole is formed to expose the pad portion. The height of a part of the polysilicon film that is positioned on one side surface of the control gate interconnection is set equal to or lower than the height of the control gate interconnection so that the polysilicon film forming a memory gate interconnection and the like does not two-dimensionally overlap the control gate interconnection. Therefore, a semiconductor memory device with increased process margin can be obtained.
摘要翻译：形成存储器栅互连等的多晶硅膜包括从位于控制栅互连的一个侧表面上的部分延伸到与控制栅互连的一侧相对的一侧的部分，并且该部分用作焊盘一部分。形成接触孔以露出焊盘部分。位于控制栅极互连的一个侧面上的多晶硅膜的一部分的高度设定为等于或低于控制栅极互连的高度，使得形成存储器栅互连等的多晶硅膜不会二维重叠控制门互连。因此，可以获得具有增加的工艺裕量的半导体存储器件。

2. 发明授权

US07939448B2 Semiconductor device having electrode and manufacturing method thereof 失效
标题翻译：具有电极的半导体装置及其制造方法
公开(公告)号：US07939448B2
公开(公告)日：2011-05-10
申请号：US12888995
申请日：2010-09-23
申请人： Tsutomu Okazaki , Motoi Ashida , Hiroji Ozaki , Tsuyoshi Koga , Daisuke Okada
发明人： Tsutomu Okazaki , Motoi Ashida , Hiroji Ozaki , Tsuyoshi Koga , Daisuke Okada
IPC分类号： H01L21/311
CPC分类号： H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/66833 , H01L29/792
摘要： A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.
摘要翻译：半导体器件的制造方法包括：第一电极形成步骤，在控制栅电极和半导体衬底之间形成控制栅极电极，该控制栅电极在半导体衬底的表面上方，控制栅绝缘膜，形成存储节点绝缘膜，以及在存储节点绝缘膜的表面上形成存储栅电极的第二电极形成步骤。第二电极形成步骤包括在存储节点绝缘膜的表面上形成存储栅极电极层的步骤，在表面上形成蚀刻速率慢于存储栅电极层的蚀刻速率的辅助膜的步骤的存储栅电极层和对存储栅电极层和辅助膜进行各向异性蚀刻的步骤。

3. 发明授权

US07816207B2 Semiconductor device having electrode and manufacturing method thereof 失效
标题翻译：具有电极的半导体装置及其制造方法
公开(公告)号：US07816207B2
公开(公告)日：2010-10-19
申请号：US12719524
申请日：2010-03-08
申请人： Tsutomu Okazaki , Motoi Ashida , Hiroji Ozaki , Tsuyoshi Koga , Daisuke Okada
发明人： Tsutomu Okazaki , Motoi Ashida , Hiroji Ozaki , Tsuyoshi Koga , Daisuke Okada
IPC分类号： H01L21/336
CPC分类号： H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/66833 , H01L29/792
摘要： A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.
摘要翻译：半导体器件的制造方法包括：第一电极形成步骤，在控制栅电极和半导体衬底之间形成控制栅极电极，该控制栅电极在半导体衬底的表面上方，控制栅绝缘膜，形成存储节点绝缘膜，以及在存储节点绝缘膜的表面上形成存储栅电极的第二电极形成步骤。第二电极形成步骤包括在存储节点绝缘膜的表面上形成存储栅极电极层的步骤，在表面上形成蚀刻速率慢于存储栅电极层的蚀刻速率的辅助膜的步骤的存储栅电极层和对存储栅电极层和辅助膜进行各向异性蚀刻的步骤。

4. 发明授权

US07709874B2 Semiconductor device having a split gate structure with a recessed top face electrode 失效
标题翻译：具有具有凹入的顶面电极的分离栅极结构的半导体器件
公开(公告)号：US07709874B2
公开(公告)日：2010-05-04
申请号：US11649208
申请日：2007-01-04
申请人： Tsutomu Okazaki , Motoi Ashida , Hiroji Ozaki , Tsuyoshi Koga , Daisuke Okada
发明人： Tsutomu Okazaki , Motoi Ashida , Hiroji Ozaki , Tsuyoshi Koga , Daisuke Okada
IPC分类号： H01L29/94
CPC分类号： H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/66833 , H01L29/792
摘要： A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.
摘要翻译：半导体器件的制造方法包括：第一电极形成步骤，在控制栅电极和半导体衬底之间形成控制栅极电极，该控制栅电极在半导体衬底的表面上方，控制栅绝缘膜，形成存储节点绝缘膜，以及在存储节点绝缘膜的表面上形成存储栅电极的第二电极形成步骤。第二电极形成步骤包括在存储节点绝缘膜的表面上形成存储栅极电极层的步骤，在表面上形成蚀刻速率慢于存储栅电极层的蚀刻速率的辅助膜的步骤的存储栅电极层和对存储栅电极层和辅助膜进行各向异性蚀刻的步骤。

5. 发明申请

US20110014783A1 SEMICONDUCTOR DEVICE HAVING ELECTRODE AND MANUFACTURING METHOD THEREOF 失效
标题翻译：具有电极的半导体器件及其制造方法
公开(公告)号：US20110014783A1
公开(公告)日：2011-01-20
申请号：US12888995
申请日：2010-09-23
申请人： Tsutomu OKAZAKI , Motoi Ashida , Hiroji Ozaki , Tsuyoshi Koga , Daisuke Okada
发明人： Tsutomu OKAZAKI , Motoi Ashida , Hiroji Ozaki , Tsuyoshi Koga , Daisuke Okada
IPC分类号： H01L21/283
CPC分类号： H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/66833 , H01L29/792
摘要： A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.
摘要翻译：半导体器件的制造方法包括：第一电极形成步骤，在控制栅电极和半导体衬底之间形成控制栅极电极，该控制栅电极在半导体衬底的表面上方，控制栅绝缘膜，形成存储节点绝缘膜，以及在存储节点绝缘膜的表面上形成存储栅电极的第二电极形成步骤。第二电极形成步骤包括在存储节点绝缘膜的表面上形成存储栅极电极层的步骤，在表面上形成蚀刻速率慢于存储栅电极层的蚀刻速率的辅助膜的步骤的存储栅电极层和对存储栅电极层和辅助膜进行各向异性蚀刻的步骤。

6. 发明申请

US20100159687A1 SEMICONDUCTOR DEVICE HAVING ELECTRODE AND MANUFACTURING METHOD THEREOF 失效
标题翻译：具有电极的半导体器件及其制造方法
公开(公告)号：US20100159687A1
公开(公告)日：2010-06-24
申请号：US12719524
申请日：2010-03-08
申请人： Tsutomu OKAZAKI , Motoi Ashida , Hiroji Ozaki , Tsuyoshi Koga , Daisuke Okada
发明人： Tsutomu OKAZAKI , Motoi Ashida , Hiroji Ozaki , Tsuyoshi Koga , Daisuke Okada
IPC分类号： H01L21/28
CPC分类号： H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/66833 , H01L29/792
摘要： A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.
摘要翻译：半导体器件的制造方法包括：第一电极形成步骤，在控制栅电极和半导体衬底之间形成控制栅极电极，该控制栅电极在半导体衬底的表面上方，控制栅绝缘膜，形成存储节点绝缘膜，以及在存储节点绝缘膜的表面上形成存储栅电极的第二电极形成步骤。第二电极形成步骤包括在存储节点绝缘膜的表面上形成存储栅极电极层的步骤，在表面上形成蚀刻速率慢于存储栅电极层的蚀刻速率的辅助膜的步骤的存储栅电极层和对存储栅电极层和辅助膜进行各向异性蚀刻的步骤。

7. 发明申请

US20070155153A1 Semiconductor device having electrode and manufacturing method thereof 失效
标题翻译：具有电极的半导体装置及其制造方法
公开(公告)号：US20070155153A1
公开(公告)日：2007-07-05
申请号：US11649208
申请日：2007-01-04
申请人： Tsutomu Okazaki , Motoi Ashida , Hiroji Ozaki , Tsuyoshi Koga , Daisuke Okada
发明人： Tsutomu Okazaki , Motoi Ashida , Hiroji Ozaki , Tsuyoshi Koga , Daisuke Okada
IPC分类号： H01L21/44
CPC分类号： H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/66833 , H01L29/792
摘要： A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.
摘要翻译：半导体器件的制造方法包括：第一电极形成步骤，在控制栅电极和半导体衬底之间形成控制栅极电极，该控制栅电极在半导体衬底的表面上方，控制栅绝缘膜，形成存储节点绝缘膜，以及在存储节点绝缘膜的表面上形成存储栅电极的第二电极形成步骤。第二电极形成步骤包括在存储节点绝缘膜的表面上形成存储栅极电极层的步骤，在表面上形成蚀刻速率慢于存储栅电极层的蚀刻速率的辅助膜的步骤的存储栅电极层和对存储栅电极层和辅助膜进行各向异性蚀刻的步骤。

8. 发明授权

US06615097B2 Production management system 失效
标题翻译：生产管理系统
公开(公告)号：US06615097B2
公开(公告)日：2003-09-02
申请号：US09764131
申请日：2001-01-19
申请人： Hiroji Ozaki
发明人： Hiroji Ozaki
IPC分类号： G06F1900
CPC分类号： G05B17/02 , Y02P80/40 , Y02P90/26
摘要： A production management system has a plurality of pieces of production apparatus, a production controller connected online to the production apparatus, and a simulator. The simulator performs a simulation of physical distribution for a specified period of time through use of a simulation parameter, apparatus information, and process information, which are acquired from the production controller. A re-simulation of physical distribution is performed while taking, as parameters for optimizing physical distribution, time-series data pertaining to the availability factor of each apparatus and the load factor of each apparatus obtained as a result of the simulation, as well as the start and termination times of an event which is to arise in the period of a simulation. A dispatch rule set for each apparatus or a group of pieces of apparatus having a single function is dynamically changed, thus feeding back the change to control of real physical distribution.
摘要翻译：生产管理系统具有多个生产设备，在生产设备上连接的生产控制器和模拟器。模拟器通过使用从生产控制器获取的模拟参数，装置信息和过程信息来在特定时间段内进行物理分布的模拟。在进行物理分配的重新模拟的同时，作为用于优化物理分布的参数，与每个装置的可用性因子有关的时间序列数据和作为模拟结果获得的每个装置的负载因子，以及在模拟期间将出现的事件的起始和终止时间。对于具有单个功能的每个装置或一组装置的调度规则集被动态地改变，从而将改变反馈到实际物理分布的控制。

9. 发明授权

US5940300A Method and apparatus for analyzing a fabrication line 失效
标题翻译：用于分析制造线的方法和装置
公开(公告)号：US5940300A
公开(公告)日：1999-08-17
申请号：US854019
申请日：1997-05-08
申请人： Hiroji Ozaki
发明人： Hiroji Ozaki
IPC分类号： H01L21/66 , G05B23/02 , G06F19/00 , G06F7/66
CPC分类号： G05B23/0264
摘要： Measurement result data obtained by the devices (A1 to A8) are stored in databases (C1 to C8). Every time new data are entered in any of the databases (C1 to C8), a database monitoring computer (E1) retrieves data related to the entered data from the data stored in the databases (C1 to C8) and stores the retrieved data in a failure analysis database (D3). A data analysis system (D0) gives a readout from the failure analysis database (D3) to an operator. The operator can thereby judge that some nonconforming defect is found and what the cause of nonconforming defect is even while the product wafer is on a fabrication line, to make a prompt remedy against the cause of nonconforming defect. Thus, a method and an apparatus for analyzing a fabrication line can be provided, allowing a prompt remedy against the cause of nonconforming defect.
摘要翻译：由设备（A1〜A8）获得的测量结果数据存储在数据库（C1〜C8）中。每当新数据输入到任何数据库（C1至C8）中时，数据库监控计算机（E1）从数据库（C1至C8）中存储的数据中检索与输入数据相关的数据，并将检索到的数据存储在故障分析数据库（D3）。数据分析系统（D0）给出了从故障分析数据库（D3）向操作者的读出。因此，操作者可以判断出产品晶片处于生产线上时发现了一些不合格的缺陷，以及不符合缺陷的原因甚至是什么，以便对不符合的缺陷的原因作出迅速的补救。因此，可以提供用于分析制造线的方法和装置，从而可以快速地补救不合格缺陷的原因。

10. 发明授权

US5097310A Complementary semiconductor device having improved device isolating region 失效
标题翻译：具有改进的器件隔离区域的补充半导体器件
公开(公告)号：US5097310A
公开(公告)日：1992-03-17
申请号：US409379
申请日：1989-09-19
申请人： Takahisa Eimori , Wataru Wakamiya , Hiroji Ozaki , Yoshinori Tanaka , Shinichi Satoh
发明人： Takahisa Eimori , Wataru Wakamiya , Hiroji Ozaki , Yoshinori Tanaka , Shinichi Satoh
IPC分类号： H01L21/761 , H01L21/76 , H01L27/08 , H01L27/092 , H01L29/78
CPC分类号： H01L27/0928
摘要： A complementary semiconductor device having an improved capability of isolating devices comprises a P well 3 and an N well 2 both formed adjacent to each other on a main surface of a substrate 1, an N type impurity layer formed in the P well 8 on the main surface of the substrate, a P type impurity layer formed in the N well 9 on the main surface of the substrate, an N type region formed at the junction of the N well and the P well 71 on the main surface of the substrate, a first shield electrode 52 formed between the N type impurity layer 8 and the N type region 71 on the main surface of the substrate through an insulating film and a second shield electrode 51 formed between the N type region 71 and the P type impurity layer 9 on the main surface of the substrate through an insulating film. The first shield electrode 52 is connected to a potential V.sub.SS and the second shield electrode 51 and the N type region 71 are connected to a potential V.sub.CC, so that an N channel MOS transistor 101 comprising the first shield electrode 52 does not turn on and a device comprising the second shield electrode does not form a field effect transistor.
摘要翻译：具有改进的隔离装置能力的互补半导体器件包括在衬底1的主表面上彼此相邻形成的P阱3和N阱2，形成在主衬底1上的P阱8中的N型杂质层在基板的主表面上形成在N阱9中的P型杂质层，形成在基板主表面上的N阱和P阱71的接合部的N型区域，第一屏蔽电极52，其通过绝缘膜形成在基板的主表面上的N型杂质层8和N型区域71之间，形成在N型区域71和P型杂质层9之间的第二屏蔽电极51，基板的主表面通过绝缘膜。第一屏蔽电极52连接到电位VSS，第二屏蔽电极51和N型区域71连接到电位VCC，使得包括第一屏蔽电极52的N沟道MOS晶体管101不导通，包括第二屏蔽电极的装置不形成场效应晶体管。

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