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1. 发明申请

US20080094905A1 Nonvolatile Memory 有权
标题翻译：非易失性存储器
公开(公告)号：US20080094905A1
公开(公告)日：2008-04-24
申请号：US11952693
申请日：2007-12-07
申请人： Koji Kishi , Hideaki Kurata , Satoshi Noda , Yusuke Jono
发明人： Koji Kishi , Hideaki Kurata , Satoshi Noda , Yusuke Jono
IPC分类号： G11C16/06
CPC分类号： G11C16/0491 , G11C16/0425 , G11C16/0458 , G11C16/10 , G11C16/26
摘要： A nonvolatile memory includes circuits each having first control transistors, memory transistors, second control transistors and memory transistors repeatedly connected in series in sequence. Inversion layers are formed in the direction intersecting the serial direction with turning on of the control transistors. A selection circuit selects a connection of the inversion layer placed under the first control transistor and its corresponding read/write circuit. The control transistors placed on both sides adjacent to the memory transistor are turned on to perform reading. The first control transistors placed on both sides of the second control transistor as viewed from side to side are turned on to perform writing into the other of the right and left memory transistors via one of the right and left memory transistors. The selection circuit connects the read/write circuit and the inversion layer in such a manner that the same read/write circuit is used in reading and writing for the same memory transistor.
摘要翻译：非易失性存储器包括各自具有依次重复串联连接的第一控制晶体管，存储晶体管，第二控制晶体管和存储器晶体管的电路。在控制晶体管导通时，在与串行方向相交的方向上形成反转层。选择电路选择放置在第一控制晶体管下方的反相层及其对应的读/写电路的连接。放置在与存储晶体管相邻的两侧的控制晶体管被导通以执行读取。放置在从一侧到另一侧观察的第二控制晶体管的两侧上的第一控制晶体管被导通，以通过右和左存储晶体管中的一个来执行向左和右存储晶体管中的另一个的写入。选择电路以这样的方式连接读/写电路和反转层，即在相同存储晶体管的读和写中使用相同的读/写电路。

2. 发明授权

US07015090B2 Method of manufacturing a semiconductor device having trenches for isolation and capacitor formation trenches 有权
标题翻译：制造具有用于隔离沟槽和电容器形成沟槽的半导体器件的方法
公开(公告)号：US07015090B2
公开(公告)日：2006-03-21
申请号：US10408353
申请日：2003-04-08
申请人： Tsutomu Okazaki , Daisuke Okada , Yoshihiro Ikeda , Keisuke Tsukamoto , Tatsuya Fukumura , Shoji Shukuri , Keiichi Haraguchi , Koji Kishi
发明人： Tsutomu Okazaki , Daisuke Okada , Yoshihiro Ikeda , Keisuke Tsukamoto , Tatsuya Fukumura , Shoji Shukuri , Keiichi Haraguchi , Koji Kishi
IPC分类号： H01L21/8248
CPC分类号： H01L27/11536 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L29/66181 , H01L29/7833
摘要： At least not less than one capacitor formation trench providing an uneven surface is formed on the surface of a capacitor formation region. Thus, the surface area of a capacitor is increased, which enables improvement of the capacitance of the capacitor per unit area. Further, by forming the capacitor formation trench and an element formation trench that are formed in the surface of the semiconductor substrate by the same step, it is possible to simplify the manufacturing process. Whereas, a dielectric film of the capacitor in the capacitor formation region and a high-voltage gate insulating film in a MISFET formation region are formed by the same step; alternatively, the dielectric film of the capacitor in the capacitor formation region and a memory gate interlayer film between a polysilicon layer and a polysilicon layer in the memory cell formation region are formed by the same step.
摘要翻译：在电容器形成区域的表面上形成至少不少于一个形成凹凸表面的电容器形成沟槽。因此，电容器的表面积增加，这能够提高每单位面积的电容器的电容。此外，通过形成通过相同的步骤形成在半导体衬底的表面中的电容器形成沟槽和元件形成沟槽，可以简化制造工艺。而电容器形成区域中的电容器的电介质膜和MISFET形成区域中的高压栅极绝缘膜通过相同的步骤形成; 或者，电容器形成区域中的电容器的电介质膜和存储单元形成区域中的多晶硅层和多晶硅层之间的存储器栅极层间膜通过相同的步骤形成。

3. 发明授权

US06986998B2 Method of analyzing components in biological samples 有权
公开(公告)号：US06986998B2
公开(公告)日：2006-01-17
申请号：US10297241
申请日：2001-06-05
申请人： Koji Kishi , Tsutomu Kakuyama , Koji Ochiai
发明人： Koji Kishi , Tsutomu Kakuyama , Koji Ochiai
IPC分类号： C12Q1/60 , C12Q1/44 , C12Q1/26 , C12Q1/28 , G01N33/53
CPC分类号： C12Q1/44 , C12Q1/60 , G01N33/92 , Y10S435/975
摘要： There is provided a method for a selective assay of component, particularly cholesterol, in very low-density lipoprotein (VLDL) which is one of serum lipoproteins.In the assay, an enzymatic reaction of lipoprotein lipase (LPL) or cholesterol esterase (CE) which well reacts with high-density lipoprotein (HDL) and VLDL is carried out at least in the presence of calixarene or a salt thereof. It is also carried out in the presence of one or more substance(s) selected from albumin and basic amino acids in addition to calixarene or a salt thereof.

4. 发明授权

US6114134A Method for assaying biological specimens for substances contained in the components thereof and reagent to be used in this method 有权
标题翻译：用于测定其组分中所含物质的生物样品的方法和用于该方法的试剂
公开(公告)号：US6114134A
公开(公告)日：2000-09-05
申请号：US453474
申请日：1999-12-02
申请人： Koji Kishi , Tsutomu Kakuyama , Yasushi Shirahase , Yoshifumi Watazu
发明人： Koji Kishi , Tsutomu Kakuyama , Yasushi Shirahase , Yoshifumi Watazu
IPC分类号： C12Q1/60 , G01N33/92 , C12Q1/00
CPC分类号： G01N33/92 , C12Q1/60 , Y10S435/975
摘要： A method for assaying biological specimens for substances contained in the components of each specimen by the use of one or more kinds of calixarenes; and a reagent comprising one or more kinds of calixarenes. The method utilizes complexes formed by calixarenes and the components of biological specimens, and makes it possible to assay biological specimens for substances contained in the components of each specimen, for example, for cholesterol contained in high-density lipoprotein (HDL), without preliminary separation from the other components of the biological specimen. The method can be conducted by easy and simple operations and lessen measurement errors or problems caused by man, and permits continuous measurement with general-purpose automatic analyzing apparatuses and multi-channel measurement together with other test items.
摘要翻译：一种通过使用一种或多种杯芳烃来测定每个样品组分中所含物质的生物样品的方法; 和包含一种或多种杯芳烃的试剂。该方法利用由杯芳烃形成的复合物和生物标本的成分，并且可以测定生物标本中各物质组分中所含的物质，例如高密度脂蛋白（HDL）中所含的胆固醇，而无需初步分离从生物样本的其他成分。该方法可以通过简单和简单的操作进行，减少人为测量误差或问题，并允许通用自动分析仪器和多通道测量与其他测试项目连续测量。

5. 发明授权

US07436716B2 Nonvolatile memory 有权
标题翻译：非易失性存储器
公开(公告)号：US07436716B2
公开(公告)日：2008-10-14
申请号：US11952693
申请日：2007-12-07
申请人： Koji Kishi , Hideaki Kurata , Satoshi Noda , Yusuke Jono
发明人： Koji Kishi , Hideaki Kurata , Satoshi Noda , Yusuke Jono
IPC分类号： G11C7/10
CPC分类号： G11C16/0491 , G11C16/0425 , G11C16/0458 , G11C16/10 , G11C16/26
摘要： A nonvolatile memory includes circuits each having first control transistors, memory transistors, second control transistors and memory transistors repeatedly connected in series in sequence. Inversion layers are formed in the direction intersecting the serial direction with turning on of the control transistors. A selection circuit selects a connection of the inversion layer placed under the first control transistor and its corresponding read/write circuit. The control transistors placed on both sides adjacent to the memory transistor are turned on to perform reading. The first control transistors placed on both sides of the second control transistor as viewed from side to side are turned on to perform writing into the other of the right and left memory transistors via one of the right and left memory transistors. The selection circuit connects the read/write circuit and the inversion layer in such a manner that the same read/write circuit is used in reading and writing for the same memory transistor.
摘要翻译：非易失性存储器包括各自具有依次重复串联连接的第一控制晶体管，存储晶体管，第二控制晶体管和存储器晶体管的电路。在控制晶体管导通时，在与串行方向相交的方向上形成反转层。选择电路选择放置在第一控制晶体管下方的反相层及其对应的读/写电路的连接。放置在与存储晶体管相邻的两侧的控制晶体管被导通以执行读取。放置在从一侧到另一侧观察的第二控制晶体管的两侧上的第一控制晶体管被导通，以通过右和左存储晶体管中的一个来执行向左和右存储晶体管中的另一个的写入。选择电路以这样的方式连接读/写电路和反转层，即在相同存储晶体管的读和写中使用相同的读/写电路。

6. 发明授权

US07324388B2 Nonvolatile memory 有权
公开(公告)号：US07324388B2
公开(公告)日：2008-01-29
申请号：US11189977
申请日：2005-07-27
申请人： Koji Kishi , Hideaki Kurata , Satoshi Noda , Yusuke Jono
发明人： Koji Kishi , Hideaki Kurata , Satoshi Noda , Yusuke Jono
IPC分类号： G11C7/10
CPC分类号： G11C16/0491 , G11C16/0425 , G11C16/0458 , G11C16/10 , G11C16/26
摘要： A nonvolatile memory includes circuits each having first control transistors, memory transistors, second control transistors and memory transistors repeatedly connected in series in sequence. Inversion layers are formed in the direction intersecting the serial direction with turning on of the control transistors. A selection circuit selects a connection of the inversion layer placed under the first control transistor and its corresponding read/write circuit. The control transistors placed on both sides adjacent to the memory transistor are turned on to perform reading. The first control transistors placed on both sides of the second control transistor as viewed from side to side are turned on to perform writing into the other of the right and left memory transistors via one of the right and left memory transistors. The selection circuit connects the read/write circuit and the inversion layer in such a manner that the same read/write circuit is used in reading and writing for the same memory transistor.

7. 发明授权

US07208287B2 Reagent set and method for detecting cholesterol in a high-density lipoprotein or low density lipoprotein 失效
标题翻译：用于检测高密度脂蛋白或低密度脂蛋白胆固醇的试剂盒和方法
公开(公告)号：US07208287B2
公开(公告)日：2007-04-24
申请号：US10776970
申请日：2004-02-11
申请人： Koji Kishi , Tsutomu Kakuyama , Koji Ochiai , Yuzo Hasegawa
发明人： Koji Kishi , Tsutomu Kakuyama , Koji Ochiai , Yuzo Hasegawa
IPC分类号： C12Q1/60
CPC分类号： C12Q1/60 , G01N33/92
摘要： A method for quantitating a specific component in lipoproteins contained in a biological sample, for example, HDL (high-density lipoprotein), LDL (low-density lipoprotein) or VLDL (very low-density lipoprotein) by using a commonly employed automatic analyzer without centrifuging or making the reaction liquor cloudy due to complexes or aggregates. Namely, a controlling means, whereby an enzyme reaction can be carried out exclusively for the target component, is introduced into a method for enzymatically assaying a component in a specific lipoprotein fraction in the serum, thereby specifically assaying the component.
摘要翻译：通过使用通常使用的自动分析仪来定量生物样品中所含的脂蛋白中的特定成分的方法，例如HDL（高密度脂蛋白），LDL（低密度脂蛋白）或VLDL（极低密度脂蛋白）），离心或使反应液由于复合物或聚集体而变浑浊。即，将针对目标成分进行酶反应的控制手段导入用于酶分析血清中特定脂蛋白部分中的成分的方法，从而特异性地测定该成分。

8. 发明授权

US07148063B2 Mitochondrial creatine kinase antibody 有权
公开(公告)号：US07148063B2
公开(公告)日：2006-12-12
申请号：US10424740
申请日：2003-04-29
申请人： Yasushi Shirahase , Tadahiro Kajita , Koji Kishi , Kazuaki Yamashita
发明人： Yasushi Shirahase , Tadahiro Kajita , Koji Kishi , Kazuaki Yamashita
IPC分类号： C12N5/20 , C07K16/40 , G01N33/53
CPC分类号： C07K16/40 , Y10S435/975
摘要： The object of the present invention is to provide a method for more accurately assaying the enzyme activities of mCK isozymes and a method for separately assaying the enzyme activities of CK isozymes by separately assaying the enzyme activities of ubiquitous mCK (umCK) and sarcomeric mCK (smCK). The above object is attained by an assay using an antibody that specifically recognizes umCK protein. In addition, other anti-mCK antibodies (e.g., anti-smCK antibody) and/or anti-human CK-M-inhibiting antibody can also be used. The above antibody is a polyclonal antibody or a monoclonal antibody. As a result of these antibodies, a monoclonal antibody (U1-1881) that is capable of specifically recognizing human umCK and is produced by a hybridoma having a deposition number of FERM BP-8342 is provided.

9. 发明申请

US20060033141A1 Method of manufacturing a semiconductor device having trenches for isolation and capacitor 审中-公开
标题翻译：制造具有用于隔离和电容器的沟槽的半导体器件的方法
公开(公告)号：US20060033141A1
公开(公告)日：2006-02-16
申请号：US11248309
申请日：2005-10-13
申请人： Tsutomu Okazaki , Daisuke Okada , Yoshihiro Ikeda , Keisuke Tsukamoto , Tatsuya Fukumura , Shoji Shukuri , Keiichi Haraguchi , Koji Kishi
发明人： Tsutomu Okazaki , Daisuke Okada , Yoshihiro Ikeda , Keisuke Tsukamoto , Tatsuya Fukumura , Shoji Shukuri , Keiichi Haraguchi , Koji Kishi
IPC分类号： H01L29/94 , H01L21/383
CPC分类号： H01L27/11536 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L29/66181 , H01L29/7833
摘要： At least not less than one capacitor formation trench providing an uneven surface is formed on the surface of a capacitor formation region. Thus, the surface area of a capacitor is increased, which enables improvement of the capacitance of the capacitor is increased, which enables improvement of the capacitance of the capacitor per unit area. Further, by forming the capacitor formation trench and an element formation trench that are formed in the surface of the semiconductor substrate by the same step, it is possible to simplify the manufacturing process. Whereas, a dielectric film of the capacitor in the capacitor formation region and a high-voltage insulating film in a MISFET formation region are formed by the same step; alternatively, the dielectric of the capacitor in the capacitor formation region and a memory gate interlayer film between a polysilicon layer and a polysilicon layer in the memory cell formation region are formed by the same step.
摘要翻译：在电容器形成区域的表面上形成至少不少于一个形成凹凸表面的电容器形成沟槽。因此，电容器的表面积增大，能够提高电容器的电容量，能够提高单位面积的电容器的电容。此外，通过形成通过相同的步骤形成在半导体衬底的表面中的电容器形成沟槽和元件形成沟槽，可以简化制造工艺。而通过相同的步骤形成电容器形成区域中的电容器的电介质膜和MISFET形成区域中的高压绝缘膜; 或者，电容器形成区域中的电容器的电介质和存储单元形成区域中的多晶硅层和多晶硅层之间的存储器栅极层间膜通过相同的步骤形成。

10. 发明授权

US06845429B2 Multi-port cache memory 有权
标题翻译：多端口缓存内存
公开(公告)号：US06845429B2
公开(公告)日：2005-01-18
申请号：US09919859
申请日：2001-08-02
申请人： Hans Jurgen Mattausch , Koji Kishi , Nobuhiko Omori
发明人： Hans Jurgen Mattausch , Koji Kishi , Nobuhiko Omori
IPC分类号： G06F12/08 , G11C11/41 , G06F13/00
CPC分类号： G06F12/0853 , G06F12/0846
摘要： The conventional multi-port cache memory, which is formed by using multi-port cells, is excellent in its operating speed. However, the integration area of the constituent multi-port cells is increased in proportion to the square of the number of ports. Thus, if it is intended to decrease the cache miss probability by increasing the storage capacity, the chip size is increased correspondingly, which increases the manufacturing cost. On the other hand, the multi-port cache memory of the present invention is formed by using, as constituents, one-port cell blocks adapted for a large storage capacity, making it possible to easily provide a multi-port cache memory of a large storage capacity and reduced integration area, which has a large random access bandwidth, is capable of parallel access from a plurality of ports, and is adapted for use in advanced microprocessors having a small cache miss probability.
摘要翻译：通过使用多端口单元形成的常规多端口高速缓存存储器的操作速度优异。然而，构成多端口小区的集成区域与端口数的平方成比例地增加。因此，如果旨在通过增加存储容量来降低高速缓存未命中概率，则芯片尺寸相应地增加，这增加了制造成本。另一方面，本发明的多端口高速缓冲存储器是通过使用适合于大存储容量的单端口单元块来构成的，从而可以容易地提供大容量的多端口高速缓冲存储器具有大的随机存取带宽的存储容量和减少的集成区域能够从多个端口并行访问，并且适用于具有小的高速缓存未命中概率的高级微处理器。

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