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    • 1. 发明授权
      US06040597A Isolation boundaries in flash memory cores 失效
    • Isolation boundaries in flash memory cores
    • 闪存内核中的隔离边界
    • US06040597A
    • 2000-03-21
    • US23166
    • 1998-02-13
    • Unsoon Kim , Yowjuang W. Liu , Yu Sun
    • Unsoon Kim , Yowjuang W. Liu , Yu Sun
    • H01L21/762 , H01L29/788
    • H01L21/76232 , H01L21/76237
    • A wet etching process for establishing isolation grooves in a flash memory core wafer includes depositing nitride and/or oxide layers on a silicon substrate of the wafer, depositing a photoresist layer thereon, and then exposing predetermined portions of the photoresist layer to ultraviolet light to establish a desired groove pattern in the photoresist layer. A dry etching process is then used to remove the nitride and/or oxide layers beneath the groove pattern of the photoresist layer to thereby expose portions of the substrate. Next, the wafer is disposed in a wet etching solution such as potassium hydroxide to form grooves in the exposed portions of the silicon substrate. The wafer is oriented and disposed in the bath as appropriate for forming V-shaped grooves, such that after etching, the angled walls of the grooves can be easily exposed to a dopant beam directly above the wafer, without having to tilt the wafer or beam source. Thereby, the walls of the grooves are easily implanted with dopant.
    • 用于在闪速存储器芯晶片中建立隔离槽的湿蚀刻工艺包括在晶片的硅衬底上沉积氮化物和/或氧化物层，在其上沉积光致抗蚀剂层，然后将光致抗蚀剂层的预定部分暴露于紫外光以建立 在光致抗蚀剂层中的期望的凹槽图案。 然后使用干蚀刻工艺去除光致抗蚀剂层的凹槽图案下方的氮化物和/或氧化物层，从而暴露衬底的部分。 接下来，将晶片设置在诸如氢氧化钾的湿蚀刻溶液中，以在硅衬底的暴露部分中形成凹槽。 晶片被定向并适当地设置在浴中以形成V形槽，使得在蚀刻之后，槽的成角度的壁可以容易地暴露于直接在晶片上方的掺杂剂束，而不必使晶片或光束倾斜 资源。 因此，槽的壁容易用掺杂剂注入。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 2. 发明授权
      US5925909A Three-dimensional complementary field effect transistor process and structures 失效
    • Three-dimensional complementary field effect transistor process and structures
    • 三维互补场效应晶体管工艺及结构
    • US5925909A
    • 1999-07-20
    • US555556
    • 1995-11-08
    • Yowjuang W. Liu , Yu Sun
    • Yowjuang W. Liu , Yu Sun
    • H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/423 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
    • H01L29/7834 , H01L21/823487 , H01L21/823885 , H01L27/088 , H01L27/0922 , H01L29/4238 , Y10S148/05
    • A field effect transistor has a short gate and is fabricated by: doping the bottom surface of a depression to form a relatively lightly doped region in the bottom of the depression; forming the gate of the field effect transistor on the sidewall of the depression such that the gate is insulated from the sidewall by a thin insulating layer; and implanting dopants to form the drain region and the source region of the transistor using the gate to mask a part of the relatively lightly doped region. The part of the relatively lightly doped region which is masked by the gate during implanting of the source and drain regions constitutes a lightly doped drain region of the transistor. The drain of the transistor is formed into the bottom of the depression. The length of the gate is primarily determined by the depth and/or profile of the sidewall. The source-to-drain on-resistance of the transistor is low because the transistor does not have a lightly doped source region. The transistor has high quality gate oxide because the sidewall of the depression upon which the gate oxide is grown is substantially free of ion impact damage.
    • 场效应晶体管具有短栅极，并且通过以下方式制造：掺杂凹陷的底表面以在凹陷的底部形成相对轻掺杂的区域; 在凹陷的侧壁上形成场效应晶体管的栅极，使得栅极通过薄绝缘层与侧壁绝缘; 以及使用所述栅极注入掺杂剂以形成所述晶体管的漏极区域和源极区域以掩蔽所述相对轻掺杂区域的一部分。 在注入源极和漏极区域期间被栅极掩蔽的相对轻掺杂区域的部分构成晶体管的轻掺杂漏极区。 晶体管的漏极形成凹陷的底部。 栅极的长度主要由侧壁的深度和/或轮廓确定。 晶体管的源极到漏极导通电阻很低，因为晶体管不具有轻掺杂的源极区域。 晶体管具有高质量的栅极氧化物，因为其上生长栅极氧化物的凹陷的侧壁基本上没有离子冲击损伤。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 5. 发明授权
      US5672524A Three-dimensional complementary field effect transistor process 失效
    • Three-dimensional complementary field effect transistor process
    • 三维互补场效应晶体管工艺
    • US5672524A
    • 1997-09-30
    • US509911
    • 1995-08-01
    • Yowjuang W. Liu , Yu Sun
    • Yowjuang W. Liu , Yu Sun
    • H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/423 , H01L29/78
    • H01L29/7834 , H01L21/823487 , H01L21/823885 , H01L27/088 , H01L27/0922 , H01L29/4238 , Y10S148/05
    • A field effect transistor has a short gate and is fabricated by: doping the bottom surface of a depression to form a relatively lightly doped region in the bottom of the depression; forming the gate of the field effect transistor on the sidewall of the depression such that the gate is insulated from the sidewall by a thin insulating layer; and implanting dopants to form the drain region and the source region of the transistor using the gate to mask a part of the relatively lightly doped region. The part of the relatively lightly doped region which is masked by the gate during implanting of the source and drain regions constitutes a lightly doped drain region of the transistor. The drain of the transistor is formed into the bottom of the depression. The length of the gate is primarily determined by the depth and/or profile of the sidewall. The source-to-drain on-resistance of the transistor is low because the transistor does not have a lightly doped source region. The transistor has high quality gate oxide because the sidewall of the depression upon which the gate oxide is grown is substantially free of ion impact damage.
    • 场效应晶体管具有短栅极，并且通过以下方式制造：掺杂凹陷的底表面以在凹陷的底部形成相对轻掺杂的区域; 在凹陷的侧壁上形成场效应晶体管的栅极，使得栅极通过薄绝缘层与侧壁绝缘; 以及使用所述栅极注入掺杂剂以形成所述晶体管的漏极区域和源极区域以掩蔽所述相对轻掺杂区域的一部分。 在注入源极和漏极区域期间被栅极掩蔽的相对轻掺杂区域的部分构成晶体管的轻掺杂漏极区。 晶体管的漏极形成凹陷的底部。 栅极的长度主要由侧壁的深度和/或轮廓确定。 晶体管的源极到漏极导通电阻很低，因为晶体管不具有轻掺杂的源极区域。 晶体管具有高质量的栅极氧化物，因为其上生长栅极氧化物的凹陷的侧壁基本上没有离子冲击损伤。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 6. 发明授权
      US5612249A Post-gate LOCOS 失效
    • Post-gate LOCOS
    • 门后LOCOS
    • US5612249A
    • 1997-03-18
    • US645844
    • 1996-05-14
    • Yu Sun , Yowjuang W. Liu
    • Yu Sun , Yowjuang W. Liu
    • H01L21/28 , H01L21/336 , H01L21/762 , H01L21/76
    • H01L29/6659 , H01L21/28123 , H01L21/76202 , H01L29/6656
    • A method of defining a local oxidation of silicon (LOCOS) field isolation process after a poly gate is deposited. A gate oxide is grown on a silicon substrate, and then poly or amorphous silicon is deposited. A thin layer of PECVD or LPCVD oxide is deposited on the poly, and LPCVD nitride is then deposited as a hard mask. A device active area is defined by photoresist mask and plasma etch. The layers may either be etched down to the silicon surface, or the silicon surface may be further etched to create a recessed silicon region.An oxide layer is grown on the exposed sidewalls of the poly, and another layer of nitride is deposited. The nitride is etched to form a nitride spacer, and a field oxide is grown. A field isolation implant is formed, followed by stripping the nitride space. The oxide layer is removed, reexposing the poly. Another layer of poly and WSi film is deposited, and gate and interconnects are defined by applying a gate mask and etch. An alternate approach of self-aligned silicide gate, junction and interconnect can be formed without using WSi by depositing Ti after the gate is defined. N-LDD and P-LDD implants are performed by masks, followed by an oxide spacer being formed. N+ and p+ junctions are then formed by separate masks and implants.
    • 在沉积多晶硅栅之后限定硅（LOCOS）场隔离工艺的局部氧化的方法。 在硅衬底上生长栅极氧化物，然后沉积聚硅或非晶硅。 沉积PECVD或LPCVD氧化物薄层，然后沉积LPCVD氮化物作为硬掩模。 器件有源区通过光刻胶掩模和等离子蚀刻来定义。 这些层可以被蚀刻到硅表面，或者可以进一步蚀刻硅表面以产生凹陷的硅区域。 在多晶硅的暴露的侧壁上生长氧化物层，并沉积另一层氮化物。 蚀刻氮化物以形成氮化物间隔物，并且生长场氧化物。 形成场隔离植入物，然后剥离氮化物空间。 去除氧化物层，重新使用聚合物。 沉积另一层poly和WSi膜，并通过施加栅极掩模和蚀刻来限定栅极和互连。 在定义栅极之后，可以通过沉积Ti来形成自对准硅化物栅，结和互连的替代方法，而不使用WSi。 N-LDD和P-LDD植入物通过掩模进行，随后形成氧化物间隔物。 然后通过分开的掩模和植入物形成N +和p +结。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 9. 发明授权
      US06232632B1 Double density non-volatile memory cells 有权
    • Double density non-volatile memory cells
    • 双密度非易失性存储单元
    • US06232632B1
    • 2001-05-15
    • US09436503
    • 1999-11-09
    • Yowjuang W. Liu
    • Yowjuang W. Liu
    • H01L29788
    • H01L27/11553 , H01L27/115
    • Double density non-volatile memory cells having a trench structure are formed in a substrate, thereby facilitating miniaturization, improved planarization and low power programming and erasing. Each double density cell comprises two floating gates and a common control gate. Each pair of double density cells shares a common source region. Embodiments include forming first and second trenches in a substrate and depositing a tunnel dielectric layer in each trench. Polycrystalline silicon is then deposited filling each trench and a hole is etched forming two floating gate electrodes in each trench. An interpoly dielectric layer is then formed and a substantially T-shaped control gate electrode is deposited filling the hole between the floating gates and extending on the substrate.
    • 在衬底中形成具有沟槽结构的双重密度非易失性存储单元，从而便于小型化，改进的平面化和低功率编程和擦除。 每个双密度单元包括两个浮动栅极和公共控制栅极。 每对双密度细胞共享一个共同的源区。 实施例包括在衬底中形成第一和第二沟槽，并在每个沟槽中沉积隧道介电层。 然后沉积多晶硅填充每个沟槽，并且蚀刻孔，在每个沟槽中形成两个浮置栅电极。 然后形成间隔电介质层，并且沉积基本上T形的控制栅极，填充浮置栅极之间的孔并在衬底上延伸。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
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