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1. 发明授权

US07848146B2 Partial local self-boosting of a memory cell channel 有权
标题翻译：部分局部自增强的存储单元通道
公开(公告)号：US07848146B2
公开(公告)日：2010-12-07
申请号：US12407228
申请日：2009-03-19
申请人： Youseok Suh , Ya-Fen Lin , Coling Stewart Bill , Takao Akaogi , Yi-Ching Wu
发明人： Youseok Suh , Ya-Fen Lin , Coling Stewart Bill , Takao Akaogi , Yi-Ching Wu
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/0483
摘要： A method for partial local self-boosting of a memory cell channel is disclosed. As a part of memory cell channel partial local self-boosting, an isolating memory cell located on a source side of a program inhibited memory cell is turned off and a gating memory cell located on a drain side of the program inhibited memory cell is used to pass a pre-charge voltage to the program inhibited memory cell to provide a pre-charge voltage to a channel of the program inhibited memory cell. Moreover, a pre-charge voltage is passed to a buffering memory cell located on the source side of the program inhibited memory cell to provide a pre-charge voltage to a channel of the buffering memory cell and the gating memory cell that is located on the drain side of the program inhibited memory cell is turned off. During programming, a program voltage is applied to the gate of the program inhibited memory cell where a channel voltage of the program inhibited memory cell is raised above a level raised by the pre-charge voltage.
摘要翻译：公开了一种用于存储器单元通道的局部局部自升压的方法。作为存储单元通道部分局部自升压的一部分，位于程序禁止存储单元的源极侧的隔离存储单元被截止，并且位于程序禁止存储单元的漏极侧的门控存储单元被用于将预充电电压传递到程序禁止的存储单元，以向编程禁止的存储单元的通道提供预充电电压。此外，预充电电压被传递到位于程序禁止的存储单元的源极侧的缓冲存储单元，以向缓冲存储单元的通道和位于该存储单元上的选通存储单元提供预充电电压程序的漏极侧禁止存储单元关闭。在编程期间，将程序禁止存储单元的通道电压升高到由预充电电压升高的电平以上的程序禁止存储单元的栅极上施加编程电压。

2. 发明申请

US20100238731A1 PARTIAL LOCAL SELF-BOOSTING OF A MEMORY CELL CHANNEL 有权
标题翻译：记忆体通道的局部自动升压
公开(公告)号：US20100238731A1
公开(公告)日：2010-09-23
申请号：US12407228
申请日：2009-03-19
申请人： Youseok Suh , Ya-Fen Lin , Colin Stewart Bill , Takao Akaogi , Yi-Ching Wu
发明人： Youseok Suh , Ya-Fen Lin , Colin Stewart Bill , Takao Akaogi , Yi-Ching Wu
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/0483
摘要： A method for partial local self-boosting of a memory cell channel is disclosed. As a part of memory cell channel partial local self-boosting, an isolating memory cell located on a source side of a program inhibited memory cell is turned off and a gating memory cell located on a drain side of the program inhibited memory cell is used to pass a pre-charge voltage to the program inhibited memory cell to provide a pre-charge voltage to a channel of the program inhibited memory cell. Moreover, a pre-charge voltage is passed to a buffering memory cell located on the source side of the program inhibited memory cell to provide a pre-charge voltage to a channel of the buffering memory cell and the gating memory cell that is located on the drain side of the program inhibited memory cell is turned off. During programming, a program voltage is applied to the gate of the program inhibited memory cell where a channel voltage of the program inhibited memory cell is raised above a level raised by the pre-charge voltage.
摘要翻译：公开了一种用于存储器单元通道的局部局部自升压的方法。作为存储单元通道部分局部自升压的一部分，位于程序禁止存储单元的源极侧的隔离存储单元被截止，并且位于程序禁止存储单元的漏极侧的门控存储单元被用于将预充电电压传递到程序禁止的存储单元，以向编程禁止的存储单元的通道提供预充电电压。此外，预充电电压被传递到位于程序禁止的存储单元的源极侧的缓冲存储单元，以向缓冲存储单元的通道和位于该存储单元上的选通存储单元提供预充电电压程序的漏极侧禁止存储单元关闭。在编程期间，将程序禁止存储单元的通道电压升高到由预充电电压升高的电平以上的程序禁止存储单元的栅极上施加编程电压。

3. 发明授权

US08638609B2 Partial local self boosting for NAND 有权
标题翻译： NAND的部分本地自增强
公开(公告)号：US08638609B2
公开(公告)日：2014-01-28
申请号：US12783351
申请日：2010-05-19
申请人： Ya-Fen Lin , Colin Bill , Takao Akaogi , Youseok Suh
发明人： Ya-Fen Lin , Colin Bill , Takao Akaogi , Youseok Suh
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C16/0483 , G11C16/10 , G11C16/3418
摘要： A memory system is programmed with minimal program disturb and reduced junction and channel leakage during self-boosting. Pre-charging bias signals are applied to word lines adjacent to a selected word line before a program signal is applied to the selected word line and a pass signal is applied to the remaining word lines. The pre-charging bias signals apply a pre-charge to the memory cells. The pre-charging bias signals are chosen to improve the isolation of the memory cells on word lines adjacent to the selected word line, improve self boost efficiency and reduce current leakage to prevent or reduce program disturb and/or programming errors especially in the inhibited memory cells on the selected word line.
摘要翻译：存储器系统被编程为在自增强期间具有最少的程序干扰和减少的结和通道泄漏。在将程序信号施加到所选择的字线之前，预充电偏置信号被施加到与所选字线相邻的字线，并且将通过信号施加到剩余的字线。预充电偏压信号将预充电施加到存储器单元。选择预充电偏压信号以改善与所选字线相邻的字线上的存储器单元的隔离，提高自升压效率并减少电流泄漏以防止或减少程序干扰和/或编程错误，特别是在禁止的存储器所选字线上的单元格。

4. 发明授权

US08692310B2 Gate fringing effect based channel formation for semiconductor device 有权
标题翻译：基于栅极边缘效应的半导体器件通道形成
公开(公告)号：US08692310B2
公开(公告)日：2014-04-08
申请号：US12368023
申请日：2009-02-09
申请人： YouSeok Suh , Sung-Yong Chung , Ya-Fen Lin , Yi-Ching Wu
发明人： YouSeok Suh , Sung-Yong Chung , Ya-Fen Lin , Yi-Ching Wu
IPC分类号： H01L29/792
CPC分类号： H01L27/11524 , H01L21/28282 , H01L27/11521 , H01L27/11568 , H01L27/1157 , H01L29/4234 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： Methods and structures for forming semiconductor channels based on gate fringing effect are disclosed. In one embodiment, a NAND flash memory device comprises multiple NAND strings of memory transistors. Each memory transistor includes a charge trapping layer and a gate electrode formed on the charge trapping layer. The memory transistors are formed close to each other to form a channel between an adjacent pair of the memory transistors based on a gate fringing effect associated with the adjacent pair of the memory transistors.
摘要翻译：公开了基于栅极边缘效应形成半导体通道的方法和结构。在一个实施例中，NAND闪存器件包括存储器晶体管的多个NAND串。每个存储晶体管包括形成在电荷俘获层上的电荷俘获层和栅电极。基于与相邻的一对存储晶体管相关的栅极边缘效应，存储晶体管彼此靠近形成在相邻的一对存储晶体管之间形成沟道。

5. 发明授权

US07723774B2 Non-diffusion junction split-gate nonvolatile memory cells and arrays, methods of programming, erasing, and reading thereof, and methods of manufacture 有权
标题翻译：非扩散结分离栅极非易失性存储器单元和阵列，其编程，擦除和读取方法以及制造方法
公开(公告)号：US07723774B2
公开(公告)日：2010-05-25
申请号：US11775851
申请日：2007-07-10
申请人： Changyuan Chen , Ya-Fen Lin , Dana Lee
发明人： Changyuan Chen , Ya-Fen Lin , Dana Lee
IPC分类号： H01L29/788
CPC分类号： G11C16/0458 , G11C16/10 , H01L27/115 , H01L27/11521 , H01L29/42328 , H01L29/42336 , H01L29/7887
摘要： Nonvolatile flash memory systems and methods are disclosed having a semiconductor substrate of a first conductivity type, including non-diffused channel regions through which electron flow is induced by application of voltage to associated gate elements. A plurality of floating gates are spaced apart from one another and each insulated from the channel region. A plurality of control gates are spaced apart from one another and insulated from the channel region, with each control gate being located between a first floating gate and a second floating gate and capacitively coupled thereto to form a subcell. A plurality of spaced-apart assist gates are insulated from the channel region, with each assist gate being located between and insulated from adjacent subcells. The channel is formed of three regions, two beneath adjacent control gate elements as well as a third region between the first two and beneath an associated assist gate.
摘要翻译：公开了非挥发性闪速存储器系统和方法，其具有第一导电类型的半导体衬底，包括非扩散沟道区，通过向相关联的栅极元件施加电压而引起电子流。多个浮动栅极彼此间隔开并且与沟道区域绝缘。多个控制栅极彼此间隔开并且与沟道区域绝缘，每个控制栅极位于第一浮动栅极和第二浮动栅极之间，并电容耦合到其上以形成子电池。多个间隔开的辅助栅极与沟道区域绝缘，每个辅助栅极位于相邻子电池之间并且与相邻的子电池绝缘。通道由三个区域组成，两个位于相邻的控制栅极元件下方，以及位于相关联的辅助栅极之间的第一个两个和第二区域之间。

6. 发明申请

US20060166661A1 Wireless communication device having a telephone number-limited back calling function 审中-公开
标题翻译：具有电话号码限制回呼功能的无线通信装置
公开(公告)号：US20060166661A1
公开(公告)日：2006-07-27
申请号：US11041965
申请日：2005-01-26
申请人： Ya-Fen Lin
发明人： Ya-Fen Lin
IPC分类号： H04M3/00
CPC分类号： H04M1/67 , H04M1/677
摘要： A wireless communication device having a number-limited back calling function is disclosed, comprising a receiving module receiving a telephone number corresponding to an in-coming call, a memory storing at least a limited telephone number, a comparison module comparing if the telephone number of the in-coming call is the same as the limited telephone number stored in the memory, a limiting module limiting a back call from being sent to a communication device corresponding to the in-coming call with the limited telephone number if the comparison result is true, and a back calling interface calling back to the telephone number corresponding to the in-coming call if the comparison result is different.
摘要翻译：公开了一种具有数量有限的返回呼叫功能的无线通信装置，包括：接收模块，其接收与进入呼叫相对应的电话号码;至少存储有限电话号码的存储器;比较模块，来电呼叫与存储在存储器中的有限电话号码相同，如果比较结果为真，则限制模块将拒绝呼叫限制为与具有有限电话号码的呼入呼叫相对应的通信设备如果比较结果不同，则返回呼叫接口回呼对应于来电呼叫的电话号码。

7. 发明授权

US07247907B2 Bidirectional split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing 有权
标题翻译：双向分闸门NAND闪存结构和阵列，编程方法，擦除和读取方法以及制造方法
公开(公告)号：US07247907B2
公开(公告)日：2007-07-24
申请号：US11134557
申请日：2005-05-20
申请人： Feng Gao , Ya-Fen Lin , John W. Cooksey , Changyuan Chen , Yuniarto Widjaja , Dana Lee
发明人： Feng Gao , Ya-Fen Lin , John W. Cooksey , Changyuan Chen , Yuniarto Widjaja , Dana Lee
IPC分类号： H01L29/788
CPC分类号： H01L29/42336 , G11C16/0425 , G11C16/0483 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11556 , H01L29/42328
摘要： A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type and a second region of the second conductivity type in the substrate, spaced apart from the first region, thereby defining a channel region therebetween. A plurality of floating gates are spaced apart from one another and each is insulated from the channel region. A plurality of control gates are spaced apart from one another, with each control gate insulated from the channel region. Each of the control gate is between a pair of floating gates and is capacitively coupled to the pair of floating gates. A plurality of select gates are spaced apart from one another, with each select gate insulated from the channel region. Each select gate is between a pair of floating gates.
摘要翻译：在第一导电类型的半导体衬底上形成分离栅极NAND闪速存储器结构。 NAND结构包括第二导电类型的第一区域和第二导电类型的第二区域，与第一区域间隔开，由此在其间限定沟道区域。多个浮动栅极彼此间隔开并且各自与沟道区域绝缘。多个控制栅极彼此间隔开，每个控制栅极与沟道区域绝缘。每个控制栅极位于一对浮动栅极之间，并且电容耦合到该对浮置栅极。多个选择栅极彼此间隔开，每个选择栅极与沟道区域绝缘。每个选择门位于一对浮动门之间。

8. 发明授权

US07242051B2 Split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing 有权
公开(公告)号：US07242051B2
公开(公告)日：2007-07-10
申请号：US11134540
申请日：2005-05-20
申请人： Yuniarto Widjaja , John W. Cooksey , Changyuan Chen , Feng Gao , Ya-Fen Lin , Dana Lee
发明人： Yuniarto Widjaja , John W. Cooksey , Changyuan Chen , Feng Gao , Ya-Fen Lin , Dana Lee
IPC分类号： H01L29/788
CPC分类号： G11C16/0425 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/26 , G11C16/3431 , G11C2216/18 , H01L21/28273 , H01L27/115 , H01L27/11517 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L29/42328 , H01L29/66825 , H01L29/7887
摘要： A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type in the substrate with a second region of the second conductivity type in the substrate, spaced apart from the first region. A continuous first channel region is defined between the first region and the second region. A plurality of floating gates are spaced apart from one another with each positioned over a separate portion of the channel region. A plurality of control gates are provided with each associated with and adjacent to a floating gate. Each control gate has two portions: a first portion over a portion of the channel region and a second portion over the associated floating gate and capacitively coupled thereto.

9. 发明授权

US07050316B1 Differential non-volatile content addressable memory cell and array using phase changing resistor storage elements 有权
标题翻译：差分非易失性内容可寻址存储单元和阵列使用相变电阻存储元件
公开(公告)号：US07050316B1
公开(公告)日：2006-05-23
申请号：US10797207
申请日：2004-03-09
申请人： Ya-Fen Lin , Elbert Lin , Dana Lee , Bomy Chen , Hung Q. Nguyen
发明人： Ya-Fen Lin , Elbert Lin , Dana Lee , Bomy Chen , Hung Q. Nguyen
IPC分类号： G11C15/00
CPC分类号： G11C15/046 , G11C13/0004
摘要： A differential sensing content addressable memory cell without any word lines connected to the cells in the same row comprises a first bit line for supplying a first bit. A first storage element has a first phase change resistor for storing a first stored bit, which is connected in series with a first diode. The first storage element is connected to the first bit line. A second bit line supplies a second bit, with the second bit being an inverse of the first bit. A second storage element has a second phase change resistor for storing a second stored bit, which is connected in series with a second diode. The second storage element is connected to the second bit line. A match line is connected to the first and second storage elements for indicating whether a match occurred between the first bit and the first stored bit, and between the second bit and the second stored bit
摘要翻译：差分感测内容可寻址存储单元，没有连接到同一行中的单元的任何字线包括用于提供第一位的第一位线。第一存储元件具有第一相变电阻器，用于存储与第一二极管串联连接的第一存储位。第一存储元件连接到第一位线。第二位线提供第二位，第二位是第一位的倒数。第二存储元件具有用于存储与第二二极管串联连接的第二存储位的第二相变电阻器。第二存储元件连接到第二位线。匹配线连接到第一和第二存储元件，用于指示在第一位和第一存储位之间以及第二位和第二存储位之间是否发生匹配

10. 发明申请

US20060094197A1 Method of trimming semiconductor elements with electrical resistance feedback 有权
标题翻译：用电阻反馈修整半导体元件的方法
公开(公告)号：US20060094197A1
公开(公告)日：2006-05-04
申请号：US10983314
申请日：2004-11-04
申请人： Bomy Chen , Ya-Fen Lin , Zhitang Song , Songlin Feng
发明人： Bomy Chen , Ya-Fen Lin , Zhitang Song , Songlin Feng
IPC分类号： H01L21/20
CPC分类号： H01L28/20 , H01C17/267 , H01L22/22
摘要： A method of trimming down the volume of a semiconductor resistor element using electrical resistance feedback. After forming conductive material disposed between a pair of electrodes, a voltage is applied to the electrodes to produce an electrical current through the conductive material sufficient to heat and melt away a portion of the conductive material. By reducing the volume of the conductive material, its resistance is increased. The application of the voltage is ceased once the desired dimensions (and thus resistivity) of the conductive material is reached. The resulting semiconductor resistor element could have a fixed resistance, or could have a variable resistance (by using phase change memory material).
摘要翻译：使用电阻反馈来减少半导体电阻元件的体积的方法。在形成设置在一对电极之间的导电材料之后，向电极施加电压以产生通过导电材料的电流，足以加热和熔化掉导电材料的一部分。通过减小导电材料的体积，其电阻增加。一旦达到导电材料的所需尺寸（因此电阻率），电压的施加就会停止。所得到的半导体电阻元件可以具有固定电阻，或者可以具有可变电阻（通过使用相变存储器材料）。

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