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1. 发明授权

US07050316B1 Differential non-volatile content addressable memory cell and array using phase changing resistor storage elements 有权
标题翻译：差分非易失性内容可寻址存储单元和阵列使用相变电阻存储元件
公开(公告)号：US07050316B1
公开(公告)日：2006-05-23
申请号：US10797207
申请日：2004-03-09
申请人： Ya-Fen Lin , Elbert Lin , Dana Lee , Bomy Chen , Hung Q. Nguyen
发明人： Ya-Fen Lin , Elbert Lin , Dana Lee , Bomy Chen , Hung Q. Nguyen
IPC分类号： G11C15/00
CPC分类号： G11C15/046 , G11C13/0004
摘要： A differential sensing content addressable memory cell without any word lines connected to the cells in the same row comprises a first bit line for supplying a first bit. A first storage element has a first phase change resistor for storing a first stored bit, which is connected in series with a first diode. The first storage element is connected to the first bit line. A second bit line supplies a second bit, with the second bit being an inverse of the first bit. A second storage element has a second phase change resistor for storing a second stored bit, which is connected in series with a second diode. The second storage element is connected to the second bit line. A match line is connected to the first and second storage elements for indicating whether a match occurred between the first bit and the first stored bit, and between the second bit and the second stored bit
摘要翻译：差分感测内容可寻址存储单元，没有连接到同一行中的单元的任何字线包括用于提供第一位的第一位线。第一存储元件具有第一相变电阻器，用于存储与第一二极管串联连接的第一存储位。第一存储元件连接到第一位线。第二位线提供第二位，第二位是第一位的倒数。第二存储元件具有用于存储与第二二极管串联连接的第二存储位的第二相变电阻器。第二存储元件连接到第二位线。匹配线连接到第一和第二存储元件，用于指示在第一位和第一存储位之间以及第二位和第二存储位之间是否发生匹配

2. 发明授权

US07403418B2 Word line voltage boosting circuit and a memory array incorporating same 有权
公开(公告)号：US07403418B2
公开(公告)日：2008-07-22
申请号：US11241582
申请日：2005-09-30
申请人： Ya-Fen Lin , Elbert Lin , Hieu Van Tran , Jack Edward Frayer , Bomy Chen
发明人： Ya-Fen Lin , Elbert Lin , Hieu Van Tran , Jack Edward Frayer , Bomy Chen
IPC分类号： G11C11/34
CPC分类号： G11C8/08 , G11C16/08
摘要： A first embodiment of a word line voltage boosting circuit for use with an array of non-volatile memory cells has a capacitor, having two ends, connected to the word line. One end of the capacitor is electrically connected to the word line. The other end of the capacitor is electrically connected to a first voltage source. The word line is also connected through a switch to a second source voltage source. A sequencing circuit activates the switch such that the word line is connected to the second voltage source, and the other end of the capacitor is not connected to the first voltage source. Then the sequencing circuit causes the switch to disconnect the word line from the second voltage source, and connect the second end of the capacitor to the first voltage source. The alternate switching of the connection boosts the voltage on the word line. In a second embodiment, a first word line is electrically connected to a first switch to a first voltage source. An adjacent word line, capacitively coupled to the first word line, is electrically connected to a second switch to a second voltage source. A sequencing circuit activates the first switch and the second switch such that the first word line is connected to the first voltage source, and the second word line is disconnected from the second voltage source. Then the sequencing circuit causes the first switch to disconnect the first word line from the first voltage source, and causes the second word line to be electrically connected to the second voltage source. The alternate switching of the connection boosts the voltage on the first word line, caused by its capacitive coupling to the second word line. A boosted voltage on the word line may be used to improve cycling and yield, where the memory cells of the array are of the floating gate type and erase through the mechanism of Fowler-Nordheim tunneling from the floating gate to a control gate which is connected to the word line.

3. 发明申请

US20070076489A1 Word line voltage boosting circuit and a memory array incorporating same 有权
公开(公告)号：US20070076489A1
公开(公告)日：2007-04-05
申请号：US11241582
申请日：2005-09-30
申请人： Ya-Fen Lin , Elbert Lin , Hieu Tran , Jack Frayer , Bomy Chen
发明人： Ya-Fen Lin , Elbert Lin , Hieu Tran , Jack Frayer , Bomy Chen
IPC分类号： G11C11/34
CPC分类号： G11C8/08 , G11C16/08
摘要： A first embodiment of a word line voltage boosting circuit for use with an array of non-volatile memory cells has a capacitor, having two ends, connected to the word line. One end of the capacitor is electrically connected to the word line. The other end of the capacitor is electrically connected to a first voltage source. The word line is also connected through a switch to a second source voltage source. A sequencing circuit activates the switch such that the word line is connected to the second voltage source, and the other end of the capacitor is not connected to the first voltage source. Then the sequencing circuit causes the switch to disconnect the word line from the second voltage source, and connect the second end of the capacitor to the first voltage source. The alternate switching of the connection boosts the voltage on the word line. In a second embodiment, a first word line is electrically connected to a first switch to a first voltage source. An adjacent word line, capacitively coupled to the first word line, is electrically connected to a second switch to a second voltage source. A sequencing circuit activates the first switch and the second switch such that the first word line is connected to the first voltage source, and the second word line is disconnected from the second voltage source. Then the sequencing circuit causes the first switch to disconnect the first word line from the first voltage source, and causes the second word line to be electrically connected to the second voltage source. The alternate switching of the connection boosts the voltage on the first word line, caused by its capacitive coupling to the second word line. A boosted voltage on the word line may be used to improve cycling and yield, where the memory cells of the array are of the floating gate type and erase through the mechanism of Fowler-Nordheim tunneling from the floating gate to a control gate which is connected to the word line.

4. 发明申请

US20080131982A1 Method Of Trimming Semiconductor Elements With Electrical Resistance Feedback 有权
标题翻译：使用电阻反馈修整半导体元件的方法
公开(公告)号：US20080131982A1
公开(公告)日：2008-06-05
申请号：US12027916
申请日：2008-02-07
申请人： Bomy Chen , Ya-Fen Lin , Zhitang Song , Songlin Feng
发明人： Bomy Chen , Ya-Fen Lin , Zhitang Song , Songlin Feng
IPC分类号： H01L21/02
CPC分类号： H01L28/20 , H01C17/267 , H01L22/22
摘要： A method of trimming down the volume of a semiconductor resistor element using electrical resistance feedback. After forming conductive material disposed between a pair of electrodes, a voltage is applied to the electrodes to produce an electrical current through the conductive material sufficient to heat and melt away a portion of the conductive material. By reducing the volume of the conductive material, its resistance is increased. The application of the voltage is ceased once the desired dimensions (and thus resistivity) of the conductive material is reached. The resulting semiconductor resistor element could have a fixed resistance, or could have a variable resistance (by using phase change memory material).
摘要翻译：使用电阻反馈来减少半导体电阻元件的体积的方法。在形成设置在一对电极之间的导电材料之后，向电极施加电压以产生通过导电材料的电流，足以加热和熔化掉导电材料的一部分。通过减小导电材料的体积，其电阻增加。一旦达到导电材料的所需尺寸（因此电阻率），电压的施加就会停止。所得到的半导体电阻元件可以具有固定电阻，或者可以具有可变电阻（通过使用相变存储器材料）。

5. 发明授权

US07351613B2 Method of trimming semiconductor elements with electrical resistance feedback 有权
标题翻译：用电阻反馈修整半导体元件的方法
公开(公告)号：US07351613B2
公开(公告)日：2008-04-01
申请号：US10983314
申请日：2004-11-04
申请人： Bomy Chen , Ya-Fen Lin , Zhitang Song , Songlin Feng
发明人： Bomy Chen , Ya-Fen Lin , Zhitang Song , Songlin Feng
IPC分类号： H01L21/82
CPC分类号： H01L28/20 , H01C17/267 , H01L22/22
摘要： A method of trimming down the volume of a semiconductor resistor element using electrical resistance feedback. After forming conductive material disposed between a pair of electrodes, a voltage is applied to the electrodes to produce an electrical current through the conductive material sufficient to heat and melt away a portion of the conductive material. By reducing the volume of the conductive material, its resistance is increased. The application of the voltage is ceased once the desired dimensions (and thus resistivity) of the conductive material is reached. The resulting semiconductor resistor element could have a fixed resistance, or could have a variable resistance (by using phase change memory material).
摘要翻译：使用电阻反馈来减少半导体电阻元件的体积的方法。在形成设置在一对电极之间的导电材料之后，向电极施加电压以产生通过导电材料的电流，足以加热和熔化掉导电材料的一部分。通过减小导电材料的体积，其电阻增加。一旦达到导电材料的所需尺寸（因此电阻率），电压的施加就会停止。所得到的半导体电阻元件可以具有固定电阻，或者可以具有可变电阻（通过使用相变存储器材料）。

6. 发明申请

US20060094197A1 Method of trimming semiconductor elements with electrical resistance feedback 有权
标题翻译：用电阻反馈修整半导体元件的方法
公开(公告)号：US20060094197A1
公开(公告)日：2006-05-04
申请号：US10983314
申请日：2004-11-04
申请人： Bomy Chen , Ya-Fen Lin , Zhitang Song , Songlin Feng
发明人： Bomy Chen , Ya-Fen Lin , Zhitang Song , Songlin Feng
IPC分类号： H01L21/20
CPC分类号： H01L28/20 , H01C17/267 , H01L22/22
摘要： A method of trimming down the volume of a semiconductor resistor element using electrical resistance feedback. After forming conductive material disposed between a pair of electrodes, a voltage is applied to the electrodes to produce an electrical current through the conductive material sufficient to heat and melt away a portion of the conductive material. By reducing the volume of the conductive material, its resistance is increased. The application of the voltage is ceased once the desired dimensions (and thus resistivity) of the conductive material is reached. The resulting semiconductor resistor element could have a fixed resistance, or could have a variable resistance (by using phase change memory material).
摘要翻译：使用电阻反馈来减少半导体电阻元件的体积的方法。在形成设置在一对电极之间的导电材料之后，向电极施加电压以产生通过导电材料的电流，足以加热和熔化掉导电材料的一部分。通过减小导电材料的体积，其电阻增加。一旦达到导电材料的所需尺寸（因此电阻率），电压的施加就会停止。所得到的半导体电阻元件可以具有固定电阻，或者可以具有可变电阻（通过使用相变存储器材料）。

7. 发明授权

US07790518B2 Method of trimming semiconductor elements with electrical resistance feedback 有权
标题翻译：用电阻反馈修整半导体元件的方法
公开(公告)号：US07790518B2
公开(公告)日：2010-09-07
申请号：US12027916
申请日：2008-02-07
申请人： Bomy Chen , Ya-Fen Lin , Zhitang Song , Songlin Feng
发明人： Bomy Chen , Ya-Fen Lin , Zhitang Song , Songlin Feng
IPC分类号： H01L21/82
CPC分类号： H01L28/20 , H01C17/267 , H01L22/22
摘要： A method of trimming down the volume of a semiconductor resistor element using electrical resistance feedback. After forming conductive material disposed between a pair of electrodes, a voltage is applied to the electrodes to produce an electrical current through the conductive material sufficient to heat and melt away a portion of the conductive material. By reducing the volume of the conductive material, its resistance is increased. The application of the voltage is ceased once the desired dimensions (and thus resistivity) of the conductive material is reached. The resulting semiconductor resistor element could have a fixed resistance, or could have a variable resistance (by using phase change memory material).
摘要翻译：使用电阻反馈来减少半导体电阻元件的体积的方法。在形成设置在一对电极之间的导电材料之后，向电极施加电压以产生通过导电材料的电流，足以加热和熔化掉导电材料的一部分。通过减小导电材料的体积，其电阻增加。一旦达到导电材料的所需尺寸（因此电阻率），电压的施加就会停止。所得到的半导体电阻元件可以具有固定电阻，或者可以具有可变电阻（通过使用相变存储器材料）。

8. 发明授权

US06809425B1 Integrated circuit with a reprogrammable nonvolatile switch having a dynamic threshold voltage (VTH) for selectively connecting a source for a signal to a circuit 有权
标题翻译：具有可再编程非易失性开关的集成电路，其具有用于选择性地将信号源与电路连接的动态阈值电压（VTH）
公开(公告)号：US06809425B1
公开(公告)日：2004-10-26
申请号：US10641610
申请日：2003-08-15
申请人： Bomy Chen , Isao Nojima , Hung Q. Nguyen
发明人： Bomy Chen , Isao Nojima , Hung Q. Nguyen
IPC分类号： H01L27088
CPC分类号： H03K19/17748 , H01L27/101 , H03K19/1778 , Y10S257/901
摘要： A nonvolatile reprogrammable switch for use in a PLD or FPGA has a nonvolatile memory cell connected to the gate of an MOS transistor, which is in a well, with the terminals of the MOS transistor connected to the source of the signal and to the circuit. The nonvolatile memory cell is of a split gate type having a first region and a second region, with a channel therebetween. The cell has a floating gate positioned over a first portion of the channel, which is adjacent to the first region and a control gate positioned over a second portion of the channel, which is adjacent to the second region. The second region is connected to the gate of the MOS transistor. The cell is programmed by injecting electrons from the channel onto the floating gate by hot electron injection mechanism. The cell is erased by Fowler-Nordheim tunneling of the electrons from the floating gate to the control gate. As a result, no high voltage is ever applied to the second region during program or erase. In addition, a MOS FET transistor has a terminal connected to the well, and another end to a voltage source, with the gate connected to the non-volatile memory cell. The switch also has a circuit element connecting the gate of the MOS transistor to a voltage source. The threshold voltage of the well can be dynamically changed by turning on/off the MOS FET transistor.
摘要翻译：用于PLD或FPGA的非易失性可重新编程开关具有连接到MOS晶体管的栅极的非易失性存储单元，MOS晶体管位于阱中，MOS晶体管的端子连接到信号源和电路。非易失性存储单元是具有第一区域和第二区域的分离栅极类型，其间具有沟道。电池具有位于通道第一部分上方的浮动栅极，该第一部分与第一区域相邻，并且控制栅极位于与第二区域相邻的通道的第二部分上方。第二区域连接到MOS晶体管的栅极。通过热电子注入机制将电子从通道注入到浮动栅上来编程电池。 Fowler-Nordheim将电池从浮动栅极隧穿到控制栅极，从而消除电池。因此，在编程或擦除期间，不会对第二区域施加高电压。此外，MOS FET晶体管具有连接到阱的端子，另一端连接到电压源，栅极连接到非易失性存储单元。该开关还具有将MOS晶体管的栅极连接到电压源的电路元件。通过接通/关断MOS FET晶体管可以动态地改变阱的阈值电压。

9. 发明授权

US07180127B2 Semiconductor memory array of floating gate memory cells with buried floating gate, pointed floating gate and pointed channel region 有权
标题翻译：半导体存储器阵列的浮动栅极存储单元具有埋入浮栅，尖浮栅和尖通道区
公开(公告)号：US07180127B2
公开(公告)日：2007-02-20
申请号：US10872052
申请日：2004-06-17
申请人： Bomy Chen , Dana Lee
发明人： Bomy Chen , Dana Lee
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L29/42336 , H01L29/66825 , H01L29/7885
摘要： A method of forming a floating gate memory cell array, and the array formed thereby, wherein a trench is formed into the surface of a semiconductor substrate. The source and drain regions are formed underneath the trench and along the substrate surface, respectively, with a non-linear channel region therebetween. The floating gate has a lower portion disposed in the trench and an upper portion disposed above the substrate surface and having a lateral protrusion extending parallel to the substrate surface. The lateral protrusion is formed by etching a cavity into an exposed end of a sacrificial layer and filling it with polysilicon. The control gate is formed about the lateral protrusion and is insulated therefrom. The trench sidewall meets the substrate surface at an acute angle to form a sharp edge that points toward the floating gate and in a direction opposite to that of the lateral protrusion.
摘要翻译：一种形成浮栅存储单元阵列的方法和由此形成的阵列，其中沟槽形成在半导体衬底的表面中。源极和漏极区分别形成在沟槽下方并且沿着衬底表面，其间具有非线性沟道区。浮动栅极具有设置在沟槽中的下部和设置在基板表面上方并具有平行于基板表面延伸的横向突起的上部。横向突起通过将空腔蚀刻到牺牲层的暴露端并用多晶硅填充而形成。控制门围绕横向突起形成并与其绝缘。沟槽侧壁以锐角与衬底表面相接触以形成指向浮动栅极并且沿与横向突起的方向相反的方向的尖锐边缘。

10. 发明授权

US06992909B2 Multi-bit ROM cell, for storing one of n>4 possible states and having bi-directional read, an array of such cells, and a method for making the array 有权
标题翻译：用于存储n> 4个可能状态之一并且具有双向读取的多位ROM单元，这种单元的阵列，以及用于制作阵列的方法
公开(公告)号：US06992909B2
公开(公告)日：2006-01-31
申请号：US11157318
申请日：2005-06-20
申请人： Bomy Chen , Kai Man Yue , Dana Lee , Feng Gao
发明人： Bomy Chen , Kai Man Yue , Dana Lee , Feng Gao
IPC分类号： G11C17/00
CPC分类号： H01L27/112 , G11C11/5692 , G11C17/12 , H01L27/1126 , H01L27/11266
摘要： A array of multi-bit Read Only Memory (ROM) cells is in a semiconductor substrate of a first conductivity type with a first concentration. Each ROM cell has a first and second regions of a second conductivity type spaced apart from one another in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. Each ROM cell has one of a plurality of N possible states, where N is greater than 2. The state of each ROM cell is determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost. The array of ROM cells are arranged in a plurality of rows and columns, with ROM cells in the same row having their gates connected together. ROM cells in the same column have the first regions connected in a common first column, and second regions connected in common second column. Finally, ROM cells in adjacent columns to one side share a common first column, and cells in adjacent columns to another side share a common second column.
摘要翻译：多位只读存储器（ROM）单元的阵列位于具有第一浓度的第一导电类型的半导体衬底中。每个ROM单元具有在基板中彼此间隔开的第二导电类型的第一和第二区域。通道在第一和第二区域之间。通道具有三个部分，第一部分，第二部分和第三部分。门间隔开并与通道的至少第二部分绝缘。每个ROM单元具有多个N个可能状态中的一个，其中N大于2.每个ROM单元的状态由存在或不存在在通道的第一部分中形成并与通道的第一部分相邻第一区域和/或与第二区域相邻的通道的第三部分。在集成电路器件的其他部分的MOS晶体管中形成扩展或光晕的同时形成这些扩展和光晕，从而降低成本。 ROM单元的阵列被布置成多个行和列，其中同一行中的ROM单元的门连接在一起。同一列中的ROM单元具有连接在公共第一列中的第一区域和连接在公共第二列中的第二区域。最后，一侧的相邻列中的ROM单元共享一个共同的第一列，另一侧的相邻列中的单元格共享第二列。

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