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1. 发明授权

US5837605A Manufacturing method of transistors 失效
标题翻译：晶体管的制造方法
公开(公告)号：US5837605A
公开(公告)日：1998-11-17
申请号：US563082
申请日：1995-11-27
申请人： Young-wook Park , Dae-rok Bae , Mun-han Park
发明人： Young-wook Park , Dae-rok Bae , Mun-han Park
IPC分类号： H01L21/335 , H01L21/28 , H01L21/285 , H01L21/336 , H01L29/78 , H01L21/441
CPC分类号： H01L21/28061
摘要： A manufacturing method for transistors wherein silicide is directed doped with a conductive impurity includes the steps of: forming a field oxide film defining an active region on a semiconductor substrate; forming transistors wherein a doped first silicide film is formed on gate electrodes on said active region; forming an interlayer dielectric film having contact holes on the whole surface of said semiconductor substrate; forming spacers on the innerwalls of each contact hole;p forming a thin doped polysilicon film on the whole surface of said semiconductor surface; and forming a doped second silicide film on the whole surface of said doped polysilicon film, filling each contact hole. The silicide film is directly doped with conductive impurity so that the conductive impurity of a polysilicon film can be prevented from being diffused to the outside. Therefore, the doped silicide film is useful to prevent the threshold voltage from increasing and the saturation current from reducing.
摘要翻译：其中硅化物被引导掺杂有导电杂质的晶体管的制造方法包括以下步骤：在半导体衬底上形成限定有源区的场氧化物膜; 形成晶体管，其中在所述有源区上的栅电极上形成掺杂的第一硅化物膜; 在所述半导体衬底的整个表面上形成具有接触孔的层间绝缘膜; 在每个接触孔的内壁上形成间隔物; p在所述半导体表面的整个表面上形成薄掺杂多晶硅膜; 以及在所述掺杂多晶硅膜的整个表面上形成掺杂的第二硅化物膜，填充每个接触孔。硅化物膜直接掺杂有导电杂质，使得可以防止多晶硅膜的导电杂质扩散到外部。因此，掺杂的硅化物膜可用于防止阈值电压升高，饱和电流降低。

2. 发明申请

US20050064660A1 Methods of fabricating integrated circuit devices that utilize doped poly-Si1-xGex conductive plugs as interconnects 有权
标题翻译：使用掺杂的多晶硅Si-xGex导电插头作为互连的集成电路器件的制造方法
公开(公告)号：US20050064660A1
公开(公告)日：2005-03-24
申请号：US10968233
申请日：2004-10-19
申请人： Sang-jeong Oh , Yeong-kwan Kim , Seung-hwan Lee , Dong-chan Kim , Young-wook Park
发明人： Sang-jeong Oh , Yeong-kwan Kim , Seung-hwan Lee , Dong-chan Kim , Young-wook Park
IPC分类号： H01L21/283 , H01L21/02 , H01L21/285 , H01L21/768 , H01L21/8242 , H01L23/485 , H01L21/44
CPC分类号： H01L27/10855 , H01L21/28525 , H01L21/76877 , H01L21/76895 , H01L23/485 , H01L28/60 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides integrated circuit devices that include a semiconductor substrate having a semiconductor region of first conductivity type therein extending adjacent the surface of the substrate. The device further includes an electrically insulating layer with a contact hole in it that exposes the semiconductor region of first conductivity type on the surface of the semiconductor substrate. The device still further includes a poly-Si1-xGex conductive plug of first conductivity type that extends in the contact hole and is electrically connected to the semiconductor region of first conductivity type is provided. Related methods of fabricating integrated circuit devices are also provided.
摘要翻译：本发明提供了一种集成电路器件，其包括半导体衬底，该半导体衬底具有第一导电类型的半导体区域，该半导体区域在衬底的表面附近延伸。该器件还包括其中具有接触孔的电绝缘层，其在半导体衬底的表面上暴露出第一导电类型的半导体区域。该装置还包括在接触孔中延伸并与第一导电类型的半导体区域电连接的第一导电类型的多晶Si1-xGex导电插塞。还提供了制造集成电路器件的相关方法。

3. 发明授权

US06828616B2 Integrated circuit devices that utilize doped Poly-Si1−xGex conductive plugs as interconnects 有权
标题翻译：利用掺杂的Poly-Si1-xGex导电插头作为互连的集成电路器件
公开(公告)号：US06828616B2
公开(公告)日：2004-12-07
申请号：US10012116
申请日：2001-11-13
申请人： Sang-jeong Oh , Yeong-kwan Kim , Seung-hwan Lee , Dong-chan Kim , Young-wook Park
发明人： Sang-jeong Oh , Yeong-kwan Kim , Seung-hwan Lee , Dong-chan Kim , Young-wook Park
IPC分类号： H01L27108
CPC分类号： H01L27/10855 , H01L21/28525 , H01L21/76877 , H01L21/76895 , H01L23/485 , H01L28/60 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides an integrated circuit device that include a semiconductor substrate having a semiconductor region of first conductivity type therein extending adjacent the surface of the substrate. The device further includes an electrically insulating layer with a contact hole in it that exposes the semiconductor region of first conductivity type on the surface of the semiconductor substrate. The device still further includes a poly-Si1−xGex conductive plug of first conductivity type that extends in the contact hole and is electrically connected to the semiconductor region of first conductivity type is provided.
摘要翻译：本发明提供了一种集成电路器件，其包括半导体衬底，该半导体衬底具有与衬底表面相邻的第一导电类型的半导体区域。该器件还包括其中具有接触孔的电绝缘层，其在半导体衬底的表面上暴露出第一导电类型的半导体区域。该装置还包括在接触孔中延伸并与第一导电类型的半导体区域电连接的第一导电类型的多晶Si1-xGex导电插塞。

4. 发明授权

US06468924B2 Methods of forming thin films by atomic layer deposition 有权
公开(公告)号：US06468924B2
公开(公告)日：2002-10-22
申请号：US09871430
申请日：2001-05-31
申请人： Seung-hwan Lee , Yeong-kwan Kim , Dong-chan Kim , Young-wook Park
发明人： Seung-hwan Lee , Yeong-kwan Kim , Dong-chan Kim , Young-wook Park
IPC分类号： H01L2131
CPC分类号： H01L21/0228 , C23C16/34 , C23C16/345 , C23C16/402 , C23C16/403 , C23C16/405 , C23C16/409 , C23C16/45531 , C23C16/45542 , H01L21/02164 , H01L21/02178 , H01L21/02183 , H01L21/02186 , H01L21/02194 , H01L21/02197 , H01L21/02274 , H01L21/3185
摘要： Methods of forming thin films include forming a first layer comprising a first element that is chemisorbed to a surface of a substrate, by exposing the surface to a first source gas having molecules therein that comprise the first element and a halogen. A step is then performed to expose the first layer to an activated hydrogen gas so that halogens associated with the first layer become bound to hydrogen provided by the activated hydrogen gas. The first layer may then be converted to a thin film comprising the first element and a second element, by exposing a surface of the first layer to a second source gas having molecules therein that comprise the second element.

5. 发明授权

US06416584B1 Apparatus for forming a film on a substrate 有权
标题翻译：用于在基板上形成膜的装置
公开(公告)号：US06416584B1
公开(公告)日：2002-07-09
申请号：US09350407
申请日：1999-07-08
申请人： Seok-jun Won , Young-wook Park , Yong-woo Hyung
发明人： Seok-jun Won , Young-wook Park , Yong-woo Hyung
IPC分类号： C23C1600
CPC分类号： C23C16/56 , C23C16/405
摘要： An apparatus for forming a film on a substrate includes a reaction chamber and gas supply lines. The gas supply lines supply gases for depositing and annealing the film. Depositing a dielectric film and annealing the dielectric film are performed in situ using the reaction chamber. Thus, the time required for forming the dielectric film is shortened, improving the productivity. Also, deposition and annealing of the dielectric film are performed in the same reaction chamber, so that less area is required for manufacturing equipment.
摘要翻译：在基板上形成膜的装置包括反应室和气体供给管线。气体供应管线供应用于沉积和退火膜的气体。使用反应室原位进行沉积介电膜并退火介电膜。因此，缩短了形成电介质膜所需的时间，提高了生产率。此外，电介质膜的沉积和退火在相同的反应室中进行，因此制造设备需要较少的面积。

6. 发明授权

US06207489B1 Method for manufacturing capacitor of semiconductor memory device having tantalum oxide film 失效
标题翻译：具有氧化钽膜的半导体存储器件的电容器的制造方法
公开(公告)号：US06207489B1
公开(公告)日：2001-03-27
申请号：US09393186
申请日：1999-09-10
申请人： Kab-jin Nam , Seok-jun Won , Ki-yeon Park , Yong-woo Hyung , Young-wook Park
发明人： Kab-jin Nam , Seok-jun Won , Ki-yeon Park , Yong-woo Hyung , Young-wook Park
IPC分类号： H01L218242
CPC分类号： H01L21/02183 , C03C23/0075 , H01L21/02271 , H01L21/0231 , H01L21/02315 , H01L21/02337 , H01L21/31604 , H01L27/1085 , H01L28/56
摘要： A method for manufacturing a capacitor having a dielectric film formed of a tantalum oxide film. The method includes forming a lower electrode that is electrically connected to an active region of a semiconductor substrate. A pre-treatment film including a component selected from a group consisting of silicon oxide, silicon nitride, and combinations thereof, is formed on the surface of the lower electrode. A dielectric film is formed on the pre-treatment film using a Ta precursor. The dielectric film includes a first dielectric layer deposited at a first temperature selected from a designated temperature range, and a second dielectric layer deposited at a second temperature different from the first temperature and selected from the same designated temperature range. A thermal treatment is thereafter performed on the dielectric film in an oxygen atmosphere.
摘要翻译：一种制造具有由氧化钽膜形成的电介质膜的电容器的方法。该方法包括形成电连接到半导体衬底的有源区的下电极。在下电极的表面上形成包括选自氧化硅，氮化硅及其组合的组分的预处理膜。使用Ta前体在预处理膜上形成电介质膜。电介质膜包括在选自指定温度范围的第一温度下沉积的第一介电层和在与第一温度不同的第二温度下沉积并选自相同指定温度范围的第二电介质层。此后在氧气氛中对电介质膜进行热处理。

7. 发明授权

US6117692A Calibrated methods of forming hemispherical grained silicon layers 失效
标题翻译：形成半球形硅层的校准方法
公开(公告)号：US6117692A
公开(公告)日：2000-09-12
申请号：US7879
申请日：1998-01-14
申请人： Young-sun Kim , Young-wook Park
发明人： Young-sun Kim , Young-wook Park
IPC分类号： H01L21/02 , G01R31/26
CPC分类号： H01L28/84
摘要： A method of forming a silicon layer includes the step of calibrating the heater temperature so that a predetermined temperature is maintained when a microelectronic substrate is subsequently heated despite a number of processing runs previously performed. This calibrating step includes loading a test substrate into the reaction chamber, subjecting the test substrate to the predetermined reaction recipe wherein the test substrate is heated according to the predetermined recipe, measuring the temperature of the substrate, and removing the test substrate from the reaction chamber. The heater temperature is then adjusted according to the measured temperature of the test substrate. A microelectronic substrate is then loaded into the reaction chamber, and a hemispherical grained silicon seed layer is formed on the microelectronic substrate according to the predetermined recipe. The hemispherical grained silicon seed layer is annealed to form a hemispherical grained silicon layer according to the predetermined recipe.
摘要翻译：形成硅层的方法包括校准加热器温度的步骤，使得当微电子基板随后被加热而保持预定温度，而不管先前执行了多个处理运行。该校准步骤包括将测试基板装载到反应室中，使测试基板经受预定的反应配方，其中根据预定配方加热测试基板，测量基板的温度，并将测试基板从反应室。然后根据测试基板的测量温度调节加热器温度。然后将微电子衬底加载到反应室中，并根据预定的配方在微电子衬底上形成半球状晶粒硅籽晶层。根据预定的配方，将半球形晶粒硅层退火以形成半球形的硅层。

8. 发明授权

US5721153A Method of making capacitor of highly integrated semiconductor device using multiple insulation layers 失效
标题翻译：使用多层绝缘层制造高度集成的半导体器件的电容器的方法
公开(公告)号：US5721153A
公开(公告)日：1998-02-24
申请号：US604300
申请日：1996-02-21
申请人： Kyung-hoon Kim , Young-wook Park , Cha-young Yoo
发明人： Kyung-hoon Kim , Young-wook Park , Cha-young Yoo
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , Y10S438/964
摘要： A capacitor of a highly integrated semiconductor device and a manufacturing method thereof is provided. In the highly integrated semiconductor device, an HSG polysilicon layer pattern is formed having a multitude of hemispherical grains (HSG) on the top and side surfaces of the storage electrode. Thus, the etching of and damage to the HSG polysilicon layer pattern can be prevented, and capacitance can be increased by maximizing the surface area of the storage electrode.
摘要翻译：提供了高度集成的半导体器件的电容器及其制造方法。在高度集成的半导体器件中，在存储电极的顶表面和侧表面上形成有多个半球形晶粒（HSG）的HSG多晶硅层图案。因此，可以防止对HSG多晶硅层图案的蚀刻和损坏，并且可以通过使存储电极的表面积最大化来增加电容。

9. 发明授权

US07544607B2 Semiconductor device having thin film formed by atomic layer deposition and method for fabricating the same 有权
公开(公告)号：US07544607B2
公开(公告)日：2009-06-09
申请号：US10990429
申请日：2004-11-18
申请人： Yeong-kwan Kim , Dong-chan Kim , Seung-hwan Lee , Young-wook Park
发明人： Yeong-kwan Kim , Dong-chan Kim , Seung-hwan Lee , Young-wook Park
IPC分类号： H01L21/4763 , H01L29/00 , H01L23/58
CPC分类号： H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02211 , H01L21/0228 , H01L21/31612 , H01L21/3185 , H01L21/76829 , H01L21/76832 , H01L21/76837 , H01L21/823475 , H01L27/10873 , H01L27/10885
摘要： A semiconductor device having a thin film formed by atomic layer deposition and a method for fabricating the same, wherein the semiconductor device includes a liner layer formed on an internal wall and bottom of a trench, gate spacers formed on the sidewalls of gate stack patterns functioning as a gate line, a first bubble prevention layer formed on the gate spacers and the gate stack patterns, bit line spacers formed on the sidewalls of bit line stack patterns functioning as a bit line, and a second bubble prevention layer formed on the bit line spacers and the gate stack patterns and at least one of the above is formed of a multi-layer of a silicon nitride layer and a silicon oxide layer, or a multi-layer of a silicon oxide layer and a silicon nitride layer, thereby filling the trench, gate stack patterns, or bit line stack patterns without a void.

10. 发明授权

US06833310B2 Semiconductor device having thin film formed by atomic layer deposition and method for fabricating the same 有权
标题翻译：具有通过原子层沉积形成的薄膜的半导体器件及其制造方法
公开(公告)号：US06833310B2
公开(公告)日：2004-12-21
申请号：US09902607
申请日：2001-07-12
申请人： Yeong-kwan Kim , Dong-chan Kim , Seung-hwan Lee , Young-wook Park
发明人： Yeong-kwan Kim , Dong-chan Kim , Seung-hwan Lee , Young-wook Park
IPC分类号： H01L2176
CPC分类号： H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02211 , H01L21/0228 , H01L21/31612 , H01L21/3185 , H01L21/76829 , H01L21/76832 , H01L21/76837 , H01L21/823475 , H01L27/10873 , H01L27/10885
摘要： A semiconductor device having a thin film formed by atomic layer deposition and a method for fabricating the same, wherein the semiconductor device includes a liner layer formed on an internal wall and bottom of a trench, gate spacers formed on the sidewalls of gate stack patterns functioning as a gate line, a first bubble prevention layer formed on the gate spacers and the gate stack patterns, bit line spacers formed on the sidewalls of bit line stack patterns functioning as a bit line, and a second bubble prevention layer formed on the bit line spacers and the gate stack patterns and at least one of the above is formed of a multi-layer of a silicon nitride layer and a silicon oxide layer, or a multi-layer of a silicon oxide layer and a silicon nitride layer, thereby filling the trench, gate stack patterns, or bit line stack patterns without a void.
摘要翻译：具有通过原子层沉积形成的薄膜的半导体器件及其制造方法，其中所述半导体器件包括形成在沟槽的内壁和底部上的衬垫层，形成在栅堆叠图案功能的侧壁上的栅极间隔作为栅极线，形成在栅极间隔物和栅极堆叠图案上的第一防止气泡层，形成在用作位线的位线堆叠图案的侧壁上的位线间隔物和形成在位线上的第二防止气泡层间隔物和栅极堆叠图案，并且上述中的至少一个由氮化硅层和氧化硅层的多层或氧化硅层和氮化硅层的多层形成，从而填充沟槽，栅极堆叠图案或无空隙的位线堆叠图案。

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