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1. 发明授权

US07316954B2 Methods of fabricating integrated circuit devices that utilize doped poly-Si1−xGex conductive plugs as interconnects 有权
标题翻译：使用掺杂的多晶硅Si-xGex导电插头作为互连的集成电路器件的制造方法
公开(公告)号：US07316954B2
公开(公告)日：2008-01-08
申请号：US10968233
申请日：2004-10-19
申请人： Sang-jeong Oh , Yeong-kwan Kim , Seung-hwan Lee , Dong-chan Kim , Young-wook Park
发明人： Sang-jeong Oh , Yeong-kwan Kim , Seung-hwan Lee , Dong-chan Kim , Young-wook Park
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L27/10855 , H01L21/28525 , H01L21/76877 , H01L21/76895 , H01L23/485 , H01L28/60 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides integrated circuit devices that include a semiconductor substrate having a semiconductor region of first conductivity type therein extending adjacent the surface of the substrate. The device further includes an electrically insulating layer with a contact hole in it that exposes the semiconductor region of first conductivity type on the surface of the semiconductor substrate. The device still further includes a poly-Si1-xGex conductive plug of first conductivity type that extends in the contact hole and is electrically connected to the semiconductor region of first conductivity type is provided. Related methods of fabricating integrated circuit devices are also provided.
摘要翻译：本发明提供了一种集成电路器件，其包括半导体衬底，该半导体衬底具有第一导电类型的半导体区域，该半导体区域在衬底的表面附近延伸。该器件还包括其中具有接触孔的电绝缘层，其在半导体衬底的表面上暴露出第一导电类型的半导体区域。该器件还包括在接触孔中延伸并且电连接到第一导电类型的半导体区域的第一导电类型的多晶Si-1-x-Ge 提供导电类型。还提供了制造集成电路器件的相关方法。

2. 发明申请

US20050064660A1 Methods of fabricating integrated circuit devices that utilize doped poly-Si1-xGex conductive plugs as interconnects 有权
标题翻译：使用掺杂的多晶硅Si-xGex导电插头作为互连的集成电路器件的制造方法
公开(公告)号：US20050064660A1
公开(公告)日：2005-03-24
申请号：US10968233
申请日：2004-10-19
申请人： Sang-jeong Oh , Yeong-kwan Kim , Seung-hwan Lee , Dong-chan Kim , Young-wook Park
发明人： Sang-jeong Oh , Yeong-kwan Kim , Seung-hwan Lee , Dong-chan Kim , Young-wook Park
IPC分类号： H01L21/283 , H01L21/02 , H01L21/285 , H01L21/768 , H01L21/8242 , H01L23/485 , H01L21/44
CPC分类号： H01L27/10855 , H01L21/28525 , H01L21/76877 , H01L21/76895 , H01L23/485 , H01L28/60 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides integrated circuit devices that include a semiconductor substrate having a semiconductor region of first conductivity type therein extending adjacent the surface of the substrate. The device further includes an electrically insulating layer with a contact hole in it that exposes the semiconductor region of first conductivity type on the surface of the semiconductor substrate. The device still further includes a poly-Si1-xGex conductive plug of first conductivity type that extends in the contact hole and is electrically connected to the semiconductor region of first conductivity type is provided. Related methods of fabricating integrated circuit devices are also provided.
摘要翻译：本发明提供了一种集成电路器件，其包括半导体衬底，该半导体衬底具有第一导电类型的半导体区域，该半导体区域在衬底的表面附近延伸。该器件还包括其中具有接触孔的电绝缘层，其在半导体衬底的表面上暴露出第一导电类型的半导体区域。该装置还包括在接触孔中延伸并与第一导电类型的半导体区域电连接的第一导电类型的多晶Si1-xGex导电插塞。还提供了制造集成电路器件的相关方法。

3. 发明授权

US06828616B2 Integrated circuit devices that utilize doped Poly-Si1−xGex conductive plugs as interconnects 有权
标题翻译：利用掺杂的Poly-Si1-xGex导电插头作为互连的集成电路器件
公开(公告)号：US06828616B2
公开(公告)日：2004-12-07
申请号：US10012116
申请日：2001-11-13
申请人： Sang-jeong Oh , Yeong-kwan Kim , Seung-hwan Lee , Dong-chan Kim , Young-wook Park
发明人： Sang-jeong Oh , Yeong-kwan Kim , Seung-hwan Lee , Dong-chan Kim , Young-wook Park
IPC分类号： H01L27108
CPC分类号： H01L27/10855 , H01L21/28525 , H01L21/76877 , H01L21/76895 , H01L23/485 , H01L28/60 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides an integrated circuit device that include a semiconductor substrate having a semiconductor region of first conductivity type therein extending adjacent the surface of the substrate. The device further includes an electrically insulating layer with a contact hole in it that exposes the semiconductor region of first conductivity type on the surface of the semiconductor substrate. The device still further includes a poly-Si1−xGex conductive plug of first conductivity type that extends in the contact hole and is electrically connected to the semiconductor region of first conductivity type is provided.
摘要翻译：本发明提供了一种集成电路器件，其包括半导体衬底，该半导体衬底具有与衬底表面相邻的第一导电类型的半导体区域。该器件还包括其中具有接触孔的电绝缘层，其在半导体衬底的表面上暴露出第一导电类型的半导体区域。该装置还包括在接触孔中延伸并与第一导电类型的半导体区域电连接的第一导电类型的多晶Si1-xGex导电插塞。

4. 发明授权

US06008135A Method for etching metal layer of a semiconductor device using hard mask 有权
标题翻译：使用硬掩模蚀刻半导体器件的金属层的方法
公开(公告)号：US06008135A
公开(公告)日：1999-12-28
申请号：US140325
申请日：1998-08-26
申请人： Sang-Jeong Oh , Yong-tak Lee
发明人： Sang-Jeong Oh , Yong-tak Lee
IPC分类号： H01L21/3063 , H01L21/3213 , H01L21/00
CPC分类号： H01L21/32139 , H01L21/32136
摘要： A method for etching a metal layer of a semiconductor device is provided. A metal layer formed on a substrate is etched using a hard mask and a mixed etching gas containing chlorine and oxygen in which the ratio of oxygen gas is preferably about 0.5-0.8. Under such conditions, a metal layer pattern of a fine profile is formed. Since the hard mask is thin, it is possible to prevent etch reactants generated in a process of etching the metal layer from being deposited on the side surface of the resultant formed of the metal layer pattern and the hard mask. As a result, no additional processing is required to remove the etch reactants from the side surfaces and the metal layer etching process is simplified.
摘要翻译：提供了一种蚀刻半导体器件的金属层的方法。使用硬掩模和含有氧气和氧气的混合蚀刻气体蚀刻形成在基板上的金属层，其中氧气比优选为约0.5〜0.8。在这种条件下，形成精细轮廓的金属层图案。由于硬掩模是薄的，因此可以防止在蚀刻金属层的过程中产生的蚀刻反应物沉积在由金属层图案和硬掩模形成的结果的侧表面上。结果，不需要额外的处理来从侧表面去除蚀刻反应物，并且简化了金属层蚀刻工艺。

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