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1. 发明申请

US20130034963A1 METHODS OF FORMING FINE PATTERNS FOR SEMICONDUCTOR DEVICE 有权
标题翻译：形成半导体器件精细图案的方法
公开(公告)号：US20130034963A1
公开(公告)日：2013-02-07
申请号：US13474764
申请日：2012-05-18
申请人： Byung-hong Chung , Cha-young Yoo , Dong-hyun Kim
发明人： Byung-hong Chung , Cha-young Yoo , Dong-hyun Kim
IPC分类号： H01L21/311
CPC分类号： H01L21/32139 , H01L21/0217 , H01L21/0228 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/31116 , H01L27/0207 , H01L27/10888 , H01L27/10891 , H01L27/11568
摘要： Methods of forming fine patterns for a semiconductor device include forming a hard mask layer on an etch target layer; forming a carbon containing layer on the hard mask layer; forming carbon containing layer patterns by etching the carbon containing layer; forming spacers covering opposing side walls of each of the carbon containing layer patterns; removing the carbon containing layer patterns; forming hard mask patterns by etching the hard mask layer using the spacers as a first etching mask; and etching the etch target layer by using the hard mask patterns a second etching mask.
摘要翻译：形成用于半导体器件的精细图案的方法包括在蚀刻目标层上形成硬掩模层; 在所述硬掩模层上形成含碳层; 通过蚀刻含碳层形成含碳层图案; 形成覆盖每个含碳层图案的相对侧壁的间隔物; 去除含碳层图案; 通过使用间隔物作为第一蚀刻掩模蚀刻硬掩模层来形成硬掩模图案; 以及通过使用所述硬掩模图案蚀刻所述蚀刻目标层的第二蚀刻掩模。

2. 发明授权

US07973352B2 Capacitors having composite dielectric layers containing crystallization inhibiting regions 有权
标题翻译：具有包含结晶抑制区域的复合电介质层的电容器
公开(公告)号：US07973352B2
公开(公告)日：2011-07-05
申请号：US12754713
申请日：2010-04-06
申请人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Young-sun Kim , Se-hoon Oh
发明人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Young-sun Kim , Se-hoon Oh
IPC分类号： H01L29/94
CPC分类号： H01L29/92 , H01L27/10852 , H01L28/40
摘要： Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.
摘要翻译：集成电路电容器在其中具有复合电介质层。这些复合电介质层包括用于增加复合介电层的整体结晶温度的结晶抑制区。集成电路电容器包括第一和第二电容器电极和在第一和第二电容器电极之间延伸的电容器介电层。电容器介电层包括邻近第一电容器电极延伸的第一电介质层，邻近第二电容器电极延伸的第二电介质层和在第一和第二电介质层之间延伸的电绝缘的结晶抑制层的复合材料。电绝缘结晶抑制层由相对于第一和第二介电层具有较高结晶温度特性的材料形成。

3. 发明授权

US07964462B2 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07964462B2
公开(公告)日：2011-06-21
申请号：US12270033
申请日：2008-11-13
申请人： Dong-chul Yoo , Han-mei Choi , Kwang-hee Lee , Kyong-won An , Cha-young Yoo
发明人： Dong-chul Yoo , Han-mei Choi , Kwang-hee Lee , Kyong-won An , Cha-young Yoo
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , H01L21/02178 , H01L21/02181 , H01L21/022 , H01L21/02271 , H01L21/02337 , H01L21/3115 , H01L21/3162 , H01L21/31645 , H01L29/513 , H01L29/66825 , H01L29/66833 , H01L29/7881
摘要： Provided is a method of manufacturing a semiconductor device. The method includes: forming a charge storage layer on a substrate on which a gate insulating layer is formed; forming a first metal oxide layer on the charge storage layer using a first reaction source including a metal oxide layer precursor and a first oxidizing agent and changing the first metal oxide layer to a second metal oxide layer using a second reaction source including a second oxidizing agent having larger oxidizing power than the first oxidizing agent and repeating the forming of the first metal oxide layer and the changing of the first metal oxide layer to the second metal oxide layer several times to form a blocking insulating layer; and forming an electrode layer on the blocking insulating layer.
摘要翻译：提供一种制造半导体器件的方法。该方法包括：在其上形成有栅极绝缘层的基板上形成电荷存储层; 使用包括金属氧化物层前体和第一氧化剂的第一反应源在电荷存储层上形成第一金属氧化物层，并且使用包括第二氧化剂的第二反应源将第一金属氧化物层改变为第二金属氧化物层具有比第一氧化剂更大的氧化能力，并且重复形成第一金属氧化物层和将第一金属氧化物层改变为第二金属氧化物层数次以形成阻挡绝缘层; 以及在所述阻挡绝缘层上形成电极层。

4. 发明授权

US07723770B2 Integrated circuit capacitors having composite dielectric layers therein containing crystallization inhibiting regions 有权
标题翻译：集成电路电容器，其中包含结晶抑制区的复合介电层
公开(公告)号：US07723770B2
公开(公告)日：2010-05-25
申请号：US11210332
申请日：2005-08-24
申请人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Young-sun Kim , Se-hoon Oh
发明人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Young-sun Kim , Se-hoon Oh
IPC分类号： H01L27/108
CPC分类号： H01L29/92 , H01L27/10852 , H01L28/40
摘要： Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.
摘要翻译：集成电路电容器在其中具有复合电介质层。这些复合电介质层包括用于增加复合介电层的整体结晶温度的结晶抑制区。集成电路电容器包括第一和第二电容器电极和在第一和第二电容器电极之间延伸的电容器介电层。电容器介电层包括邻近第一电容器电极延伸的第一电介质层，邻近第二电容器电极延伸的第二电介质层和在第一和第二电介质层之间延伸的电绝缘的结晶抑制层的复合材料。电绝缘结晶抑制层由相对于第一和第二介电层具有较高结晶温度特性的材料形成。

5. 发明申请

US20100117194A1 METAL-INSULATOR-METAL CAPACITORS WITH A CHEMICAL BARRIER LAYER IN A LOWER ELECTRODE 审中-公开
标题翻译：金属绝缘体 - 金属电容器，在较低的电极中具有化学障碍层
公开(公告)号：US20100117194A1
公开(公告)日：2010-05-13
申请号：US12639184
申请日：2009-12-16
申请人： Eun-ae Chung , Jae-hyoung Choi , Jung-hee Chung , Young-sun Kim , Cha-young Yoo
发明人： Eun-ae Chung , Jae-hyoung Choi , Jung-hee Chung , Young-sun Kim , Cha-young Yoo
IPC分类号： H01L29/92 , H01G4/06 , H01G4/008
CPC分类号： H01L21/7687 , H01L27/10852 , H01L28/65 , H01L28/75
摘要： A metal-insulator-metal (MIM) capacitor includes a lower electrode, a dielectric layer, and an upper electrode. The lower electrode includes a first conductive layer, a chemical barrier layer on the first conductive layer, and a second conductive layer on the chemical barrier layer. The chemical barrier layer is between the first and second conductive layers and is a different material than the first and second conductive layers. The dielectric layer is on the lower electrode. The upper electrode is on the dielectric layer opposite to the lower electrode. The first and second conductive layers can have the same thickness. The chemical barrier layer can be thinner than each of the first and second conductive layers. Related methods are discussed.
摘要翻译：金属绝缘体金属（MIM）电容器包括下电极，电介质层和上电极。下电极包括第一导电层，第一导电层上的化学阻挡层和化学阻挡层上的第二导电层。化学屏障层位于第一和第二导电层之间，并且是与第一和第二导电层不同的材料。介电层位于下电极上。上电极位于与下电极相对的电介质层上。第一和第二导电层可以具有相同的厚度。化学阻挡层可以比第一和第二导电层中的每一个薄。讨论相关方法。

6. 发明申请

US20090127611A1 NON-VOLATILE MEMORY DEVICE AND MEMORY CARD AND SYSTEM INCLUDING THE SAME 审中-公开
标题翻译：非易失性存储器件和包括其的存储卡和系统
公开(公告)号：US20090127611A1
公开(公告)日：2009-05-21
申请号：US12120443
申请日：2008-05-14
申请人： Ki-yeon Park , Cha-young Yoo , Sung-hae Lee , Jun-noh Lee , Min-kyung Ryu
发明人： Ki-yeon Park , Cha-young Yoo , Sung-hae Lee , Jun-noh Lee , Min-kyung Ryu
IPC分类号： H01L29/792 , H01L29/788
CPC分类号： H01L29/513 , H01L29/40114 , H01L29/40117 , H01L29/42324 , H01L29/4234
摘要： A non-volatile memory device includes a semiconductor layer including source and drain regions and a channel region between the source and drain regions; a tunneling insulating layer on the channel region of the semiconductor layer; a charge storage layer on the tunneling insulating layer; a blocking insulating layer on the charge storage layer and including a first oxide layer with a first thickness, a high-k dielectric layer, and a second oxide layer with a second thickness different from the first thickness that are stacked sequentially on the charge storage layer; and a control gate on the blocking insulating layer.
摘要翻译：非易失性存储器件包括包括源区和漏区的半导体层和源区和漏区之间的沟道区; 在半导体层的沟道区上的隧道绝缘层; 隧道绝缘层上的电荷存储层; 电荷存储层上的阻挡绝缘层，并且包括具有第一厚度的第一氧化物层，高k电介质层和具有不同于第一厚度的第二厚度的第二氧化物层，其顺次层叠在电荷存储层上 ; 和阻挡绝缘层上的控制栅极。

7. 发明授权

US07304367B2 Metal-insulator-metal capacitors including transition metal silicide films on doped polysilicon contact plugs 有权
标题翻译：金属绝缘体金属电容器，包括掺杂多晶硅接触插头上的过渡金属硅化物膜
公开(公告)号：US07304367B2
公开(公告)日：2007-12-04
申请号：US10870745
申请日：2004-06-17
申请人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Nam-myun Cho , Jeong-sik Choi , Se-hoon Oh , Dong-kyun Park
发明人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Nam-myun Cho , Jeong-sik Choi , Se-hoon Oh , Dong-kyun Park
IPC分类号： H01L29/00
CPC分类号： H01L28/91
摘要： A MIM capacitor can include a doped polysilicon contact plug in an interlayer insulating film. A lower electrode of the MIM capacitor includes a transition metal nitride film is on the doped polysilicon contact plug. A transition metal silicide film is between the doped polysilicon contact plug and the transition metal nitride film.
摘要翻译： MIM电容器可以包括层间绝缘膜中的掺杂多晶硅接触插塞。 MIM电容器的下电极包括在掺杂多晶硅接触插塞上的过渡金属氮化物膜。过渡金属硅化物膜位于掺杂多晶硅接触插塞和过渡金属氮化物膜之间。

8. 发明申请

US20070099419A1 Methods for forming semiconductor devices including thermal processing 有权
公开(公告)号：US20070099419A1
公开(公告)日：2007-05-03
申请号：US11641138
申请日：2006-12-19
申请人： Jae-hyoung Choi , Wan-don Kim , Cha-young Yoo , Suk-jin Chung
发明人： Jae-hyoung Choi , Wan-don Kim , Cha-young Yoo , Suk-jin Chung
IPC分类号： H01L21/44
CPC分类号： H01L28/65 , H01L28/40
摘要： Methods for fabricating semiconductor memory devices may include forming a first conductive layer for a first electrode on a semiconductor substrate, forming a dielectric layer on the first conductive layer, and forming a second conductive layer for a second electrode on the dielectric layer. Portions of the second conductive layer and the dielectric layer can be removed, and a thermal process can be performed on the second conductive layer and the dielectric layer. The thermal process can reduce interface stress between the second conductive layer and the dielectric layer and/or cure the dielectric layer. In addition, the dielectric layer may be maintained in an amorphous state during and after the thermal process.

9. 发明授权

US07172946B2 Methods for forming semiconductor devices including thermal processing 失效
标题翻译：用于形成包括热处理的半导体器件的方法
公开(公告)号：US07172946B2
公开(公告)日：2007-02-06
申请号：US10629430
申请日：2003-07-29
申请人： Jae-hyoung Choi , Wan-don Kim , Cha-young Yoo , Suk-jin Chung
发明人： Jae-hyoung Choi , Wan-don Kim , Cha-young Yoo , Suk-jin Chung
IPC分类号： H01L21/20
CPC分类号： H01L28/65 , H01L28/40
摘要： Methods for fabricating semiconductor memory devices may include forming a first conductive layer for a first electrode on a semiconductor substrate, forming a dielectric layer on the first conductive layer, and forming a second conductive layer for a second electrode on the dielectric layer. Portions of the second conductive layer and the dielectric layer can be removed, and a thermal process can be performed on the second conductive layer and the dielectric layer. The thermal process can reduce interface stress between the second conductive layer and the dielectric layer and/or cure the dielectric layer. In addition, the dielectric layer may be maintained in an amorphous state during and after the thermal process.
摘要翻译：用于制造半导体存储器件的方法可以包括在半导体衬底上形成用于第一电极的第一导电层，在第一导电层上形成电介质层，以及在电介质层上形成用于第二电极的第二导电层。可以去除第二导电层和电介质层的部分，并且可以在第二导电层和电介质层上进行热处理。热处理可以减少第二导电层和电介质层之间的界面应力和/或固化电介质层。此外，在热处理期间和之后，电介质层可以保持在非晶状态。

10. 发明申请

US20060166476A1 Method of forming a dielectric structure having a high dielectric constant and method of manufacturing a semiconductor device having the dielectric structure 有权
标题翻译：具有高介电常数的介电结构的形成方法和具有电介质结构的半导体器件的制造方法
公开(公告)号：US20060166476A1
公开(公告)日：2006-07-27
申请号：US11339416
申请日：2006-01-25
申请人： Jong-Cheol Lee , Sung-Tae Kim , Young-Sun Kim , Cha-Young Yoo , Gab-Jin Nam , Young-Geun Park , Jae-Hyoung Choi , Jae-Hyun Yeo , Ha-Jin Lim , Yun-Seok Kim
发明人： Jong-Cheol Lee , Sung-Tae Kim , Young-Sun Kim , Cha-Young Yoo , Gab-Jin Nam , Young-Geun Park , Jae-Hyoung Choi , Jae-Hyun Yeo , Ha-Jin Lim , Yun-Seok Kim
IPC分类号： H01L21/471
CPC分类号： H01L21/022 , C23C14/5826 , C23C14/586 , C23C16/56 , H01L21/02142 , H01L21/02252 , H01L21/28273 , H01L21/3141 , H01L21/3143 , H01L21/31645 , H01L27/10852 , H01L27/10873 , H01L27/115 , H01L27/11521 , H01L28/40 , H01L29/513 , H01L29/517 , H01L29/78
摘要： In a method of manufacturing a dielectric structure, after a first dielectric layer is formed on a substrate by using a metal oxide doped with silicon, the substrate is placed on a susceptor of a chamber. By treating the first dielectric layer with a plasma in controlling a voltage difference between the susceptor and a ground, a second dielectric layer is formed on the first dielectric layer. The second dielectric layer including a metal oxynitride doped with silicon having enough content of nitrogen is formed on the first dielectric layer. Therefore, dielectric properties of the dielectric structure comprising the first and the second dielectric layers can be improved and a leakage current can be greatly decreased. By adapting the dielectric structure to a gate insulation layer and/or to a dielectric layer of a capacitor or of a non-volatile semiconductor memory device, capacitances and electrical properties can be improved.
摘要翻译：在制造电介质结构的方法中，在通过使用掺杂有硅的金属氧化物在基板上形成第一介电层之后，将基板放置在室的基座上。通过在控制基座和接地之间的电压差的同时用等离子体处理第一电介质层，在第一电介质层上形成第二电介质层。在第一电介质层上形成包括掺杂有足够的氮含量的硅的金属氮氧化物的第二电介质层。因此，可以提高包括第一和第二电介质层的电介质结构的介电性能，并且可以大大降低泄漏电流。通过使电介质结构适应于栅极绝缘层和/或电容器或非易失性半导体存储器件的电介质层，可以提高电容和电性能。

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