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    • 1. 发明授权
    • Internal voltage generating circuit of a semiconductor device using test pad and a method thereof
    • 使用测试焊盘的半导体器件的内部电压产生电路及其方法
    • US06184720B2
    • 2001-02-06
    • US09334920
    • 1999-06-17
    • Young Hee KimJin Keun Oh
    • Young Hee KimJin Keun Oh
    • H03K908
    • G01R31/31715G01R31/31712G01R31/318575G05F1/465
    • An internal voltage generating circuit and method for generating thereof in semiconductor device capable of performing test without any needless transfer between a test equipment and a repair equipment are disclosed. The circuit includes a plurality of test power voltage pads, each of which can be selectively applied with the external power voltage and a ground voltage during test; a fuse programmable control signal generator coupled to the plurality of test power voltage pads for generating a control signal according to the signals applied to the plurality of the test power voltage pads during test, and for generating the control signal according to fuse-programmed state after at least one fuse included therein is programmed; a reference voltage generator for receiving the external power voltage so as to produce a reference voltage having a predetermined level; and a voltage trimming unit for trimming the reference voltage in accordance with the output of the fuse programmable control signal generator.
    • 公开了一种内部电压产生电路及其在半导体器件中的生成方法,能够在测试设备和维修设备之间进行无需传输的测试。 该电路包括多个测试电源电压焊盘,每个测试电源焊盘可以在测试期间选择性地施加外部电源电压和接地电压; 熔丝可编程控制信号发生器,其耦合到所述多个测试电源电压焊盘,用于根据在测试期间施加到所述多个测试电源电压焊盘的信号产生控制信号,并且用于根据熔丝编程状态生成所述控制信号 其中包括的至少一个保险丝被编程; 参考电压发生器,用于接收外部电源电压以产生具有预定电平的参考电压; 以及电压修整单元,用于根据熔丝可编程控制信号发生器的输出修整参考电压。
    • 2. 发明授权
    • Semiconductor memory test circuit and method for the same
    • 半导体存储器测试电路及其方法相同
    • US06389563B1
    • 2002-05-14
    • US09340731
    • 1999-06-29
    • Jin Keun OhYoung Hee Kim
    • Jin Keun OhYoung Hee Kim
    • G11C2900
    • G11C29/34G11C29/40G11C29/46
    • A semiconductor memory test circuit and a method for the same to reduce the test time in testing a semiconductor memory. The semiconductor memory test circuit includes: a parallel test circuit for performing a parallel test when inputting a battery backup signal (bbu), a column address signal (cas5), a CAS before RAS signal (cbr), a write enable signal (ew), a power-up bar signal (pwrupb), and a row address signal (ras71)); and a test mode circuit which is controlled by a combination of a parallel test signal (pt) and the battery backup signal (bbu) generated from the parallel test circuit, and generates a test time reduction signal (ttrb), whereby the semiconductor memory test circuit compresses one least significant bit indicating a row address of a device in the case of a 4K refresh operation when the test time reduction signal (ttrb) is enabled, and compresses two least significant bits indicating a row address of a device in the case of an 8K refresh operation when the test time reduction signal (ttrb) is enabled.
    • 一种半导体存储器测试电路及其方法,用于减少测试半导体存储器的测试时间。 半导体存储器测试电路包括:并行测试电路,用于在输入电池备用信号(bbu),列地址信号(cas5),RAS信号(cbr)之前的CAS,写使能信号(ew) ,上电条信号(pwrupb)和行地址信号(ras71)); 以及由并行测试电路产生的并行测试信号(pt)和电池备用信号(bbu)的组合控制的测试模式电路,并且产生测试时间减少信号(ttrb),由此半导体存储器测试 当测试时间减少信号(ttrb)被使能时,在4K刷新操作的情况下,电路压缩指示设备的行地址的一个最低有效位,并且在两个最低有效位的情况下压缩指示设备的行地址的两个最低有效位 当测试时间减少信号(ttrb)被使能时,8K刷新操作。
    • 3. 发明授权
    • Anti-fuse programming circuit with cross-coupled feedback loop
    • 具有交叉耦合反馈回路的反熔丝编程电路
    • US6133778A
    • 2000-10-17
    • US342140
    • 1999-06-29
    • Young Hee KimKie Bong Ku
    • Young Hee KimKie Bong Ku
    • G06F12/16G11C17/18G11C29/00G11C29/04H01H85/00H01H85/30G11C17/00
    • G11C17/18
    • An anti-fuse programming circuit comprising an operation switching part for precharging the anti-fuse programming circuit with a half voltage to operate it, an anti-fuse connected to the operation switching part, the anti-fuse being subjected to a dielectric breakdown when it is supplied with an overcurrent, a sense signal input part for inputting a sense signal to verify a programmed state of the anti-fuse, a breakdown voltage supply part for supplying a source voltage for the dielectric breakdown of the anti-fuse, an output part for outputting a signal indicative of the programmed state of the anti-fuse in response to the sense signal inputted by the sense signal input part, a feedback part for feeding back the output signal from the output part strongly at low power and high speed, a current blocking part for blocking a current path from the breakdown voltage supply part to the anti-fuse in response to a control signal from the feedback part, a reverse current prevention part for blocking the flow of current from the feedback part to the output part, and a latch part for strongly stabilizing the anti-fuse at the level of the half voltage in response to a control signal from the output part. Current consumption can significantly be reduced in programming the anti-fuse.
    • 一种反熔丝编程电路,包括用于对反熔丝编程电路进行预充电以操作其的半导体电压的操作切换部分,连接到操作切换部分的反熔丝,当反熔丝经受绝缘击穿时 被提供有过电流,感测信号输入部分,用于输入感测信号以验证反熔丝的编程状态;击穿电压提供部分,用于提供用于反熔丝的介质击穿的源电压;输出部分 用于响应于由感测信号输入部分输入的感测信号输出表示反熔丝的编程状态的信号,用于以低功率和高速强烈地从输出部分反馈输出信号的反馈部分, 电流阻挡部分,用于响应于来自反馈部分的控制信号阻断从击穿电压供应部分到抗熔丝的电流路径,用于bl的反向电流防止部分 抑制从反馈部分到输出部分的电流流动,以及用于响应于来自输出部分的控制信号,在半电压电平下强烈稳定反熔丝的锁存部分。 电抗消融可以显着减少编程反熔丝。
    • 5. 发明申请
    • Method for forming colored oxide film layer on nickel plating or chrome plating layer
    • 在镀镍或镀铬层上形成有色氧化物膜层的方法
    • US20080008830A1
    • 2008-01-10
    • US11653210
    • 2007-01-16
    • Young Hee Kim
    • Young Hee Kim
    • B05D5/06B05D3/02
    • C23C8/16C23C8/02C25D5/48
    • The present invention provides a method for forming a colored oxide film layer on the surface of an article made of iron or a non-iron metal, by subjecting a nickel plating or chrome plating layer formed on the surface of the article to oxidizing heat treatment, in order to impart high corrosion resistance and a variety of vivid colors to the article. The method for forming a colored oxide film layer according to the present invention comprises the steps of: (a) subjecting an article made of iron or a non-iron metal to nickel plating or chrome plating; and (b) subjecting the article thus treated in step (a) to oxidizing heat treatment in an oxidizing atmosphere at 200 to 500° C. for 1 minute to 20 hours, to form a colored oxide film layer on the surface of the plating layer.
    • 本发明提供一种在由铁或非铁金属制成的制品的表面上形成着色氧化物膜层的方法,该方法是将形成在制品表面上的镀镍或镀铬层进行氧化热处理, 以便赋予制品高的耐腐蚀性和各种生动的颜色。 根据本发明的形成有色氧化物膜层的方法包括以下步骤:(a)对由铁或非铁金属制成的物品进行镀镍或镀铬; 和(b)使在步骤(a)中处理的制品在200-500℃的氧化气氛中进行氧化处理1分钟至20小时,以在镀层的表面上形成着色氧化物膜层 。
    • 8. 发明申请
    • Force Transfer Mechanism
    • 力转移机制
    • US20130152713A1
    • 2013-06-20
    • US13819517
    • 2011-08-26
    • Young Hee Kim
    • Young Hee Kim
    • F16H21/44F16H19/04
    • F16H21/44F16F15/046F16F2232/00F16H19/04F16H25/183Y10T74/18096Y10T74/18992
    • A force transfer mechanism includes cylindrical guide housing; a movable body which is slidably arranged in the guide housing so as to move in a linear direction by means of an externally applied force, and which includes a cutout groove having one or more inclined surfaces, and through-holes formed in a direction perpendicular to the linear motion direction in portions corresponding to the inclined surfaces; and a slave unit, one end of which is coupled to the movable body such that said end passes through the through-holes of the movable body and moves along the inclined surfaces of the cutout groove vertically relative to the movement direction of the movable body, and the other end of which is elastically supported.
    • 力传递机构包括圆柱形引导壳体; 可移动体,其可滑动地布置在所述引导壳体中,以便通过外力施加在线性方向上移动,并且其包括具有一个或多个倾斜表面的切口槽,以及沿垂直于所述导向壳体的方向形成的通孔 对应于倾斜表面的部分的直线运动方向; 以及一个从动单元,其一端联接到可移动体,使得所述端部穿过可移动体的通孔,并且沿切口槽的倾斜表面相对于可移动体的移动方向垂直移动, 并且其另一端被弹性地支撑。