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1. 发明授权

US06323720B1 Internal voltage generator using anti-fuse 有权
标题翻译：内部电压发生器采用防熔丝
公开(公告)号：US06323720B1
公开(公告)日：2001-11-27
申请号：US09342218
申请日：1999-06-29
申请人： Young-Hee Kim , Kie Bong Ku
发明人： Young-Hee Kim , Kie Bong Ku
IPC分类号： G05F110
CPC分类号： G05F1/465
摘要： The present invention relates to an internal voltage generator using anti-fuse, which generates decoding signals using anti-fuses capable of being programmed by signals inputted from the outside, and then generates the internal voltages, each of them having a different level, thereby conveniently trimming the internal voltage to be suitable for an external environment even at a packaging step process of a semiconductor device. Decoding means for generating the decoding signals includes: buffer means changing voltage signals of TTL level inputted through bonding pads to those of CMOS level; programming signal generation means generating signals for programming the anti-fuses in accordance with signals from said buffer means; a plurality of anti-fuse means having the anti-fuses capable of being programmed by the signals from said programming signal generation means, and outputting signals in response to a state of the anti-fuses; and output means performing a logical operation of the signals from said anti-fuse means, thereby outputting said decoding signals.
摘要翻译：本发明涉及一种使用反熔丝的内部电压发生器，其使用能够通过从外部输入的信号进行编程的抗熔丝产生解码信号，然后产生每个具有不同电平的内部电压，从而方便即使在半导体器件的封装步骤处理中，内部电压也适合于外部环境。用于产生解码信号的解码装置包括：缓冲装置，将通过接合焊盘输入的TTL电平的电压信号改变为CMOS电平的电平; 编程信号发生装置根据来自所述缓冲装置的信号产生用于编程抗熔丝的信号; 多个反熔丝装置，其具有能够由所述编程信号发生装置的信号编程的反熔丝，并且响应于防熔丝的状态输出信号; 以及输出装置，执行来自所述反熔丝装置的信号的逻辑运算，由此输出所述解码信号。

2. 发明授权

US6133778A Anti-fuse programming circuit with cross-coupled feedback loop 有权
标题翻译：具有交叉耦合反馈回路的反熔丝编程电路
公开(公告)号：US6133778A
公开(公告)日：2000-10-17
申请号：US342140
申请日：1999-06-29
申请人： Young Hee Kim , Kie Bong Ku
发明人： Young Hee Kim , Kie Bong Ku
IPC分类号： G06F12/16 , G11C17/18 , G11C29/00 , G11C29/04 , H01H85/00 , H01H85/30 , G11C17/00
CPC分类号： G11C17/18
摘要： An anti-fuse programming circuit comprising an operation switching part for precharging the anti-fuse programming circuit with a half voltage to operate it, an anti-fuse connected to the operation switching part, the anti-fuse being subjected to a dielectric breakdown when it is supplied with an overcurrent, a sense signal input part for inputting a sense signal to verify a programmed state of the anti-fuse, a breakdown voltage supply part for supplying a source voltage for the dielectric breakdown of the anti-fuse, an output part for outputting a signal indicative of the programmed state of the anti-fuse in response to the sense signal inputted by the sense signal input part, a feedback part for feeding back the output signal from the output part strongly at low power and high speed, a current blocking part for blocking a current path from the breakdown voltage supply part to the anti-fuse in response to a control signal from the feedback part, a reverse current prevention part for blocking the flow of current from the feedback part to the output part, and a latch part for strongly stabilizing the anti-fuse at the level of the half voltage in response to a control signal from the output part. Current consumption can significantly be reduced in programming the anti-fuse.
摘要翻译：一种反熔丝编程电路，包括用于对反熔丝编程电路进行预充电以操作其的半导体电压的操作切换部分，连接到操作切换部分的反熔丝，当反熔丝经受绝缘击穿时被提供有过电流，感测信号输入部分，用于输入感测信号以验证反熔丝的编程状态;击穿电压提供部分，用于提供用于反熔丝的介质击穿的源电压;输出部分用于响应于由感测信号输入部分输入的感测信号输出表示反熔丝的编程状态的信号，用于以低功率和高速强烈地从输出部分反馈输出信号的反馈部分，电流阻挡部分，用于响应于来自反馈部分的控制信号阻断从击穿电压供应部分到抗熔丝的电流路径，用于bl的反向电流防止部分抑制从反馈部分到输出部分的电流流动，以及用于响应于来自输出部分的控制信号，在半电压电平下强烈稳定反熔丝的锁存部分。电抗消融可以显着减少编程反熔丝。

3. 发明授权

US08027210B2 Data input apparatus with improved setup/hold window 失效
标题翻译：具有改进的建立/保持窗口的数据输入设备
公开(公告)号：US08027210B2
公开(公告)日：2011-09-27
申请号：US12199046
申请日：2008-08-27
申请人： Kie Bong Ku , Kwang Jun Cho
发明人： Kie Bong Ku , Kwang Jun Cho
IPC分类号： G11C7/00
CPC分类号： G11C7/1072 , G11C7/1078 , G11C7/1084 , G11C7/109 , G11C7/1093 , G11C7/22 , G11C7/225 , G11C8/06 , G11C8/18
摘要： In the data input apparatus, a data delay unit outputs data input from outside the data input apparatice. The data delay unit varies the degree of delay in response to a test mode signal. A data alignment signal generating unit receives a first signal synchronized with an external clock signal and a second signal synchronized with a data strobe signal, and the data alignment signal generating unit outputs one of the first signal and the second signal as a data alignment signal in response to the test mode signal. A data alignment unit is synchronized with the data alignment signal to align the data delayed in the data delay unit. The data input apparatus improves the setup/hold window when a semiconductor memory device is in the test mode.
摘要翻译：在数据输入装置中，数据延迟单元输出从数据输入装置外部输入的数据。数据延迟单元改变响应于测试模式信号的延迟程度。数据对准信号发生单元接收与外部时钟信号同步的第一信号和与数据选通信号同步的第二信号，并且数据对准信号生成单元将第一信号和第二信号中的一个作为数据对准信号输出响应测试模式信号。数据对准单元与数据对准信号同步，以对准在数据延迟单元中延迟的数据。当半导体存储器件处于测试模式时，数据输入设备改进了建立/保持窗口。

4. 发明授权

US08520462B2 Semiconductor memory apparatus 失效
标题翻译：半导体存储装置
公开(公告)号：US08520462B2
公开(公告)日：2013-08-27
申请号：US13189969
申请日：2011-07-25
申请人： Kie Bong Ku
发明人： Kie Bong Ku
IPC分类号： G11C5/14
CPC分类号： G11C7/1045 , G11C11/4074 , G11C29/83 , G11C29/883
摘要： A semiconductor memory apparatus includes a memory cell array including a plurality of chips, a control circuit configured to control an internal operation of the memory cell array, a power circuit configured to supply power to the control circuit, and a mode setting circuit configured to output a flag signal for power supply control based on a mode register set command and data received through a data input/output pad, in response to a clock enable signal.
摘要翻译：一种半导体存储装置，包括：包含多个芯片的存储单元阵列;控制电路，被配置为控制存储单元阵列的内部动作;电源电路，被配置为向所述控制电路供电;以及模式设定电路，响应于时钟使能信号，基于模式寄存器设置命令和通过数据输入/输出板接收的数据的电源控制的标志信号。

5. 发明申请

US20120218849A1 SEMICONDUCTOR MEMORY APPARATUS 失效
标题翻译：半导体存储器
公开(公告)号：US20120218849A1
公开(公告)日：2012-08-30
申请号：US13189969
申请日：2011-07-25
申请人： Kie Bong Ku
发明人： Kie Bong Ku
IPC分类号： G11C5/14
CPC分类号： G11C7/1045 , G11C11/4074 , G11C29/83 , G11C29/883
摘要： A semiconductor memory apparatus includes a memory cell array including a plurality of chips, a control circuit configured to control an internal operation of the memory cell array, a power circuit configured to supply power to the control circuit, and a mode setting circuit configured to output a flag signal for power supply control based on a mode register set command and data received through a data input/output pad, in response to a clock enable signal.
摘要翻译：一种半导体存储装置，包括：包含多个芯片的存储单元阵列;控制电路，被配置为控制存储单元阵列的内部动作;电源电路，被配置为向所述控制电路供电;以及模式设定电路，响应于时钟使能信号，基于模式寄存器设置命令和通过数据输入/输出板接收的数据的电源控制的标志信号。

6. 发明申请

US20070242531A1 WRITE APPARATUS FOR DDR SDRAM SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译： DDR SDRAM半导体存储器件的写入装置
公开(公告)号：US20070242531A1
公开(公告)日：2007-10-18
申请号：US11687285
申请日：2007-03-16
申请人： Kie Bong Ku , Kwang Jun Cho
发明人： Kie Bong Ku , Kwang Jun Cho
IPC分类号： G11C7/10
CPC分类号： G11C7/1039 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/1096
摘要： A writing apparatus of a semiconductor memory device includes a pulse generator, a latch unit and an output latch unit. The pulse generator outputs a first pulse every rising edge of a data strobe pulse and a second pulse every falling edge of the data strobe pulse, respectively. The latch unit latches data input every rising edge of the first pulse, latches data input every rising edge of the second pulse and the latched data, respectively, and allocates the latched data to first and second data lines. The output latch unit latches data, which are firstly allocated to the first and second data lines, in response to a first control signal, and latches data, which are secondly allocated to the first and second data lines, in response to a second control signal.
摘要翻译：半导体存储器件的写入装置包括脉冲发生器，锁存单元和输出锁存单元。脉冲发生器分别在数据选通脉冲的每个下降沿沿数据选通脉冲的每个上升沿和第二脉冲输出第一脉冲。锁存单元在第一脉冲的每个上升沿锁存数据输入，分别锁存在第二脉冲的上升沿和锁存数据上的数据输入，并将锁存的数据分配给第一和第二数据线。输出锁存单元响应于第一控制信号锁存首先分配给第一和第二数据线的数据，并且响应于第二控制信号锁存第二分配给第一和第二数据线的数据。

7. 发明授权

US07679969B2 Semiconductor memory device utilizing data mask signal for sharing an input/output channel in a test mode and data output method using the same 失效
标题翻译：半导体存储器件利用用于在测试模式下共享输入/输出通道的数据掩码信号和使用其的数据输出方法
公开(公告)号：US07679969B2
公开(公告)日：2010-03-16
申请号：US12141169
申请日：2008-06-18
申请人： Kie Bong Ku
发明人： Kie Bong Ku
IPC分类号： G11C7/10
CPC分类号： G11C29/12 , G11C29/1201
摘要： A semiconductor device receives a first data mask signal and a second data mask signal. A data mask control unit outputs a data mask control signal by combining a test mode signal with the first data mask signal. A data clock output unit receives a delay locked loop (DLL) clock and outputs a data clock in response to the data mask control signal. A column address enable (YAE) control signal generating unit generates a column address enable control signal to control the enablement of a column address enable signal. The column address enable control signal generating unit generates the column address enable control signal by combining the test mode signal with the second data mask signal.
摘要翻译：半导体器件接收第一数据掩码信号和第二数据掩码信号。数据掩码控制单元通过将测试模式信号与第一数据掩码信号组合来输出数据掩码控制信号。数据时钟输出单元接收延迟锁定环（DLL）时钟，并响应于数据掩码控制信号而输出数据时钟。列地址使能（YAE）控制信号生成单元生成列地址使能控制信号，以控制列地址使能信号的使能。列地址使能控制信号生成单元通过将测试模式信号与第二数据掩码信号组合来生成列地址使能控制信号。

8. 发明授权

US07671646B2 Delay locked loop 有权
标题翻译：延迟锁定环路
公开(公告)号：US07671646B2
公开(公告)日：2010-03-02
申请号：US12421434
申请日：2009-04-09
申请人： Kwang Jun Cho , Kie Bong Ku
发明人： Kwang Jun Cho , Kie Bong Ku
IPC分类号： H03L7/06
CPC分类号： H03K5/1565
摘要： The digital duty cycle correction circuit according to the present invention includes a first conversion circuit for buffering an internal clock output from a delay locked loop (DLL), converting the buffered internal clock into first and second clocks through first and second terminals, delaying the second clock according to voltage supplied to the second terminal through a capacitor, converting the delayed second clock into a first signal, and converting the first clock into a third clock, which rises at a falling edge of the first clock and falls at a rising edge of the first signal; and a second conversion circuit for converting the third clock into an output clock, which rises at a falling edge of the third clock and falls at a rising edge of the third clock.
摘要翻译：根据本发明的数字占空比校正电路包括用于缓冲来自延迟锁定环（DLL）的内部时钟输出的第一转换电路，通过第一和第二终端将缓冲的内部时钟转换成第一和第二时钟，延迟第二时钟，根据通过电容器提供给第二终端的电压，将延迟的第二时钟转换为第一信号，并将第一时钟转换为第三时钟，第三时钟在第一时钟的下降沿上升，并且下降到第一个信号; 以及第二转换电路，用于将第三时钟转换为在第三时钟的下降沿上升并在第三时钟的上升沿下降的输出时钟。

9. 发明授权

US07548100B2 Delay locked loop 有权
标题翻译：延迟锁定环路
公开(公告)号：US07548100B2
公开(公告)日：2009-06-16
申请号：US11687396
申请日：2007-03-16
申请人： Kwang Jun Cho , Kie Bong Ku
发明人： Kwang Jun Cho , Kie Bong Ku
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： The digital duty cycle correction circuit according to the present invention includes a first conversion circuit for buffering an internal clock output from a delay locked loop (DLL), converting the buffered internal clock into first and second clocks through first and second terminals, delaying the second clock according to voltage supplied to the second terminal through a capacitor, converting the delayed second clock into a first signal, and converting the first clock into a third clock, which rises at a falling edge of the first clock and falls at a rising edge of the first signal; and a second conversion circuit for converting the third clock into an output clock, which rises at a falling edge of the third clock and falls at a rising edge of the third clock.
摘要翻译：根据本发明的数字占空比校正电路包括用于缓冲来自延迟锁定环（DLL）的内部时钟输出的第一转换电路，通过第一和第二终端将缓冲的内部时钟转换成第一和第二时钟，延迟第二时钟，根据通过电容器提供给第二终端的电压，将延迟的第二时钟转换为第一信号，并将第一时钟转换为第三时钟，第三时钟在第一时钟的下降沿上升，并且下降到第一个信号; 以及第二转换电路，用于将第三时钟转换为在第三时钟的下降沿上升并在第三时钟的上升沿下降的输出时钟。

10. 发明授权

US08237486B2 Clock control circuit and semiconductor memory apparatus using the same 有权
标题翻译：时钟控制电路及使用其的半导体存储装置
公开(公告)号：US08237486B2
公开(公告)日：2012-08-07
申请号：US12965372
申请日：2010-12-10
申请人： Kie Bong Ku
发明人： Kie Bong Ku
IPC分类号： H03K3/00
CPC分类号： G11C7/222
摘要： An internal clock frequency control circuit of a semiconductor memory apparatus includes a mode register set configured to receive a mode register set control signal and output a mode register set signal; a delay unit configured to generate an enable signal when a predetermined cycle has elapsed after the mode register set signal was activated; a division command decoder configured to receive and decode a synchronization command to generate a division start signal when the enable signal is activated; and a division selection unit configured to receive an input clock having a first frequency and output a selection clock having a second frequency, wherein a value of the second frequency is substantially the same as the first frequency or lower than the first frequency depending on a level of the division start signal.
摘要翻译：半导体存储装置的内部时钟频率控制电路包括：模式寄存器组，被配置为接收模式寄存器组控制信号并输出模式寄存器设置信号; 延迟单元，被配置为在模式寄存器设置信号被激活之后经过了预定周期时产生使能信号; 分配命令解码器，被配置为当所述使能信号被激活时，接收和解码同步命令以产生除法开始信号; 以及分割选择单元，被配置为接收具有第一频率的输入时钟并输出具有第二频率的选择时钟，其中所述第二频率的值基本上与所述第一频率相同或者低于所述第一频率，的分割开始信号。

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