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1. 发明授权

US5835505A Semiconductor integrated circuit and system incorporating the same 失效
标题翻译：半导体集成电路和系统结合在一起
公开(公告)号：US5835505A
公开(公告)日：1998-11-10
申请号：US843581
申请日：1997-04-16
申请人： Yoshito Nishimichi , Satoshi Ogura , Shinji Ozaki , Seiji Tokunoh , Akira Miyoshi , Hiroaki Yamamoto , Yoshiaki Kasuga
发明人： Yoshito Nishimichi , Satoshi Ogura , Shinji Ozaki , Seiji Tokunoh , Akira Miyoshi , Hiroaki Yamamoto , Yoshiaki Kasuga
IPC分类号： G06F11/36 , G01R31/28 , G11C29/00
CPC分类号： G06F11/3648
摘要： A semiconductor integrated circuit includes a functional block realizing at least part of a function of the semiconductor integrated circuit. The functional block includes a plurality of basic cells and a plurality of terminal cells. Each of the plurality of terminal cells has a connector for mediating a communication between another semiconductor integrated circuit and one of the plurality of basic cells.
摘要翻译：半导体集成电路包括实现半导体集成电路的功能的至少一部分的功能块。功能块包括多个基本单元和多个终端单元。多个终端单元中的每一个具有用于中介另一半导体集成电路与多个基本单元中的一个之间的通信的连接器。

2. 发明授权

US5754813A Data processor 失效
标题翻译：数据处理器
公开(公告)号：US5754813A
公开(公告)日：1998-05-19
申请号：US811663
申请日：1997-03-05
申请人： Hiroaki Yamamoto , Shinji Ozaki , Yoshito Nishimichi
发明人： Hiroaki Yamamoto , Shinji Ozaki , Yoshito Nishimichi
IPC分类号： G06F9/38 , G06F9/40
CPC分类号： G06F9/382 , G06F9/3802 , G06F9/3814 , G06F9/3869
摘要： Two instruction execution units execute different types of instructions. Two instruction selection circuits are provided. Two instruction buses are coupled to an instruction standby unit having predecoders and an instruction queue. The instruction standby unit is connected by two wait instruction buses to the input sides of the instruction selection circuits. An instruction fetch control circuit detects an instruction that has not been executed by any of the instruction execution units. Such an unexecuted instruction waits in the instruction queue, thereafter being applied, together with its predecode result, to each instruction selection circuit to be selected at the next selection time. As a result of such arrangement, fast execution of different types of instructions in parallel is accomplished.
摘要翻译：两个指令执行单元执行不同类型的指令。提供两个指令选择电路。两个指令总线耦合到具有预解码器和指令队列的指令备用单元。指令备用单元通过两条等待指令总线连接到指令选择电路的输入侧。指令获取控制电路检测任何指令执行单元尚未执行的指令。这种未执行的指令在指令队列中等待，然后与其预解码结果一起应用于在下一个选择时间被选择的每个指令选择电路。作为这种安排的结果，可以实现并行执行不同类型指令的快速执行。

3. 发明授权

US5829021A System for controlling operating timing of a cache memory 失效
标题翻译：用于控制高速缓冲存储器的操作定时的系统
公开(公告)号：US5829021A
公开(公告)日：1998-10-27
申请号：US470933
申请日：1995-06-06
申请人： Hiroaki Yamamoto , Shinji Ozaki , Yoshito Nishimichi
发明人： Hiroaki Yamamoto , Shinji Ozaki , Yoshito Nishimichi
IPC分类号： G06F9/38 , G06F12/00
CPC分类号： G06F9/382 , G06F9/3802 , G06F9/3814 , G06F9/3869
摘要： Two instruction execution units execute different types of instructions. Two instruction selection circuits are provided. Two instruction buses are coupled to an instruction standby unit having predecoders and an instruction queue. The instruction standby unit is connected by two wait instruction buses to the input sides of the instruction selection circuits. An instruction fetch control circuit detects an instruction that has not been executed by any of the instruction execution units. Such an unexecuted instruction waits in the instruction queue, thereafter being applied, together with its predecode result, to each instruction selection circuit to be selected at the next selection time. As a result of such arrangement, fast execution of different types of instructions in parallel is accomplished.
摘要翻译：两个指令执行单元执行不同类型的指令。提供两个指令选择电路。两个指令总线耦合到具有预解码器和指令队列的指令备用单元。指令备用单元通过两条等待指令总线连接到指令选择电路的输入侧。指令获取控制电路检测任何指令执行单元尚未执行的指令。这种未执行的指令在指令队列中等待，然后与其预解码结果一起应用于在下一个选择时间被选择的每个指令选择电路。作为这种安排的结果，可以实现并行执行不同类型指令的快速执行。

4. 发明授权

US06480875B1 Adder circuit and associated layout structure 失效
标题翻译：加法器电路和相关布局结构
公开(公告)号：US06480875B1
公开(公告)日：2002-11-12
申请号：US08957159
申请日：1997-10-24
申请人： Akira Miyoshi , Hiroaki Yamamoto , Yoshito Nishimichi
发明人： Akira Miyoshi , Hiroaki Yamamoto , Yoshito Nishimichi
IPC分类号： G06F750
CPC分类号： G06F7/508 , H01L27/0207 , H01L27/092
摘要： In an adder circuit, a block carry generation logic over three consecutive digits is produced from the following equations. G0=g2+p2·g1+p2·p1·g0 /g0=/p2+/g2·/p1+/g2·/g1·/g0 In other words, the block carry generation logic /G0 is produced by a single PMOS transistor, a series circuit formed of two PMOS transistors connected in series, and a series circuit formed of three PMOS transistors connected in series. The block carry generation logic G0 is produced by a single NMOS transistor, a series circuit formed of two NMOS transistors connected in series, and a series circuit formed of three NMOS transistors connected in series. Block carry generation logics can be formed in such a way as to achieve not only a reduction of the layout area but also a higher operation rate.
摘要翻译：在加法器电路中，从以下等式产生三位连续位数的块载入生成逻辑。换句话说，块载入生成逻辑/ G0由单个PMOS晶体管产生，串联电路由两个PMOS晶体管形成，串联电路以及串联连接的3个PMOS晶体管构成的串联电路。块载入生成逻辑G0由单个NMOS晶体管，串联连接的两个NMOS晶体管构成的串联电路和由串联连接的三个NMOS晶体管构成的串联电路产生。块携带生成逻辑可以形成为不仅实现布局区域的减少，而且实现更高的操作速率。

5. 发明授权

US5941937A Layout structure for barrel shifter with decode circuit 失效
标题翻译：具有解码电路的桶形移位器的布局结构
公开(公告)号：US5941937A
公开(公告)日：1999-08-24
申请号：US959374
申请日：1997-10-28
申请人： Hiroaki Yamamoto , Yoshito Nishimichi
发明人： Hiroaki Yamamoto , Yoshito Nishimichi
IPC分类号： G06F5/01
CPC分类号： G06F5/015
摘要： Two flip-flops and decode circuits are provided. Whereas the one flip-flop receives 1-bit bit-shift-amount data B(1), the other flip-flop receives 1-bit bit-shift-amount data B(0). The decode circuits decode the bit-shift-amount data from the flip-flops. The flip-flops and the decode circuits are laterally laid out in a line. The flip-flops and the decode circuits are symmetrically laid out in bits, together with four flip-flops that receive respective 1-bit data to be bit-shifted (data A(3) to A(0)) and a bit shifter that bit-shifts the data A(3) to A(0) for a bit shift amount from said decode circuits, to form a bit slice structure and to be arranged within a data path. Accordingly, it is possible to achieve an effective reduction of the length of signal wiring over which bit-shift-amount data propagate. The reduction of wire load can be accomplished. The speed-up of data bit shift processing can be realized.
摘要翻译：提供了两个触发器和解码电路。而一个触发器接收1位位移量数据B（1），另一个触发器接收1位位移量数据B（0）。解码电路解码来自触发器的位移量数据。触发器和解码电路横向布置在一行中。触发器和解码电路以位为单位对称布置，以及四个触发器，其接收要进行位移的相应1位数据（数据A（3）至A（0））和位移器将数据A（3）从所述解码电路进行位移量位移到A（0），以形成位片结构并且被布置在数据路径内。因此，有可能有效地减少传播位移量数据的信号线的长度。可以实现线负载的减少。可以实现数据位移处理的加速。

6. 发明授权

US5907694A Data processing apparatus for performing a pipeline operation on a load and extension instruction 失效
标题翻译：用于在加载和扩展指令上执行流水线操作的数据处理装置
公开(公告)号：US5907694A
公开(公告)日：1999-05-25
申请号：US824984
申请日：1997-03-27
申请人： Masato Suzuki , Nobuo Higaki , Shinya Miyaji , Nobuki Tominaga , Yoshito Nishimichi
发明人： Masato Suzuki , Nobuo Higaki , Shinya Miyaji , Nobuki Tominaga , Yoshito Nishimichi
IPC分类号： G06F9/302 , G06F9/312 , G06F9/318 , G06F9/38
CPC分类号： G06F9/3001 , G06F9/30043 , G06F9/3826
摘要： The present data processing apparatus effects the pipeline operation for each of the machine cycle time with a plurality of pipeline stages processed in parallel. With respect to a load & extension instruction for instructing with the single instruction a first processing portion for reading the data shorter than the register length from RAM 19 and a second processing portion for zero-extending or the sign-extending the data into the register length, a zero-extension or a sign-extension operation in the second processing operation is executed, in a pipeline stream different from the pipeline stream where a first processing operation is executed or in a pipeline stage different from the pipeline stage where the reading from the storage portion of the first processing operation is executed.
摘要翻译：本数据处理装置利用并行处理的多个流水线级对机器周期时间的每一个进行流水线操作。关于用单指令进行指令的加载和扩展指令，用于从RAM 19读取比寄存器长度短的数据的第一处理部分和用于零扩展的第二处理部分或将数据符号扩展到寄存器长度，在与执行第一处理操作的流水线流不同的流水线流中或者与流水线级不同的流水线级执行在第二处理操作中的零扩展或符号扩展操作，执行第一处理操作的存储部分。

7. 发明授权

US4779234A First-in-first-out memory capable of simultaneous readings and writing operations 失效
标题翻译：先进先出的内存，能够同时读取和写入操作
公开(公告)号：US4779234A
公开(公告)日：1988-10-18
申请号：US866963
申请日：1986-05-27
申请人： Katsuyuki Kaneko , Masaru Uya , Yoshito Nishimichi
发明人： Katsuyuki Kaneko , Masaru Uya , Yoshito Nishimichi
IPC分类号： G11C7/00 , G06F5/10 , G06F5/12 , G11C8/16 , G11C11/41
CPC分类号： G06F5/12 , G11C8/16 , G06F2205/123
摘要： A FIFO memory using one of the ports of a RAM having two or more ports for writing and another port for reading is disclosed. Writing into the FIFO memory is done instantly, while reading from the FIFO memory is effected by holding the output of the preliminarily accessed RAM until the end of a reading operation. The output of the RAM is updated by a request from outside and according to the state of the FIFO memory, and this operation is done simultaneously with reading or writing.
摘要翻译：公开了一种FIFO存储器，其使用具有用于写入的两个或更多个端口的RAM的端口之一和用于读取的另一个端口。通过保持预先访问的RAM的输出直到读取操作结束来实现从FIFO存储器的读取来实现对FIFO存储器的写入。通过来自外部的请求和根据FIFO存储器的状态来更新RAM的输出，并且该操作与读取或写入同时进行。

8. 发明授权

US4709173A Integrated circuit having latch circuit with multiplexer selection function 失效
标题翻译：集成电路具有多路选择功能的锁存电路
公开(公告)号：US4709173A
公开(公告)日：1987-11-24
申请号：US864466
申请日：1986-05-19
申请人： Yoshito Nishimichi , Masaru Uya , Katsuyuki Kaneko
发明人： Yoshito Nishimichi , Masaru Uya , Katsuyuki Kaneko
IPC分类号： H03K3/037 , H03K3/012 , H03K3/356 , H03K17/00 , H03K19/094
CPC分类号： H03K3/356052 , H03K17/00 , H03K3/012 , H03K3/356017
摘要： An integrated circuit having a latch circuit with a selection function includes a selection circuit having a plurality of logic circuits each capable of presenting three output states depending on a selection signal supplied thereto, a latch circuit having a bistable circuit composed of first and second logic inverting circuits, and a connection system for supplying an output of the selection circuit to an input of the latch circuit. An output resistance of the second logic inverting circuit is set to be at least ten times as high as an output resistance of any one of the logic circuits which make up the selection circuit.
摘要翻译：具有具有选择功能的锁存电路的集成电路包括具有多个逻辑电路的选择电路，每个逻辑电路能够根据提供的选择信号呈现三种输出状态;锁存电路，具有由第一和第二逻辑反相电路，以及用于将选择电路的输出提供给锁存电路的输入的连接系统。第二逻辑反相电路的输出电阻被设定为构成选择电路的逻辑电路中的任何一个的输出电阻的十倍以上。

9. 发明授权

US5347232A Phase locked loop clock generator 失效
标题翻译：锁相环时钟发生器
公开(公告)号：US5347232A
公开(公告)日：1994-09-13
申请号：US061016
申请日：1993-05-14
申请人： Yoshito Nishimichi
发明人： Yoshito Nishimichi
IPC分类号： H03L7/087 , H03L7/095 , H03L7/10
CPC分类号： H03L7/087 , H03L7/095 , Y10S331/02
摘要： A phase locked loop (PLL) is disclosed, which produces a source clock signal which has a frequency twice that of a reference clock signal fed from the outside and is in synchronism with a reference clock signal. A timer counts pulses of a reference clock signal in order to measure time corresponding to the lock-in time of the PLL and delivers a count completion signal when the value of counting reaches a predetermined value. A start controller is in control of a clock buffer so that, after a count completion signal is delivered, the clock buffer starts feeding a source clock signal to a load circuit as an internal clock signal, in synchronism with a reference clock signal. A stop controller is also in control of the clock buffer so that, when a clock stop request signal becomes asserted, the clock buffer stops feeding an internal clock signal, in synchronism with a reference clock signal.
摘要翻译：公开了一种锁相环（PLL），其产生源时钟信号，该源时钟信号的频率是从外部馈送的参考时钟信号的两倍，并且与参考时钟信号同步。定时器对参考时钟信号的脉冲进行计数，以便测量对应于PLL的锁定时间的时间，并且当计数值达到预定值时递送计数完成信号。启动控制器控制时钟缓冲器，使得在递送计数完成信号之后，与参考时钟信号同步，时钟缓冲器开始将源时钟信号作为内部时钟信号馈送到负载电路。停止控制器也控制时钟缓冲器，使得当时钟停止请求信号被断言时，时钟缓冲器与参考时钟信号同步地停止馈送内部时钟信号。

10. 发明授权

US5287025A Timing control circuit 失效
标题翻译：定时控制电路
公开(公告)号：US5287025A
公开(公告)日：1994-02-15
申请号：US871983
申请日：1992-04-22
申请人： Yoshito Nishimichi
发明人： Yoshito Nishimichi
IPC分类号： G06F1/10 , H03K5/00 , H03K5/13 , H03K5/135 , H03L7/081
CPC分类号： G06F1/10 , H03K5/133 , H03K5/135 , H03L7/0814 , H03K2005/00065 , H03K2005/00071 , H03K2005/00104
摘要： A timing control circuit to be used for a phase locked loop (PLL) wherein, a plurality of delay circuit elements capable of controlling the delay connected in series are used as a signal delay circuit, delay values of all the delay circuit elements can be changed at the same time with the delay control signals of the respective delay circuit elements being commonly connected, and the delay control signal is controlled so as to select the desired delay with the combination of a selecting circuit, a bi-directional shift register circuit, a phase detecting circuit, a shift control circuit, a delay control circuit so as to realize the wide range of timing control, thereby to provide a function of adjusting the delay of a signal delay circuit for effecting a timing control operation.
摘要翻译：一种用于锁相环（PLL）的定时控制电路，其中使用能够控制串联连接的延迟的多个延迟电路元件作为信号延迟电路，可以改变所有延迟电路元件的延迟值同时各延迟电路元件的延迟控制信号共同连接，并且控制延迟控制信号，以便通过选择电路，双向移位寄存器电路，相位检测电路，移位控制电路，延迟控制电路，以实现大范围的定时控制，从而提供调整信号延迟电路的延迟以实现定时控制操作的功能。

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