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1. 发明授权

US5835505A Semiconductor integrated circuit and system incorporating the same 失效
标题翻译：半导体集成电路和系统结合在一起
公开(公告)号：US5835505A
公开(公告)日：1998-11-10
申请号：US843581
申请日：1997-04-16
申请人： Yoshito Nishimichi , Satoshi Ogura , Shinji Ozaki , Seiji Tokunoh , Akira Miyoshi , Hiroaki Yamamoto , Yoshiaki Kasuga
发明人： Yoshito Nishimichi , Satoshi Ogura , Shinji Ozaki , Seiji Tokunoh , Akira Miyoshi , Hiroaki Yamamoto , Yoshiaki Kasuga
IPC分类号： G06F11/36 , G01R31/28 , G11C29/00
CPC分类号： G06F11/3648
摘要： A semiconductor integrated circuit includes a functional block realizing at least part of a function of the semiconductor integrated circuit. The functional block includes a plurality of basic cells and a plurality of terminal cells. Each of the plurality of terminal cells has a connector for mediating a communication between another semiconductor integrated circuit and one of the plurality of basic cells.
摘要翻译：半导体集成电路包括实现半导体集成电路的功能的至少一部分的功能块。功能块包括多个基本单元和多个终端单元。多个终端单元中的每一个具有用于中介另一半导体集成电路与多个基本单元中的一个之间的通信的连接器。

2. 发明授权

US5754813A Data processor 失效
标题翻译：数据处理器
公开(公告)号：US5754813A
公开(公告)日：1998-05-19
申请号：US811663
申请日：1997-03-05
申请人： Hiroaki Yamamoto , Shinji Ozaki , Yoshito Nishimichi
发明人： Hiroaki Yamamoto , Shinji Ozaki , Yoshito Nishimichi
IPC分类号： G06F9/38 , G06F9/40
CPC分类号： G06F9/382 , G06F9/3802 , G06F9/3814 , G06F9/3869
摘要： Two instruction execution units execute different types of instructions. Two instruction selection circuits are provided. Two instruction buses are coupled to an instruction standby unit having predecoders and an instruction queue. The instruction standby unit is connected by two wait instruction buses to the input sides of the instruction selection circuits. An instruction fetch control circuit detects an instruction that has not been executed by any of the instruction execution units. Such an unexecuted instruction waits in the instruction queue, thereafter being applied, together with its predecode result, to each instruction selection circuit to be selected at the next selection time. As a result of such arrangement, fast execution of different types of instructions in parallel is accomplished.
摘要翻译：两个指令执行单元执行不同类型的指令。提供两个指令选择电路。两个指令总线耦合到具有预解码器和指令队列的指令备用单元。指令备用单元通过两条等待指令总线连接到指令选择电路的输入侧。指令获取控制电路检测任何指令执行单元尚未执行的指令。这种未执行的指令在指令队列中等待，然后与其预解码结果一起应用于在下一个选择时间被选择的每个指令选择电路。作为这种安排的结果，可以实现并行执行不同类型指令的快速执行。

3. 发明授权

US5829021A System for controlling operating timing of a cache memory 失效
标题翻译：用于控制高速缓冲存储器的操作定时的系统
公开(公告)号：US5829021A
公开(公告)日：1998-10-27
申请号：US470933
申请日：1995-06-06
申请人： Hiroaki Yamamoto , Shinji Ozaki , Yoshito Nishimichi
发明人： Hiroaki Yamamoto , Shinji Ozaki , Yoshito Nishimichi
IPC分类号： G06F9/38 , G06F12/00
CPC分类号： G06F9/382 , G06F9/3802 , G06F9/3814 , G06F9/3869
摘要： Two instruction execution units execute different types of instructions. Two instruction selection circuits are provided. Two instruction buses are coupled to an instruction standby unit having predecoders and an instruction queue. The instruction standby unit is connected by two wait instruction buses to the input sides of the instruction selection circuits. An instruction fetch control circuit detects an instruction that has not been executed by any of the instruction execution units. Such an unexecuted instruction waits in the instruction queue, thereafter being applied, together with its predecode result, to each instruction selection circuit to be selected at the next selection time. As a result of such arrangement, fast execution of different types of instructions in parallel is accomplished.
摘要翻译：两个指令执行单元执行不同类型的指令。提供两个指令选择电路。两个指令总线耦合到具有预解码器和指令队列的指令备用单元。指令备用单元通过两条等待指令总线连接到指令选择电路的输入侧。指令获取控制电路检测任何指令执行单元尚未执行的指令。这种未执行的指令在指令队列中等待，然后与其预解码结果一起应用于在下一个选择时间被选择的每个指令选择电路。作为这种安排的结果，可以实现并行执行不同类型指令的快速执行。

4. 发明授权

US06480875B1 Adder circuit and associated layout structure 失效
标题翻译：加法器电路和相关布局结构
公开(公告)号：US06480875B1
公开(公告)日：2002-11-12
申请号：US08957159
申请日：1997-10-24
申请人： Akira Miyoshi , Hiroaki Yamamoto , Yoshito Nishimichi
发明人： Akira Miyoshi , Hiroaki Yamamoto , Yoshito Nishimichi
IPC分类号： G06F750
CPC分类号： G06F7/508 , H01L27/0207 , H01L27/092
摘要： In an adder circuit, a block carry generation logic over three consecutive digits is produced from the following equations. G0=g2+p2·g1+p2·p1·g0 /g0=/p2+/g2·/p1+/g2·/g1·/g0 In other words, the block carry generation logic /G0 is produced by a single PMOS transistor, a series circuit formed of two PMOS transistors connected in series, and a series circuit formed of three PMOS transistors connected in series. The block carry generation logic G0 is produced by a single NMOS transistor, a series circuit formed of two NMOS transistors connected in series, and a series circuit formed of three NMOS transistors connected in series. Block carry generation logics can be formed in such a way as to achieve not only a reduction of the layout area but also a higher operation rate.
摘要翻译：在加法器电路中，从以下等式产生三位连续位数的块载入生成逻辑。换句话说，块载入生成逻辑/ G0由单个PMOS晶体管产生，串联电路由两个PMOS晶体管形成，串联电路以及串联连接的3个PMOS晶体管构成的串联电路。块载入生成逻辑G0由单个NMOS晶体管，串联连接的两个NMOS晶体管构成的串联电路和由串联连接的三个NMOS晶体管构成的串联电路产生。块携带生成逻辑可以形成为不仅实现布局区域的减少，而且实现更高的操作速率。

5. 发明授权

US5941937A Layout structure for barrel shifter with decode circuit 失效
标题翻译：具有解码电路的桶形移位器的布局结构
公开(公告)号：US5941937A
公开(公告)日：1999-08-24
申请号：US959374
申请日：1997-10-28
申请人： Hiroaki Yamamoto , Yoshito Nishimichi
发明人： Hiroaki Yamamoto , Yoshito Nishimichi
IPC分类号： G06F5/01
CPC分类号： G06F5/015
摘要： Two flip-flops and decode circuits are provided. Whereas the one flip-flop receives 1-bit bit-shift-amount data B(1), the other flip-flop receives 1-bit bit-shift-amount data B(0). The decode circuits decode the bit-shift-amount data from the flip-flops. The flip-flops and the decode circuits are laterally laid out in a line. The flip-flops and the decode circuits are symmetrically laid out in bits, together with four flip-flops that receive respective 1-bit data to be bit-shifted (data A(3) to A(0)) and a bit shifter that bit-shifts the data A(3) to A(0) for a bit shift amount from said decode circuits, to form a bit slice structure and to be arranged within a data path. Accordingly, it is possible to achieve an effective reduction of the length of signal wiring over which bit-shift-amount data propagate. The reduction of wire load can be accomplished. The speed-up of data bit shift processing can be realized.
摘要翻译：提供了两个触发器和解码电路。而一个触发器接收1位位移量数据B（1），另一个触发器接收1位位移量数据B（0）。解码电路解码来自触发器的位移量数据。触发器和解码电路横向布置在一行中。触发器和解码电路以位为单位对称布置，以及四个触发器，其接收要进行位移的相应1位数据（数据A（3）至A（0））和位移器将数据A（3）从所述解码电路进行位移量位移到A（0），以形成位片结构并且被布置在数据路径内。因此，有可能有效地减少传播位移量数据的信号线的长度。可以实现线负载的减少。可以实现数据位移处理的加速。

6. 发明授权

US09456738B2 Endoscopic diagnosis system 有权
标题翻译：内窥镜诊断系统
公开(公告)号：US09456738B2
公开(公告)日：2016-10-04
申请号：US13283407
申请日：2011-10-27
申请人： Hiroaki Yamamoto
发明人： Hiroaki Yamamoto
IPC分类号： A61B6/00 , A61B1/04 , A61B1/06 , A61B5/1455 , A61B1/07
CPC分类号： A61B1/043 , A61B1/063 , A61B1/0638 , A61B1/0646 , A61B1/0653 , A61B1/07 , A61B5/14551
摘要： An endoscopic diagnosis system includes a first narrowband light source for emitting first narrowband light having a given wavelength range, a second narrowband light source for emitting second narrowband light having a wavelength range different from that of the first narrowband light, a first image sensor for receiving reflected light of the first narrowband light illuminating a subject from the subject to acquire a narrowband light image in a narrowband light observation mode, a second image sensor for receiving first autofluorescence emitted from the subject as the first narrowband light illuminates the subject to acquire a first autofluorescence image in a first autofluorescence observation mode and receiving second autofluorescence emitted from the subject as the second narrowband light illuminates the subject to acquire a second autofluorescence image in a second autofluorescence observation mode.
摘要翻译：内窥镜诊断系统包括用于发射具有给定波长范围的第一窄带光的第一窄带光源，用于发射具有与第一窄带光不同的波长范围的第二窄带光的第二窄带光源，用于接收的第一图像传感器第一窄带光从被摄体照射被摄体的反射光，以获取窄带光观察模式中的窄带光图像;第二图像传感器，用于当第一窄带光照射对象时，从被检体发射的第一自发荧光发光，以获得第一第一自发荧光观察模式中的自发荧光图像，并且当第二窄带光照射对象以在第二自发荧光观察模式中获取第二自发荧光图像时，接收从对象发射的第二自发荧光。

7. 发明授权

US08915844B2 Endoscope diagnostic apparatus 有权
标题翻译：内窥镜诊断仪
公开(公告)号：US08915844B2
公开(公告)日：2014-12-23
申请号：US13596867
申请日：2012-08-28
申请人： Hiroaki Yamamoto
发明人： Hiroaki Yamamoto
IPC分类号： A61B1/06 , A61B1/04 , A61B1/05 , A61B1/00
CPC分类号： A61B1/043 , A61B1/00006 , A61B1/00009 , A61B1/05 , A61B1/063 , A61B1/0638 , A61B1/0653
摘要： The endoscope diagnostic apparatus includes a light source emitting white light and two or more kinds of excited light with different center wavelengths for emitting two or more kinds of self-fluorescence from a self-fluorescent material, an imaging unit which receives reflected light of white light to image a normal light image, and receives self-fluorescence emitted from the self-fluorescent material to image self-fluorescent images, and a light source control unit which has compensation coefficients for preventing emission intensity from being lowered depending on the volume of blood when the two or more kinds of excited light are absorbed by blood, and compensates the ratios of emission intensity of the two or more kinds of excited light using the calculated compensation coefficients so as to exclude the influence of absorption of light by blood in each of the two or more kinds of excited light.
摘要翻译：内窥镜诊断装置包括：发出白光的光源和具有不同中心波长的两种以上的激发光，用于从自发荧光材料发射两种或更多种自发荧光;成像单元，其接收白光的反射光对正常的光图像进行成像，并且接收从自身荧光材料发射的自体荧光以图像自发荧光图像;以及光源控制单元，其具有用于防止发射强度根据血液体积而降低的补偿系数两种或更多种激发光被血液吸收，并且使用所计算的补偿系数来补偿两种或更多种激发光的发射强度的比率，以便排除在每个激光的每一个中由血液吸收光的影响两种或多种激发光。

8. 发明授权

US08836983B2 Information processing device, image forming apparatus, and non-transitory computer readable medium 有权
标题翻译：信息处理装置，图像形成装置和非暂时性计算机可读介质
公开(公告)号：US08836983B2
公开(公告)日：2014-09-16
申请号：US13558766
申请日：2012-07-26
申请人： Hiroaki Yamamoto , Jyunya Yamada , Tadashi Hata , Toshiharu Hayashida
发明人： Hiroaki Yamamoto , Jyunya Yamada , Tadashi Hata , Toshiharu Hayashida
IPC分类号： G06F3/12
CPC分类号： G06F9/4401
摘要： An information processing device includes an execution unit that executes a control program for causing a functional unit to realize a predetermined function, a memory that stores the control program, a state variable indicating a state of the functional unit, and activation history of either initial activation or second and following activation, in a nonvolatile memory, and a communication unit that causes the execution unit to communicate with the functional unit, wherein the execution unit includes a first procedure where the control program is stored in the memory and the control program is read and is executed, and a second procedure where the control program pre-stored in the memory is read and is executed, refers to the activation history when activation is performed, executes the first procedure in a case of the initial activation, and executes the second procedure in a case of the second and following activation.
摘要翻译：信息处理装置包括：执行单元，执行用于使功能单元实现预定功能的控制程序，存储控制程序的存储器，指示功能单元的状态的状态变量，以及初始激活的激活历史或第二次和之后的激活，以及使执行单元与功能单元通信的通信单元，其中执行单元包括第一过程，其中控制程序存储在存储器中并且读取控制程序并且执行预先存储在存储器中的控制程序被读取并被执行的第二过程，参考执行激活时的激活历史，在初始激活的情况下执行第一过程，并且执行第二过程在第二次和之后激活的情况下的程序。

9. 发明申请

US20120324182A1 STORAGE DEVICE 审中-公开
标题翻译：储存设备
公开(公告)号：US20120324182A1
公开(公告)日：2012-12-20
申请号：US13582185
申请日：2010-12-10
申请人： Hiroaki Yamamoto , Takatoshi Sato , Masanori Tsuda
发明人： Hiroaki Yamamoto , Takatoshi Sato , Masanori Tsuda
IPC分类号： G06F12/16
CPC分类号： G06F3/0641 , G06F3/0608 , G06F3/0689
摘要： A storage device 110 includes: a data writing part 111 configured to store data to be written into a storage device 120 and also, when storing other data of the same content as the data already stored in the storage device into the storage device, refer to the data already stored in the storage device as the other data; and a data separating part 112 configured to separate data to be written into a user data portion and a management data portion that are classified in accordance with a previously set criterion. The data writing part 111 is configured to store the user data portion into a user data file 121, store the management data portion into a management data file 122, and store the user data portion and the management data portion separated by the data separating part 112 into the storage device 120.
摘要翻译：存储装置110包括：数据写入部111，被配置为存储要写入存储装置120的数据，并且当将与存储在存储装置中的数据相同的内容的其他数据存储到存储装置中时，参考已经存储在存储设备中的数据作为其他数据; 以及数据分离部分112，被配置为将要写入的用户数据部分的数据和根据先前设定的标准分类的管理数据部分分离。数据写入部分111被配置为将用户数据部分存储到用户数据文件121中，将管理数据部分存储到管理数据文件122中，并存储由数据分离部分112分隔的用户数据部分和管理数据部分进入存储装置120。

10. 发明授权

US08061083B2 Door noise suppressing structure in open/close body drive apparatus 有权
标题翻译：开/关体驱动装置中的门噪声抑制结构
公开(公告)号：US08061083B2
公开(公告)日：2011-11-22
申请号：US12360469
申请日：2009-01-27
申请人： Nakatsune Shirai , Hidenori Ishihara , Tomoki Yamashita , Hiroaki Yamamoto , Katsumi Endo
发明人： Nakatsune Shirai , Hidenori Ishihara , Tomoki Yamashita , Hiroaki Yamamoto , Katsumi Endo
IPC分类号： E05F11/38
CPC分类号： E05F15/697 , E05F11/445 , E05Y2800/422 , E05Y2900/55
摘要： A drive apparatus for opening and closing a window glass provided in a door having an inner panel is disclosed. The drive apparatus includes a motor provided in the door and a regulator that receives drive force from the motor and selectively open and close the window glass. The door noise includes motor operating noise and vibration transmission noise that is generated when vibration of the motor is transmitted to the inner panel via the regulator. The motor is configured such that a first-order frequency component in vibration of the motor is greater than any other nth component (n is an integer greater than or equal to two), so that the first-order frequency component in the door noise is greater than any other nth frequency component (n is an integer greater than or equal to two).
摘要翻译：公开了一种用于打开和关闭设置在具有内板的门中的窗玻璃的驱动装置。驱动装置包括设置在门中的马达和调节器，其接收来自马达的驱动力并选择性地打开和关闭窗玻璃。门噪声包括电动机运行噪声和当电动机的振动经由调节器传递到内板时产生的振动传播噪声。电动机被构造成使得电动机的振动中的一阶频率分量大于任何其他第n个分量（n是大于或等于2的整数），使得门噪声中的一阶频率分量为大于任何其他第n个频率分量（n是大于或等于2的整数）。

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