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1. 发明授权

US07570502B2 Inverter apparatus comprising switching elements 失效
标题翻译：包括开关元件的逆变器装置
公开(公告)号：US07570502B2
公开(公告)日：2009-08-04
申请号：US10565389
申请日：2004-07-23
申请人： Yoshitaka Sugawara , Katsunori Asano , Mitsuru Matsukawa , Yoshifumi Minowa , Toshihiko Shikata
发明人： Yoshitaka Sugawara , Katsunori Asano , Mitsuru Matsukawa , Yoshifumi Minowa , Toshihiko Shikata
IPC分类号： H02M7/5387
CPC分类号： H02M7/521 , H02M1/32 , H02M1/38 , H02M2001/0012
摘要： A problem to be solved by the present invention is to eliminate variation in potential in a turn-off time period of each GTO element, and to stabilize a gate drawing current by surely performing the turn-off of the GTO element. In an inverter apparatus having a three-phase inverter configured to include paired GTO elements an inverter control portion has a simultaneous switching prevention function of delaying a turn-on operation of each of the GTO elements which correspond to phases other than a phase corresponding to an optional one of the GTO elements and also correspond to an electrode opposite to an electrode corresponding to the optional one of the GTO elements by a predetermined time in a case where a turn-on command signal for turning on each of the GTO elements is generated within a predetermined time period since the turn-off of the optional one of the GTO elements.
摘要翻译：本发明要解决的问题是消除每个GTO元件的关断时间段中的电位变化，并且通过可靠地执行GTO元件的关断来稳定栅极引出电流。在具有配置为包括成对的GTO元件的三相逆变器的逆变器装置中，逆变器控制部具有同时切换防止功能，其延迟对应于除了相应于相同的相位之外的相位的每个GTO元件的接通操作在GTO元件中可选的一个，并且在用于接通每个GTO元件的接通命令信号的情况下，也对应于与对应于GTO元件中的任选一个GTO元件的电极相对预定时间的电极自从关闭任选的一个GTO元件以来的预定时间段。

2. 发明授权

US07960738B2 Silicon carbide semiconductor device and manufacturing method therefor 失效
公开(公告)号：US07960738B2
公开(公告)日：2011-06-14
申请号：US12801681
申请日：2010-06-21
申请人： Koji Nakayama , Yoshitaka Sugawara , Katsunori Asano , Hidekazu Tsuchida , Isaho Kamata , Toshiyuki Miyanagi , Tomonori Nakamura
发明人： Koji Nakayama , Yoshitaka Sugawara , Katsunori Asano , Hidekazu Tsuchida , Isaho Kamata , Toshiyuki Miyanagi , Tomonori Nakamura
IPC分类号： H01L29/15 , H01L31/0312
CPC分类号： H01L29/868 , H01L29/045 , H01L29/0619 , H01L29/1608 , H01L29/66068 , H01L29/73 , H01L29/7397
摘要： With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle θ of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 μm/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.

3. 发明申请

US20100258817A1 Silicon carbide semiconductor device and manufacturing method therefor 失效
公开(公告)号：US20100258817A1
公开(公告)日：2010-10-14
申请号：US12801681
申请日：2010-06-21
申请人： Koji Nakayama , Yoshitaka Sugawara , Katsunori Asano , Hidekazu Tsuchida , Isaho Kamata , Toshiyuki Miyanagi , Tomonori Nakamura
发明人： Koji Nakayama , Yoshitaka Sugawara , Katsunori Asano , Hidekazu Tsuchida , Isaho Kamata , Toshiyuki Miyanagi , Tomonori Nakamura
IPC分类号： H01L29/24
CPC分类号： H01L29/868 , H01L29/045 , H01L29/0619 , H01L29/1608 , H01L29/66068 , H01L29/73 , H01L29/7397
摘要： With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle θ of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 μm/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.

4. 发明授权

US07960737B2 Silicon carbide semiconductor device and manufacturing method therefor 失效
公开(公告)号：US07960737B2
公开(公告)日：2011-06-14
申请号：US12801679
申请日：2010-06-21
申请人： Koji Nakayama , Yoshitaka Sugawara , Katsunori Asano , Hidekazu Tsuchida , Isaho Kamata , Toshiyuki Miyanagi , Tomonori Nakamura
发明人： Koji Nakayama , Yoshitaka Sugawara , Katsunori Asano , Hidekazu Tsuchida , Isaho Kamata , Toshiyuki Miyanagi , Tomonori Nakamura
IPC分类号： H01L29/15 , H01L31/0312
CPC分类号： H01L29/868 , H01L29/045 , H01L29/0619 , H01L29/1608 , H01L29/66068 , H01L29/73 , H01L29/7397
摘要： With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle θ of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 μm/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.

5. 发明授权

US07960257B2 Silicon carbide semiconductor device and manufacturing method therefor 失效
标题翻译：碳化硅半导体器件及其制造方法
公开(公告)号：US07960257B2
公开(公告)日：2011-06-14
申请号：US12801680
申请日：2010-06-21
申请人： Koji Nakayama , Yoshitaka Sugawara , Katsunori Asano , Hidekazu Tsuchida , Isaho Kamata , Toshiyuki Miyanagi , Tomonori Nakamura
发明人： Koji Nakayama , Yoshitaka Sugawara , Katsunori Asano , Hidekazu Tsuchida , Isaho Kamata , Toshiyuki Miyanagi , Tomonori Nakamura
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L29/868 , H01L29/045 , H01L29/0619 , H01L29/1608 , H01L29/66068 , H01L29/73 , H01L29/7397
摘要： With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle θ of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 μm/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.
摘要翻译：为了防止由于使用碳化硅半导体的双极性半导体器件随时间的变化引起的正向电压的增加，缓冲层，漂移层和其他p型和n型半导体层形成在生长表面，其由具有偏角角度的硅碳化物半导体的晶体的表面给出; （000-1）碳表面8度，以每小时薄膜增加率为10μm/小时的膜生长速率，比常规对应物高3倍以上。硅烷和丙烷材料气体和掺杂气体的流速大大增加，以提高膜生长速率。

6. 发明授权

US06342709B1 Insulated gate semiconductor device 失效
标题翻译：绝缘栅半导体器件
公开(公告)号：US06342709B1
公开(公告)日：2002-01-29
申请号：US09117997
申请日：1998-08-11
申请人： Yoshitaka Sugawara , Katsunori Asano
发明人： Yoshitaka Sugawara , Katsunori Asano
IPC分类号： H01L3300
CPC分类号： H01L29/7811 , H01L29/0619 , H01L29/1095 , H01L29/1608 , H01L29/42368 , H01L29/7397 , H01L29/7809 , H01L29/7813
摘要： In a semiconductor device having a trench type insulated gate structure, in the case where a drift layer 2 of an n− conduction type has a high carrier density, when a high voltage is applied between a drain and a source in such a manner that a channel is not formed, the electric field strength of an insulator layer 9 below the trench type insulated gate is increased, thus causing breakdown. The withstand voltage of the semiconductor device is limited by the breakdown of the insulator layer 9, and it is difficult to realize high withstand voltage. In the characteristic of the present invention, a field relaxation semiconductor region 1 of a conduction type opposite to the conduction type of the drift layer 2 is formed within the drift layer 2 below the insulator layer 9 in the trench of the trench type insulated gate semiconductor device. Also, the thickness of a bottom portion of the insulator layer 9 provided in the trench of the trench type insulated gate semiconductor device is made significantly greater than the thickness of a lateral portion thereof.
摘要翻译：在具有沟槽型绝缘栅极结构的半导体器件中，在n型导电型漂移层2具有高载流子密度的情况下，当在漏极和源极之间施加高电压时，通道不形成，沟槽型绝缘栅下方的绝缘体层9的电场强度增加，从而导致击穿。半导体器件的耐电压受绝缘体层9击穿的限制，难以实现高耐压。在本发明的特征中，与导通相反的导电类型的场弛豫半导体区域1 在沟槽型绝缘栅半导体器件的沟槽中的绝缘体层9下方的漂移层2内形成漂移层2的类型。此外，设置在沟槽型绝缘栅极半导体器件的沟槽中的绝缘体层9的底部的厚度显着大于其侧面部分的厚度。

7. 发明申请

US20100258816A1 Silicon carbide semiconductor device and manufacturing method therefor 失效
公开(公告)号：US20100258816A1
公开(公告)日：2010-10-14
申请号：US12801679
申请日：2010-06-21
申请人： Joji Nakayama , Yoshitaka Sugawara , Katsunori Asano , Hidekazu Tsuchida , Isaho Kamata , Toshiyuki Miyanagi , Tomonori Nakamura
发明人： Joji Nakayama , Yoshitaka Sugawara , Katsunori Asano , Hidekazu Tsuchida , Isaho Kamata , Toshiyuki Miyanagi , Tomonori Nakamura
IPC分类号： H01L29/24
CPC分类号： H01L29/868 , H01L29/045 , H01L29/0619 , H01L29/1608 , H01L29/66068 , H01L29/73 , H01L29/7397
摘要： With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle θ of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 μm/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.

8. 发明申请

US20100182813A1 PN DIODE, ELECTRIC CIRCUIT DEVICE AND POWER CONVERSION DEVICE 审中-公开
标题翻译： PN二极管，电路设备和电源转换器件
公开(公告)号：US20100182813A1
公开(公告)日：2010-07-22
申请号：US12665482
申请日：2008-06-17
申请人： Katsunori Asano , Yoshitaka Sugawara , Atsushi Tanaka
发明人： Katsunori Asano , Yoshitaka Sugawara , Atsushi Tanaka
IPC分类号： H02M7/06 , H01L29/20 , H01L29/24 , H01L29/16 , H01L21/26 , H02M7/12
CPC分类号： H01L27/0814 , H01L21/8213 , H01L29/1602 , H01L29/1608 , H01L29/2003 , H01L29/32 , H01L29/861 , H02M1/34 , H02M7/003 , Y02B70/1483
摘要： In a SiC pn diode, the lifetime is controlled by electron beam irradiation of about 3×1013 cm−2 or more. As a result of the life time control, as shown by a current-voltage characteristic (K10) in FIG. 1, the current started to flow at about 32 V and the on-voltage at an applied current of 100 A was 50 V in the SiC pn diode. In this case, the SiC pn diode has a resistance of 0.5Ω when the SiC pn diode is turned on. The conducting region of the SiC pn diode is 0.4 cm2, and is reduced to 0.2 Ωcm2 by increasing the on-resistance by the lifetime control. Therefore, for instance, in an electric circuit device using a diode and a resistor connected in series in prior arts, the resistor can be eliminated.
摘要翻译：在SiC pn二极管中，寿命由大约3×1013 cm -2以上的电子束照射控制。作为寿命控制的结果，如图1中的电流 - 电压特性（K10）所示。如图1所示，电流在大约32V开始流动，并且在SiC pn二极管中在100A的施加电流下的导通电压为50V。在这种情况下，SiC pn二极管的电阻为0.5＆OHgr; 当SiC pn二极管导通时。 SiC pn二极管的导电区域为0.4平方厘米，通过寿命控制增加导通电阻，将其减小到0.2和OHgr。因此，例如，在现有技术中使用二极管和电阻串联连接的电路装置中，可以消除电阻。

9. 发明申请

US20070262472A1 High Withstand Voltage Semiconductor Device Covered with Resin and Manufacturing Method Therefor 审中-公开
标题翻译：树脂覆盖的高耐压半导体器件及其制造方法
公开(公告)号：US20070262472A1
公开(公告)日：2007-11-15
申请号：US11664586
申请日：2005-10-05
申请人： Shinichi Okada , Yoshitaka Sugawara , Katsunori Asano , Daisuke Takayama , Yoshikazu Shoji , Tadashi Janado , Takashi Sueyoshi , Ken-Ichiro Hiwatari
发明人： Shinichi Okada , Yoshitaka Sugawara , Katsunori Asano , Daisuke Takayama , Yoshikazu Shoji , Tadashi Janado , Takashi Sueyoshi , Ken-Ichiro Hiwatari
IPC分类号： H01L23/29 , H01L21/56
CPC分类号： H01L23/24 , H01L23/296 , H01L23/3121 , H01L24/48 , H01L2224/48137 , H01L2224/4823 , H01L2224/8592 , H01L2924/00014 , H01L2924/01004 , H01L2924/01078 , H01L2924/10272 , H01L2924/1305 , H01L2924/13055 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A high withstand voltage semiconductor chip mounted on a package or a board is covered with a sealing resin, and the resin is cured while a high voltage is applied between at least one of electrode terminals connected from a chip electrode or the chip via wiring of wires or the like and another electrode that necessitates a dielectric withstand voltage between the electrode and the electrode terminal during the curing. The sealing resin is provided by a synthetic high molecular compound structured in a manner that an organic silicon polymer C is constituted by alternately linearly linking an organic silicon polymer A having a crosslinking structure of siloxane with an organic silicon polymer B having a linear link structure of siloxane (Si—O—Si bond) by siloxane bond and the polymers are three-dimensionally linked together by covalent bond. With this arrangement, a dielectric withstand voltage capability, which is stable by suppression of an increase in the leakage current even when a high reverse voltage is applied and agrees with the designed value, can be obtained in a high withstand voltage semiconductor chip that is mounted on a board or a package and sealed with the resin.
摘要翻译：安装在封装或板上的高耐压半导体芯片被密封树脂覆盖，并且在从芯片电极连接的至少一个电极端子或芯片之间施加高电压而使树脂固化，或类似物以及在固化期间必须在电极和电极端子之间具有介电耐受电压的另一电极。密封树脂由合成的高分子化合物提供，所述合成高分子化合物以有机硅聚合物C通过将具有硅氧烷的交联结构的有机硅聚合物A与具有硅氧烷的交联结构的有机硅聚合物A与具有直链结构通过硅氧烷键的硅氧烷（Si-O-Si键），并且聚合物通过共价键三维连接在一起。通过这种布置，即使在施加高的反向电压并且与设计值一致的情况下也可以通过抑制漏电流的增加而稳定的介电耐受电压能力可以在安装的高耐压半导体芯片中获得在纸板或包装上，并用树脂密封。

10. 发明申请

US20070120145A1 Gate turn-off thyristor 审中-公开
标题翻译：门极关断晶闸管
公开(公告)号：US20070120145A1
公开(公告)日：2007-05-31
申请号：US10552268
申请日：2004-04-07
申请人： Katsunori Asano , Yoshitaka Sugawara
发明人： Katsunori Asano , Yoshitaka Sugawara
IPC分类号： H01L31/111
CPC分类号： H01L29/1016 , H01L29/0615 , H01L29/0834 , H01L29/744
摘要： A mesa-type wide-gap semiconductor gate turn-off thyristor has a low gate withstand voltage and a large leakage current. Since the ionization rate of P-type impurities greatly increases at high temperatures when compared with that at room temperature, the hole implantation amount increases and the minority carrier lifetime becomes longer. Consequently, the maximum controllable current is significantly lowered when compared with that at room temperature. To solve these problems, a p-type base layer is formed on an n-type SiC cathode emitter layer which has a cathode electrode on one surface, and a thin n-type base layer is formed on the p-type base layer. A mesa-shaped p-type anode emitter layer is formed in the central region of the n-type base layer. An n-type gate contact region is formed sufficiently apart from the junction between the p-type anode emitter layer and the n-type base layer, and an n-type low-resistance gate region is so formed in the n-type base layer that it surrounds the anode emitter layer.
摘要翻译：台式宽间隙半导体栅极截止晶闸管具有低栅极耐受电压和较大的漏电流。由于与高温下相比，P型杂质的电离率大大增加，所以空穴注入量增加，少数载流子寿命变长。因此，与室温相比，最大可控电流显着降低。为了解决这些问题，在单面表面具有阴极的n型SiC阴极发射极层上形成p型基极层，在p型基极层上形成薄的n型基极层。在n型基极层的中心区域形成台状p型阳极发射极层。与p型阳极发射极层和n型基极层之间的接合部充分地形成n型栅极接触区域，在n型基极层上形成n型低电阻栅极区域它围绕阳极发射极层。

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