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    • 3. 发明授权
    • Test assistant system for logical design process
    • 用于逻辑设计过程的测试助理系统
    • US5282146A
    • 1994-01-25
    • US694136
    • 1991-05-01
    • Masami AiharaMasatoshi SekineTsutomu TakeiHiroaki NishiKazuyoshi KohnoTakeshi KitaharaAtsushi Masuda
    • Masami AiharaMasatoshi SekineTsutomu TakeiHiroaki NishiKazuyoshi KohnoTakeshi KitaharaAtsushi Masuda
    • G06F11/25G01R31/3183G06F17/50G06F15/60
    • G01R31/318357G01R31/318307G06F17/5022
    • Disclosed is a test assistant system for a logical design process comprising a description storage data base for storing statements expressing logical functions of circuit components to be tested, a compiler for compiling the statements to output object data, a data base for storing the object data, a test pattern generator for generating test patterns by using the object data stored in the data base, a test pattern data base for storing the test patterns, each having a level number, a simulator for executing a simulation for the logical function by using the test patterns stored in the test pattern data base, and a display for displaying the object data, the test patterns, the information used in the simulation, and relationships among them. The data base comprises a region for storing a statement correspondence table expressing statements as descriptions of the logical functions of the circuit components, a region for storing a circuit component table expressing a circuit component corresponding to the function described in the statement, a region for storing a dependent relationship table expressing the dependent relationship between the statements, and a correspondence relationship table expressing the correspondence relationship between the statement correspondence table and the circuit component table.
    • 公开了一种用于逻辑设计过程的测试辅助系统,包括用于存储表示要测试的电路组件的逻辑功能的语句的描述存储数据库,用于编译语句以输出对象数据的编译器,用于存储对象数据的数据库, 用于通过使用存储在数据库中的对象数据来生成测试模式的测试模式发生器,用于存储测试模式的测试模式数据库,每个具有级别号码,用于通过使用测试执行用于逻辑功能的模拟的模拟器 存储在测试模式数据库中的模式,以及用于显示对象数据,测试模式,模拟中使用的信息以及它们之间的关系的显示。 数据库包括用于存储表示语句的语句对应表的区域,作为对电路组件的逻辑功能的描述的区域,用于存储表示对应于语句中描述的功能的电路组件的电路组件表的区域,用于存储 表示语句之间的依赖关系的依赖关系表和表示语句对应表与电路分量表之间的对应关系的对应关系表。
    • 4. 发明授权
    • High-level synthesis method including processing for optimizing arithmetic sequence of an operation string
    • 包括用于优化操作串的算术序列的处理的高级合成方法
    • US06237125B1
    • 2001-05-22
    • US08986571
    • 1997-12-05
    • Atsushi MasudaYoshinori Shigeta
    • Atsushi MasudaYoshinori Shigeta
    • G06F1750
    • G06F17/5045
    • A dependent relation of operations is extracted from an operation string expressing an operation specification, and thus the dependent relation of operations is created. Connecting relations between arithmetic units constituting an initial circuit construction of a logic circuit are extracted, and thus the connecting relations of the arithmetic units and the corresponding dependent relation of operations are created. Basic conversion rules are applied to the dependent relation of operations, new conversion rules are prepared, and thus conversion rules are created. The conversion rules are repeatedly applied to the dependent relation of operations for optimization, and optimized dependent relation of operations is created. An optimized operation string is prepared from the optimized dependent relation of operations, and an optimized operation string is obtained.
    • 从表示操作规范的操作串中提取操作的依赖关系,从而创建操作的依赖关系。 提取构成逻辑电路的初始电路结构的算术单元之间的连接关系,从而创建运算单元的连接关系和对应的依赖关系。 基本转换规则适用于操作的依赖关系,准备新的转换规则,从而创建转换规则。 将转换规则重复应用于优化操作的依赖关系,并创建优化的操作依赖关系。 根据优化的操作依赖关系准备优化的操作串,并获得优化的操作字符串。
    • 5. 发明授权
    • Apparatus and method for high-level synthesis of a logic circuit
    • 用于逻辑电路的高级合成的装置和方法
    • US5706205A
    • 1998-01-06
    • US534065
    • 1995-09-26
    • Atsushi MasudaMasatoshi SekineJeffery P. Hansen
    • Atsushi MasudaMasatoshi SekineJeffery P. Hansen
    • G06F17/50
    • G06F17/5045
    • A high-level synthesis apparatus synthesizes a large-scale logic circuit. The apparatus has a unit for generating a control description graph according to a behavioral description graph written in a behavioral description language; a unit for sorting the control description graph according to control conditions and extracting single flows including partial graphs or closed loops from the sorted control description graph; a unit for providing an initial circuit; a unit for dividing the single flows into execution steps; a unit for allocating hardware parts of the initial circuit to the execution steps; and a unit for converting each of the single flows into a finite state machine and combining the finite state machines into one. This apparatus optimizes each single flow and adds parts to or modifies the initial circuit, to synthesize a large-scale circuit.
    • 高级合成装置合成大规模逻辑电路。 该装置具有用于根据以行为描述语言编写的行为描述图生成控制描述图的单元; 用于根据控制条件对控制描述图进行排序并从排序的控制描述图中提取包括局部图或闭环的单个流; 用于提供初始电路的单元; 将单个流分为执行步骤的单元; 用于将所述初始电路的硬件部分分配给所述执行步骤的单元; 以及用于将每个单个流转换成有限状态机并将有限状态机组合为一个的单元。 该装置优化每个单个流,并将部件添加到或修改初始电路,以合成大规模电路。
    • 9. 发明授权
    • High-level synthesis apparatus, high-level synthesis system and high-level synthesis method
    • 高级合成装置,高级合成系统和高级合成方法
    • US07913204B2
    • 2011-03-22
    • US12252643
    • 2008-10-16
    • Atsushi Masuda
    • Atsushi Masuda
    • G06F17/50
    • G06F17/5045G06F17/5022
    • A high-level synthesis apparatus for automatically generating a register transfer level (RTL) logic circuit from a behavioral description has a scheduling unit configured to perform data flow analysis and scheduling to generate a data flow graph showing an operation cycle of an operation from the behavioral description, a scheduling result inputting/outputting unit configured to extract a point to be allocated to a register from the data flow graph and output register information indicating the point, the scheduling result inputting/outputting unit being provided with dynamic analysis data that includes at least one of the number of times that data at the point has been substituted and the number of times that a value stored at the point has changed by a predetermined simulation, an allocating unit configured to consult dynamic analysis data and allocate circuit elements to the behavioral description, and an RTL description generating unit configured to generate the logic circuit based on the allocation of circuit elements by the allocating unit.
    • 用于根据行为描述自动生成寄存器传送电平(RTL)逻辑电路的高级合成装置具有调度单元,其被配置为执行数据流分析和调度以生成表示从行为的操作的操作周期的数据流图 描述,调度结果输入/输出单元,被配置为从数据流图中提取要分配给寄存器的点,并输出指示该点的寄存器信息,调度结果输入/输出单元提供动态分析数据,该动态分析数据至少包括 在该点的数据被替代的次数和在该点存储的值的次数已经通过预定的模拟而改变的次数之一,配置单元被配置为咨询动态分析数据并将电路元件分配给行为描述 以及被配置为基于逻辑电路生成的RTL描述生成单元 关于由分配单元分配电路元件。