专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5282146A Test assistant system for logical design process 失效
标题翻译：用于逻辑设计过程的测试助理系统
公开(公告)号：US5282146A
公开(公告)日：1994-01-25
申请号：US694136
申请日：1991-05-01
申请人： Masami Aihara , Masatoshi Sekine , Tsutomu Takei , Hiroaki Nishi , Kazuyoshi Kohno , Takeshi Kitahara , Atsushi Masuda
发明人： Masami Aihara , Masatoshi Sekine , Tsutomu Takei , Hiroaki Nishi , Kazuyoshi Kohno , Takeshi Kitahara , Atsushi Masuda
IPC分类号： G06F11/25 , G01R31/3183 , G06F17/50 , G06F15/60
CPC分类号： G01R31/318357 , G01R31/318307 , G06F17/5022
摘要： Disclosed is a test assistant system for a logical design process comprising a description storage data base for storing statements expressing logical functions of circuit components to be tested, a compiler for compiling the statements to output object data, a data base for storing the object data, a test pattern generator for generating test patterns by using the object data stored in the data base, a test pattern data base for storing the test patterns, each having a level number, a simulator for executing a simulation for the logical function by using the test patterns stored in the test pattern data base, and a display for displaying the object data, the test patterns, the information used in the simulation, and relationships among them. The data base comprises a region for storing a statement correspondence table expressing statements as descriptions of the logical functions of the circuit components, a region for storing a circuit component table expressing a circuit component corresponding to the function described in the statement, a region for storing a dependent relationship table expressing the dependent relationship between the statements, and a correspondence relationship table expressing the correspondence relationship between the statement correspondence table and the circuit component table.
摘要翻译：公开了一种用于逻辑设计过程的测试辅助系统，包括用于存储表示要测试的电路组件的逻辑功能的语句的描述存储数据库，用于编译语句以输出对象数据的编译器，用于存储对象数据的数据库，用于通过使用存储在数据库中的对象数据来生成测试模式的测试模式发生器，用于存储测试模式的测试模式数据库，每个具有级别号码，用于通过使用测试执行用于逻辑功能的模拟的模拟器存储在测试模式数据库中的模式，以及用于显示对象数据，测试模式，模拟中使用的信息以及它们之间的关系的显示。数据库包括用于存储表示语句的语句对应表的区域，作为对电路组件的逻辑功能的描述的区域，用于存储表示对应于语句中描述的功能的电路组件的电路组件表的区域，用于存储表示语句之间的依赖关系的依赖关系表和表示语句对应表与电路分量表之间的对应关系的对应关系表。

2. 发明授权

US07974203B2 Traffic control system, traffic control method, communication device and computer program 有权
标题翻译：交通控制系统，交通管制方法，通讯装置及电脑程式
公开(公告)号：US07974203B2
公开(公告)日：2011-07-05
申请号：US11450079
申请日：2006-06-09
申请人： Takeshi Kitahara , Masaki Fukushima , Yoji Kishi , Hajime Nakamura
发明人： Takeshi Kitahara , Masaki Fukushima , Yoji Kishi , Hajime Nakamura
IPC分类号： H04J1/16
CPC分类号： H04L47/10 , H04L43/0829 , H04L43/0864 , H04L43/0882 , H04L47/11 , H04L47/2441 , H04L47/2475 , H04L47/283
摘要： The invention is directed to a traffic control system. The traffic control system comprises a communication device. The communication device includes a traffic type differentiation unit for differentiating a traffic type of an application that generates traffic to be processed on a communication network, a traffic control execution unit for controlling the traffic according to a traffic control condition corresponding to the traffic type, and a setting change reception unit for receiving setting change information on the traffic type or setting change information on the traffic control condition from the communication network. The traffic control system also comprises a setting change information transmission device provided on the communication network for transmitting setting change information.
摘要翻译：本发明涉及交通控制系统。交通控制系统包括通信设备。通信装置包括：业务类型区分单元，用于区分在通信网络上生成要处理的业务的应用的业务类型;业务控制执行单元，用于根据对应于业务类型的业务控制条件来控制业务;以及设置变更接收单元，用于从通信网络接收关于业务类型的设置改变信息或关于业务控制条件的设置改变信息。交通控制系统还包括设置在通信网络上用于发送设置改变信息的设置改变信息传输设备。

3. 发明授权

US07962883B2 Developing semiconductor circuit design with conditional flipflops to save power consumption 失效
标题翻译：开发具有条件触发器的半导体电路设计，以节省功耗
公开(公告)号：US07962883B2
公开(公告)日：2011-06-14
申请号：US12195574
申请日：2008-08-21
申请人： Takeshi Kitahara , Tetsuaki Utsumi
发明人： Takeshi Kitahara , Tetsuaki Utsumi
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/62
摘要： This disclosure concerns a semiconductor circuit design method for designing a clock wiring structure supplying a clock to a flip-flop by using a computer. The semiconductor circuit design method comprises setting the flip-flop based on circuit information on a semiconductor integrated circuit; obtaining a control signal controlling the flip-flop; calculating a first evaluation value indicating a power consumption and a magnitude of a clock skew time when clock gating is applied to the flip-flop; setting a gated clock structure clock-gating the flip-flop when the first evaluation value is higher than a first threshold; calculating a second evaluation value indicating the power consumption and a magnitude of a cell area when a low power flip-flop lower in power consumption than the flip-flop is applied to the flip-flop; and replacing the flip-flop by the lower power flip-flop when the second evaluation value is higher than a second threshold.
摘要翻译：本公开涉及一种用于设计通过使用计算机向触发器提供时钟的时钟布线结构的半导体电路设计方法。半导体电路设计方法包括：基于半导体集成电路上的电路信息设置触发器; 获得控制所述触发器的控制信号; 计算指示当触发器施加时钟选通时的功耗和时钟偏移时间的大小的第一评估值; 当所述第一评估值高于第一阈值时，设置门控时钟结构时钟门控所述触发器; 当触发器的功耗低于低功耗触发器的情况下，计算指示功率消耗的第二评估值和小区面积的大小; 以及当所述第二评估值高于第二阈值时由所述较低功率触发器替换所述触发器。

4. 发明授权

US07889688B2 Radio communication apparatus and traffic control method for extending drive-time of battery 有权
标题翻译：无线电通信装置和用于延长电池驱动时间的交通控制方法
公开(公告)号：US07889688B2
公开(公告)日：2011-02-15
申请号：US11785621
申请日：2007-04-19
申请人： Takeshi Kitahara , Hajime Nakamura , Satoshi Konishi
发明人： Takeshi Kitahara , Hajime Nakamura , Satoshi Konishi
IPC分类号： G08C17/00
CPC分类号： H04W52/0277 , H04W28/10 , Y02D70/00
摘要： A radio communication apparatus has a battery, a transmit buffer for temporarily accumulating packets to be sent, a battery state monitoring unit for monitoring a battery state of the battery, and a traffic control unit. The traffic control unit determines a packet burst length and an interval time between the packet bursts in order to obtain charge recovery effect based on the battery state, and controls so as to take out data packets of the packet burst length from the transmit buffer for every interval time between the packet bursts of the packet burst.
摘要翻译：无线电通信装置具有电池，用于临时存储要发送的分组的发送缓冲器，用于监视电池的电池状态的电池状态监视单元和业务控制单元。流量控制单元确定分组突发长度和分组突发之间的间隔时间，以便基于电池状态获得电荷恢复效果，并且控制以便从每个发送缓冲器取出数据包突发长度的数据分组分组突发的分组突发之间的间隔时间。

5. 发明申请

US20100258233A1 CERAMIC SUBSTRATE, METHOD OF MANUFACTURING CERAMIC SUBSTRATE, AND METHOD OF MANUFACTURING POWER MODULE SUBSTRATE 审中-公开
标题翻译：陶瓷基板，制造陶瓷基板的方法和制造功率模块基板的方法
公开(公告)号：US20100258233A1
公开(公告)日：2010-10-14
申请号：US12734428
申请日：2008-11-06
申请人： Hiroshi Tonomura , Takeshi Kitahara , Hiroya Ishizuka , Yoshirou Kuromitsu , Yoshiyuki Nagatomo
发明人： Hiroshi Tonomura , Takeshi Kitahara , Hiroya Ishizuka , Yoshirou Kuromitsu , Yoshiyuki Nagatomo
IPC分类号： B32B37/04 , C04B35/14 , B29C35/08 , G01N33/38 , C04B35/64
CPC分类号： B23K1/20 , C04B35/584 , C04B37/026 , C04B2235/72 , C04B2235/721 , C04B2235/723 , C04B2235/96 , C04B2237/121 , C04B2237/128 , C04B2237/368 , C04B2237/402 , C04B2237/52 , C04B2237/704 , C04B2237/706 , C04B2237/86 , H01L21/4807 , H01L21/481 , H01L23/15 , H01L23/3735 , H01L23/4006 , H01L23/473 , H01L2224/32225 , H01L2224/48227 , H01L2924/1305 , H01L2924/13055 , H05K1/0306 , H05K3/0029 , H05K3/0052 , H05K3/38 , H05K3/381 , H05K2201/0355 , H05K2201/09036 , H05K2201/0909 , H05K2203/095 , Y10T29/49155 , H01L2924/00
摘要： Disclosed is a ceramic substrate including silicon in which the concentration of a silicon oxide and a silicon composite oxide in the surface thereof is less than or equal to 2.7 Atom %.
摘要翻译：公开了包括硅的陶瓷基板，其表面中的氧化硅和硅复合氧化物的浓度小于或等于2.7原子％。

6. 发明授权

US07629471B2 Transcriptional factor, process for producing the same and use thereof 有权
标题翻译：转录因子，其生产方法及其应用
公开(公告)号：US07629471B2
公开(公告)日：2009-12-08
申请号：US10546854
申请日：2004-02-24
申请人： Takeshi Kitahara , Hidenori Watanabe , Kunio Ando
发明人： Takeshi Kitahara , Hidenori Watanabe , Kunio Ando
IPC分类号： C07D213/80 , C07D211/78 , A61K31/34
CPC分类号： C07D307/32 , C07C403/10 , C07C403/12 , C07C403/14 , C07C403/18 , C07C2601/14
摘要： Ascochlorin or an analog or derivative thereof and a compound having a primary amino group are mixed and reacted with each other in the presence/absence of a basic catalyst to synthesize a novel imino compound. The novel imino compound thus synthesized is a ligand capable of activating nuclear receptor superfamily such as retinoid orphan receptor (RXR), peroxisome proliferator-activated receptor (PPAR) and steroid receptor (PXR), and shows an effect of promoting the transcription of a drug-metabolizing enzyme CYP7A1. The imino compound has a therapeutic effect on diseases such as lifestyle-related diseases, chronic inflammation and cancers.
摘要翻译：在碱性催化剂存在/不存在下，将异烟肼或其类似物或衍生物和具有伯氨基的化合物混合并相互反应以合成新的亚氨基化合物。由此合成的新型亚氨基化合物是能够激活核受体超家族的配体，例如类视色素孤儿受体（RXR），过氧化物酶体增殖物激活受体（PPAR）和类固醇受体（PXR），并且显示促进药物转录的作用代谢酶CYP7A1。亚氨基化合物对生活方式相关疾病，慢性炎症和癌症等疾病具有治疗作用。

7. 发明申请

US20090267215A1 POWER MODULE SUBSTRATE, METHOD FOR MANUFACTURING POWER MODULE SUBSTRATE, AND POWER MODULE 有权
标题翻译：功率模块基板，制造功率模块基板的方法和功率模块
公开(公告)号：US20090267215A1
公开(公告)日：2009-10-29
申请号：US12446826
申请日：2007-10-26
申请人： Takeshi Kitahara , Hiroya Ishizuka , Yoshirou Kuromitsu , Tomoyuki Watanabe
发明人： Takeshi Kitahara , Hiroya Ishizuka , Yoshirou Kuromitsu , Tomoyuki Watanabe
IPC分类号： H01L23/488 , H01L23/15 , H01L21/60
CPC分类号： H01L23/3735 , H01L24/29 , H01L24/32 , H01L24/83 , H01L25/072 , H01L2224/291 , H01L2224/32225 , H01L2224/83424 , H05K1/0306 , H05K1/09 , H05K3/0061 , H05K3/202 , H05K3/38 , H05K2201/0355 , H05K2201/068 , H05K2203/0405 , H01L2924/014
摘要： Disclosed is a power module having improved joint reliability. Specifically disclosed is a power module including a power module substrate wherein a circuit layer is brazed on the front surface of a ceramic substrate, a metal layer is brazed on the rear surface of the ceramic substrate and a semiconductor chip is soldered to the circuit layer. The metal layer is composed of an Al alloy having an average purity of not less than 98.0 wt. % but not more than 99.9 wt. % as a whole. In this metal layer, the Fe concentration in the side of a surface brazed with the ceramic substrate is set at less than 0.1 wt. %, and the Fe concentration in the side of a surface opposite to the brazed surface is set at not less than 0.1 wt. %.
摘要翻译：公开了具有改进的接头可靠性的功率模块。具体公开了一种功率模块，其包括功率模块基板，其中电路层钎焊在陶瓷基板的前表面上，金属层钎焊在陶瓷基板的后表面上，半导体芯片焊接到电路层。金属层由平均纯度不小于98.0重量％的Al合金构成。％但不超过99.9wt。作为一个整体。在该金属层中，将与陶瓷基板钎焊的表面侧的Fe浓度设定为小于0.1重量％。％，并且与钎焊表面相反的表面侧的Fe浓度设定为0.1重量％以上。％。

8. 发明授权

US07543258B2 Clock design apparatus and clock design method 失效
标题翻译：时钟设计装置和时钟设计方法
公开(公告)号：US07543258B2
公开(公告)日：2009-06-02
申请号：US11402525
申请日：2006-04-11
申请人： Takeshi Kitahara , Yoshiki Tsukiboshi
发明人： Takeshi Kitahara , Yoshiki Tsukiboshi
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5077 , G06F17/505 , G06F2217/62 , G06F2217/78
摘要： A clock design apparatus includes a delay time adjusting section, a prohibition specifying section and a clock tree synthesis section. The delay time adjusting section is configured to adjust signal delay time of signal propagation paths on a semiconductor integrated circuit to be designed. The prohibition specifying section is configured to specify a part of the signal propagation paths as a circuit prevented from being changed. The clock tree synthesis section is configured to synthesize a clock tree of the semiconductor integrated circuit in accordance with the specification made by the prohibition specifying section.
摘要翻译：时钟设计装置包括延迟时间调整部分，禁止指定部分和时钟树合成部分。延迟时间调整部被配置为调整要设计的半导体集成电路上的信号传播路径的信号延迟时间。禁止指定部分被配置为指定阻止改变的电路的一部分信号传播路径。时钟树合成部分被配置为根据禁止指定部分制定的规范来合成半导体集成电路的时钟树。

9. 发明授权

US06668363B2 Clock supplying circuit and method having enable buffer cells with first and second input terminals 失效
标题翻译：具有使能缓冲单元的第一和第二输入端的时钟供给电路和方法
公开(公告)号：US06668363B2
公开(公告)日：2003-12-23
申请号：US09875159
申请日：2001-06-07
申请人： Fumihiro Minami , Takeshi Kitahara , Kimiyoshi Usami , Seiichi Nishio
发明人： Fumihiro Minami , Takeshi Kitahara , Kimiyoshi Usami , Seiichi Nishio
IPC分类号： G06F1750
CPC分类号： G06F17/505 , G06F2217/78
摘要： A computer aided design technique for clock gated logic circuits effective to reduce the electric power consumption is disclosed. The computer aided design for clock gated logic circuits is conducted by extracting, by the use of information about a clock gated logic circuit under the design, a halt condition under which a clocked circuit driven by a clock signal can halt with no clock signal supplied, generating enable signal candidates, from a halt condition, which can be used as enable signals in the clock gated logic circuit, analyzing the clock gated logic circuit in order to obtain information about a delay time of signal transmission and electric power consumption reduction if respective one of enable signal candidates is used as an enable signal of a clock gating circuit inserted in the clock gated logic circuit under the design, storing enable signal candidate information including the result of the analysis conducted by an analysis step in an information store, selecting an appropriate one of the enable signal candidates which satisfy given restrictions regarding a delay time of signal transmission in the clock gated logic circuit under the design, by the use of enable signal candidate information; and adding the clock gating circuit activated with the enable signal as selected by enable signal selection step to the clock gated logic circuit under the design.
摘要翻译：公开了一种有效降低功耗的时钟选通逻辑电路的计算机辅助设计技术。用于时钟门控逻辑电路的计算机辅助设计是通过使用设计下的时钟门控逻辑电路的信息来提取停止条件，在该停止条件下，由时钟信号驱动的时钟电路可以在没有提供时钟信号的情况下停止，从可以用作时钟选通逻辑电路中的使能信号的停止条件产生使能信号候选，分析时钟门控逻辑电路，以便获得关于信号传输的延迟时间和电力消耗减少的信息，如果相应的一个使能信号候选被用作在设计下插入时钟门控逻辑电路中的时钟门控电路的使能信号，存储包括通过信息存储中的分析步骤进行的分析结果的使能信号候选信息，选择适当的满足关于信号传输的延迟时间的给定限制的使能信号候选中的一个 e时钟门控逻辑电路设计，通过使用使能信号候补信息; 并将通过使能信号选择步骤选择的使能信号激活的时钟选通电路设计为时钟门控逻辑电路。

10. 发明授权

US5689673A Apparatus and method for controlling instruction flow by using a matrix of transmission gates in super-scaler microprocessor and selectively delaying microprocessor instruction execution based on resource availability 失效
标题翻译：用于通过使用超级缩放微处理器中的传输门矩阵来控制指令流的装置和方法，并且基于资源可用性选择性地延迟微处理器指令执行
公开(公告)号：US5689673A
公开(公告)日：1997-11-18
申请号：US388602
申请日：1995-02-14
申请人： Takeshi Kitahara
发明人： Takeshi Kitahara
IPC分类号： G06F9/38 , G06F13/14 , G06F9/22 , G06F9/30
CPC分类号： G06F9/3885 , G06F9/3836 , G06F9/384
摘要： An instruction flow control circuit controls the selection and execution of instruction signals in a microprocessor having multiple execution units that can execute plural instructions at one time. The instruction flow control circuit compares a number of signals indicating how many execution units are available with a number of signals indicating how many execution units are required. The circuit is a matrix of transmission gates which propagate signals through, or shift signals between, various signal paths for available resources, depending on the signals requesting the executing units. A number of output gates suppress the execution of instruction signals where an execution unit is requested but none are available.
摘要翻译：指令流控制电路控制在具有多个可执行多个指令的执行单元的微处理器中的指令信号的选择和执行。指令流控制电路将指示有多少执行单元可用的多个信号与指示需要多少个执行单元的多个信号进行比较。电路是根据请求执行单元的信号，在各种用于可用资源的信号路径之间传播信号或传输信号的传输门矩阵。多个输出门禁止执行指令信号，其中执行单元被请求但没有可用。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式