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1. 发明申请

US20060267637A1 Calibration comparator circuit 失效
标题翻译：校准比较器电路
公开(公告)号：US20060267637A1
公开(公告)日：2006-11-30
申请号：US10569654
申请日：2004-09-08
申请人： Yoshiharu Umemura , Toshiyuki Okayasu , Toshiaki Awaji , Masahiro Yamakawa
发明人： Yoshiharu Umemura , Toshiyuki Okayasu , Toshiaki Awaji , Masahiro Yamakawa
IPC分类号： H03K5/22
CPC分类号： G01R31/31932 , G01R31/3191
摘要： There is provided a testing apparatus for testing a device under test, wherein the testing apparatus is provided with a timing generator for generating a timing signal indicating the timing at which a test signal is applied; a plurality of timing delay units for delaying the timing signal; a plurality of drivers for applying the test signals; a sampler for sampling the test signal and outputting a sample voltage; a comparator for outputting a comparison result indicating whether the sample voltage is higher than the reference voltage; a determination part for determining whether the sample voltage matches the reference voltage; and a timing calibration part for calibrating the delay time caused in the timing signal by the plurality of timing delay units in order to synchronize the timing at which the test signals are applied to the device under test.
摘要翻译：提供了一种用于测试被测设备的测试装置，其中测试装置设置有定时发生器，用于产生指示应用测试信号的定时的定时信号; 用于延迟定时信号的多个定时延迟单元; 用于施加测试信号的多个驱动器; 采样器，用于对测试信号进行采样并输出采样电压; 比较器，用于输出指示样品电压是否高于参考电压的比较结果; 确定部分，用于确定所述采样电压是否与所述参考电压相匹配; 以及定时校准部件，用于校准由多个定时延迟单元在定时信号中引起的延迟时间，以使测试信号被施加到被测器件的定时同步。

2. 发明授权

US07389190B2 Testing apparatus for testing a device under test and comparator circuit and calibration apparatus for the testing apparatus 失效
标题翻译：用于测试被测设备的测试装置和用于测试装置的比较器电路和校准装置
公开(公告)号：US07389190B2
公开(公告)日：2008-06-17
申请号：US10569654
申请日：2004-09-08
申请人： Yoshiharu Umemura , Toshiyuki Okayasu , Toshiaki Awaji , Masahiro Yamakawa
发明人： Yoshiharu Umemura , Toshiyuki Okayasu , Toshiaki Awaji , Masahiro Yamakawa
IPC分类号： G06F19/00
CPC分类号： G01R31/31932 , G01R31/3191
摘要： There is provided a testing apparatus for testing a device under test, wherein the testing apparatus is provided with a timing generator for generating a timing signal indicating the timing at which a test signal is applied; a plurality of timing delay units for delaying the timing signal; a plurality of drivers for applying the delayed test signals; a sampler for sampling the test signal and outputting a sample voltage; a comparator for outputting a comparison result indicating whether the sample voltage is higher than the reference voltage; a determination part for determining whether the sample voltage matches the reference voltage; and a timing calibration part for calibrating the delay time caused in the timing signal by the plurality of timing delay units in order to synchronize the timing at which the test signals are applied to the device under test.
摘要翻译：提供了一种用于测试被测设备的测试装置，其中测试装置设置有定时发生器，用于产生指示应用测试信号的定时的定时信号; 用于延迟定时信号的多个定时延迟单元; 用于应用延迟的测试信号的多个驱动器; 采样器，用于对测试信号进行采样并输出采样电压; 比较器，用于输出指示样品电压是否高于参考电压的比较结果; 确定部分，用于确定所述采样电压是否与所述参考电压相匹配; 以及定时校准部件，用于校准由多个定时延迟单元在定时信号中引起的延迟时间，以使测试信号被施加到被测器件的定时同步。

3. 发明申请

US20060097898A1 Sampling circuit 有权
标题翻译：采样电路
公开(公告)号：US20060097898A1
公开(公告)日：2006-05-11
申请号：US11271132
申请日：2005-11-10
申请人： Masahiro Yamakawa , Yoshiharu Umemura , Toshiaki Awaji , Satoshi Shiwa
发明人： Masahiro Yamakawa , Yoshiharu Umemura , Toshiaki Awaji , Satoshi Shiwa
IPC分类号： H03M1/10
CPC分类号： H03M1/1245
摘要： A sampling circuit for compensating the phase difference of a sampling pulse due to a temperature variation to accurately sample input signals is provided. The sampling circuit samples received input signals. The sampling circuit includes a pulse generator for generating a pulse signal according to a timing at which an input signal should be sampled, a step recovery diode for outputting a sampling pulse responsive to the pulse signal, a detector for detecting the value for the input signal according to the sampling pulse, a temperature detecting circuit for detecting the temperature around the step recovery diode and a temperature compensating unit for controlling a timing at which the step recovery diode outputs the sampling pulse based on the temperature detected by the temperature detecting circuit.
摘要翻译：提供了一种用于补偿由于温度变化导致的采样脉冲的相位差以准确采样输入信号的采样电路。采样电路对接收到的输入信号进行采样。采样电路包括脉冲发生器，用于根据输入信号应采样的定时产生脉冲信号;步骤恢复二极管，用于响应脉冲信号输出采样脉冲;检测器，用于检测输入信号的值根据采样脉冲，用于检测阶梯恢复二极管周围的温度的温度检测电路和温度补偿单元，用于根据由温度检测电路检测到的温度来控制阶梯恢复二极管输出采样脉冲的定时。

4. 发明授权

US07208982B2 Sampling circuit 有权
标题翻译：采样电路
公开(公告)号：US07208982B2
公开(公告)日：2007-04-24
申请号：US11271132
申请日：2005-11-10
申请人： Masahiro Yamakawa , Yoshiharu Umemura , Toshiaki Awaji , Satoshi Shiwa
发明人： Masahiro Yamakawa , Yoshiharu Umemura , Toshiaki Awaji , Satoshi Shiwa
IPC分类号： G11C27/02
CPC分类号： H03M1/1245
摘要： A sampling circuit for compensating the phase difference of a sampling pulse due to a temperature variation to accurately sample input signals is provided. The sampling circuit samples received input signals. The sampling circuit includes a pulse generator for generating a pulse signal according to a timing at which an input signal should be sampled, a step recovery diode for outputting a sampling pulse responsive to the pulse signal, a detector for detecting the value for the input signal according to the sampling pulse, a temperature detecting circuit for detecting the temperature around the step recovery diode and a temperature compensating unit for controlling a timing at which the step recovery diode outputs the sampling pulse based on the temperature detected by the temperature detecting circuit.
摘要翻译：提供了一种用于补偿由于温度变化导致的采样脉冲的相位差以准确采样输入信号的采样电路。采样电路对接收到的输入信号进行采样。采样电路包括脉冲发生器，用于根据输入信号应采样的定时产生脉冲信号;步骤恢复二极管，用于响应脉冲信号输出采样脉冲;检测器，用于检测输入信号的值根据采样脉冲，用于检测阶梯恢复二极管周围的温度的温度检测电路和温度补偿单元，用于根据由温度检测电路检测的温度来控制阶梯恢复二极管输出采样脉冲的定时。

5. 发明授权

US08598902B2 Probe, electronic device test apparatus, and method of producing the same 失效
标题翻译：探针，电子装置试验装置及其制造方法
公开(公告)号：US08598902B2
公开(公告)日：2013-12-03
申请号：US12994579
申请日：2009-05-12
申请人： Yoshiharu Umemura , Kensuke Kato , Yoshirou Nakata , Naomi Miyake
发明人： Yoshiharu Umemura , Kensuke Kato , Yoshirou Nakata , Naomi Miyake
IPC分类号： G01R31/20
CPC分类号： G01R1/0735 , G01R1/07378 , G01R3/00
摘要： A probe comprises: a membrane having a bump which contacts an input/output terminal of an IC device built into a semiconductor wafer under test; a pitch conversion board having a bottom surface on which a first terminal is provided and a top surface on which a second terminal connected to the first terminal is provided; a circuit board which is electrically connected to a test head and has a third terminal; a first anisotropic conductive rubber member having a first conductor part which electrically connects the bump of the membrane and the first terminal of the pitch conversion board; and a second anisotropic conductive rubber member having a second conductor part which electrically connects the second terminal of the pitch conversion board and the third terminal of the circuit board, and the second conductor parts are provided on the whole of the second anisotropic conductive rubber member.
摘要翻译：探针包括：膜，其具有与内置于被测半导体晶片内的IC器件的输入/输出端接触的凸块; 具有设置有第一端子的底面的俯仰变换板和设置有与第一端子连接的第二端子的顶面; 电连接到测试头并具有第三端子的电路板; 第一各向异性导电橡胶构件，其具有使膜的凸块与俯仰变换基板的第一端子电连接的第一导体部; 以及第二各向异性导电橡胶构件，其具有电连接所述音调转换板的第二端子和所述电路板的第三端子的第二导体部分和所述第二导体部件，并且设置在所述第二各向异性导电橡胶构件的整体上。

6. 发明授权

US08513962B2 Wafer tray and test apparatus 有权
标题翻译：晶圆托盘和测试仪器
公开(公告)号：US08513962B2
公开(公告)日：2013-08-20
申请号：US12881137
申请日：2010-09-13
申请人： Toshiyuki Kiyokawa , Yoshiharu Umemura
发明人： Toshiyuki Kiyokawa , Yoshiharu Umemura
IPC分类号： G01R31/00
CPC分类号： H01L21/67207 , G01R31/2893 , H01L21/67346 , H01L21/681
摘要： In order to shorten testing time of a plurality of devices under test formed on a semiconductor wafer, a wafer tray used by a test apparatus performing the test is provided. The wafer tray includes a first flow passage for fixing the semiconductor wafer to the wafer tray using vacuum suction, a second flow passage for fixing the wafer tray to the test apparatus using vacuum suction, and a heater for heating a loading surface on which at least the semiconductor wafer is loaded. By using this wafer tray, the semiconductor wafer, which is the object being tested, can be smoothly attached to and detached from different test heads, and testing can be begun quickly after the semiconductor wafer is attached to a test head.
摘要翻译：为了缩短形成在半导体晶片上的多个待测器件的测试时间，提供了由执行测试的测试设备使用的晶片托盘。晶片托盘包括用于使用真空抽吸将半导体晶片固定到晶片托盘的第一流动通道，用于使用真空抽吸将晶片托盘固定到测试装置的第二流动通道，以及加热器，用于加热装载表面至少加载半导体晶片。通过使用该晶片托盘，作为被测定对象的半导体晶片能够平滑地安装到不同的测试头上并从其拆卸，并且可以在将半导体晶片安装到测试头之后快速开始测试。

7. 发明授权

US08410807B2 Test system and probe apparatus 有权
标题翻译：测试系统和探头设备
公开(公告)号：US08410807B2
公开(公告)日：2013-04-02
申请号：US12901484
申请日：2010-10-08
申请人： Yoshiharu Umemura , Yoshio Komoto
发明人： Yoshiharu Umemura , Yoshio Komoto
IPC分类号： G01R31/00
CPC分类号： G01R31/2891 , G01R1/0491 , G01R31/2893
摘要： A probe apparatus includes a wire substrate with terminals; a wafer tray forming a hermetically sealed space with the wire substrate and for mounting a semiconductor wafer; a probe wafer provided between the wire substrate and the wafer tray, having an apparatus connection terminal electrically connected to a terminal of the wire substrate and wafer connection terminals electrically connected to the semiconductor chips respectively and collectively; an apparatus anisotropic conductive sheet provided between the wire substrate and the probe wafer; a wafer anisotropic conductive sheet provided between the probe wafer and the semiconductor wafer; and a decompressing section that decompresses the hermetically sealed space between the wire substrate and the wafer tray, to cause the wafer tray to move to a predetermined position from the wire substrate, to electrically connect the wire substrate and the probe wafer, and to electrically connect the probe wafer and the semiconductor wafer.
摘要翻译：探针装置包括具有端子的线基板; 晶片托盘，用丝线基板形成密封空间并安装半导体晶片; 设置在所述线基板和所述晶片托盘之间的探针晶片，具有与所述线基板的端子电连接的装置连接端子和分别电连接到所述半导体芯片的晶片连接端子; 设置在线基板和探针晶片之间的装置各向异性导电片; 设置在探针晶片和半导体晶片之间的晶片各向异性导电片; 以及减压部，其对所述线基板和所述晶片托盘之间的密封空间进行减压，以使所述晶片托盘从所述线基板移动到预定位置，以电连接所述线基板和所述探针晶片，并且电连接探针晶片和半导体晶片。

8. 发明授权

US08289040B2 Test wafer unit and test system 有权
标题翻译：测试晶圆单元和测试系统
公开(公告)号：US08289040B2
公开(公告)日：2012-10-16
申请号：US12947721
申请日：2010-11-16
申请人： Yoshio Komoto , Yoshiharu Umemura , Shinichi Hamaguchi , Yasushi Kawaguchi
发明人： Yoshio Komoto , Yoshiharu Umemura , Shinichi Hamaguchi , Yasushi Kawaguchi
IPC分类号： G01R31/00
CPC分类号： G01R31/2874 , G01R31/2863 , G01R31/2867
摘要： A wafer unit for testing is electrically connected to a plurality of chips to be tested formed on a wafer to be tested, the wafer unit for testing including: a connecting wafer provided to face the wafer to be tested, and to be electrically connected to each of the plurality of chips to be tested; and a temperature distribution adjusting section provided on the connecting wafer, and to adjust a temperature distribution of the wafer to be tested.
摘要翻译：用于测试的晶片单元电连接到待测试的晶片上形成的待测试的多个芯片，用于测试的晶片单元包括：设置成面对待测晶片的连接晶片，并与每个芯片电连接的待测试的多个芯片; 以及温度分布调整部，设置在连接晶片上，并调整被测试晶片的温度分布。

9. 发明授权

US08134379B2 Probe wafer, probe device, and testing system 失效
标题翻译：探头晶圆，探针装置和测试系统
公开(公告)号：US08134379B2
公开(公告)日：2012-03-13
申请号：US12857478
申请日：2010-08-16
申请人： Yoshio Komoto , Yoshiharu Umemura
发明人： Yoshio Komoto , Yoshiharu Umemura
IPC分类号： G01R31/00
CPC分类号： G01R1/07378 , G01R31/2831
摘要： A probe wafer electrically connected to a semiconductor wafer on which a plurality of semiconductor chips are formed includes: a wafer substrate for pitch conversion including a wafer connection surface and an apparatus connection surface opposing the wafer connection surface; a plurality of wafer connection terminals formed on the wafer connection surface of the wafer substrate for pitch conversion, at least one wafer connection terminal provided for each of the semiconductor chips and electrically connected to an input/output terminal of the corresponding semiconductor chip; a plurality of apparatus connection terminals formed on the apparatus connection surface of the wafer substrate in one-to-one relation with the plurality of wafer connection terminals at an interval different from an interval of the wafer connection terminals, to be electrically connected to an external apparatus; and a plurality of transfer paths, each electrically connecting a corresponding wafer connection terminal to an apparatus connection terminal.
摘要翻译：电连接到其上形成有多个半导体芯片的半导体晶片的探针晶片包括：用于间距变换的晶片衬底，包括晶片连接表面和与晶片连接表面相对的器件连接表面; 形成在用于间距变换的晶片基板的晶片连接表面上的多个晶片连接端子，为每个半导体芯片设置的电连接到相应的半导体芯片的输入/输出端子的至少一个晶片连接端子; 多个装置连接端子以与晶片连接端子的间隔不同的间隔与所述多个晶片连接端子成一一对应地形成在所述晶片基板的所述装置连接面上，以电连接到外部仪器; 以及多个传送路径，每个传送路径将相应的晶片连接端子电连接到设备连接端子。

10. 发明申请

US20110121847A1 PROBE, ELECTRONIC DEVICE TEST APPARATUS, AND METHOD OF PRODUCING THE SAME 失效
标题翻译：探针，电子装置测试装置及其制造方法
公开(公告)号：US20110121847A1
公开(公告)日：2011-05-26
申请号：US12994579
申请日：2009-05-12
申请人： Yoshiharu Umemura
发明人： Yoshiharu Umemura
IPC分类号： G01R31/20
CPC分类号： G01R1/0735 , G01R1/07378 , G01R3/00
摘要： A probe comprises: a membrane having a bump which contacts an input/output terminal of an IC device built into a semiconductor wafer under test; a pitch conversion board having a bottom surface on which a first terminal is provided and a top surface on which a second terminal connected to the first terminal is provided; a circuit board which is electrically connected to a test head and has a third terminal; a first anisotropic conductive rubber member having a first conductor part which electrically connects the bump of the membrane and the first terminal of the pitch conversion board; and a second anisotropic conductive rubber member having a second conductor part which electrically connects the second terminal of the pitch conversion board and the third terminal of the circuit board, and the second conductor parts are provided on the whole of the second anisotropic conductive rubber member.
摘要翻译：探针包括：膜，其具有与内置于被测半导体晶片内的IC器件的输入/输出端接触的凸块; 具有设置有第一端子的底面的俯仰变换板和设置有与第一端子连接的第二端子的顶面; 电连接到测试头并具有第三端子的电路板; 第一各向异性导电橡胶构件，其具有使膜的凸块与俯仰变换基板的第一端子电连接的第一导体部; 以及第二各向异性导电橡胶构件，其具有电连接所述音调转换板的第二端子和所述电路板的第三端子的第二导体部分和所述第二导体部件，并且设置在所述第二各向异性导电橡胶构件的整体上。

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