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1. 发明授权

US08410807B2 Test system and probe apparatus 有权
标题翻译：测试系统和探头设备
公开(公告)号：US08410807B2
公开(公告)日：2013-04-02
申请号：US12901484
申请日：2010-10-08
申请人： Yoshiharu Umemura , Yoshio Komoto
发明人： Yoshiharu Umemura , Yoshio Komoto
IPC分类号： G01R31/00
CPC分类号： G01R31/2891 , G01R1/0491 , G01R31/2893
摘要： A probe apparatus includes a wire substrate with terminals; a wafer tray forming a hermetically sealed space with the wire substrate and for mounting a semiconductor wafer; a probe wafer provided between the wire substrate and the wafer tray, having an apparatus connection terminal electrically connected to a terminal of the wire substrate and wafer connection terminals electrically connected to the semiconductor chips respectively and collectively; an apparatus anisotropic conductive sheet provided between the wire substrate and the probe wafer; a wafer anisotropic conductive sheet provided between the probe wafer and the semiconductor wafer; and a decompressing section that decompresses the hermetically sealed space between the wire substrate and the wafer tray, to cause the wafer tray to move to a predetermined position from the wire substrate, to electrically connect the wire substrate and the probe wafer, and to electrically connect the probe wafer and the semiconductor wafer.
摘要翻译：探针装置包括具有端子的线基板; 晶片托盘，用丝线基板形成密封空间并安装半导体晶片; 设置在所述线基板和所述晶片托盘之间的探针晶片，具有与所述线基板的端子电连接的装置连接端子和分别电连接到所述半导体芯片的晶片连接端子; 设置在线基板和探针晶片之间的装置各向异性导电片; 设置在探针晶片和半导体晶片之间的晶片各向异性导电片; 以及减压部，其对所述线基板和所述晶片托盘之间的密封空间进行减压，以使所述晶片托盘从所述线基板移动到预定位置，以电连接所述线基板和所述探针晶片，并且电连接探针晶片和半导体晶片。

2. 发明授权

US08749260B2 Test wafer unit and test system 失效
标题翻译：测试晶圆单元和测试系统
公开(公告)号：US08749260B2
公开(公告)日：2014-06-10
申请号：US12947713
申请日：2010-11-16
申请人： Yasuo Tokunaga , Yoshio Komoto
发明人： Yasuo Tokunaga , Yoshio Komoto
IPC分类号： G01R31/00
CPC分类号： G01R31/318511 , G01R31/31723
摘要： Provided is a test wafer unit that tests a plurality of devices under test formed on a wafer under test, the test wafer unit comprising a plurality of test circuits that are formed on the same semiconductor wafer, where a plurality of types of the test circuits having different functions are provided for each device under test; and a selecting section that selects which type of test circuit is electrically connected to each pad of a device under test. Therefore, the test wafer unit can select the test circuit corresponding to testing content to be performed and connect this test circuit to the device under test to perform testing on a variety of devices under test or to perform a variety of tests on a device under test.
摘要翻译：提供了一种测试晶片单元，其测试在被测晶片上形成的多个待测器件，该测试晶片单元包括形成在同一半导体晶片上的多个测试电路，其中多种类型的测试电路具有为每个待测设备提供不同的功能; 以及选择部，其选择哪种类型的测试电路电连接到被测器件的每个焊盘。因此，测试晶片单元可以选择与要执行的测试内容相对应的测试电路，并将该测试电路连接到被测器件，以对被测设备上的各种器件进行测试，或者对被测器件进行各种测试。

3. 发明授权

US08624620B2 Test system and write wafer 有权
标题翻译：测试系统和写晶圆
公开(公告)号：US08624620B2
公开(公告)日：2014-01-07
申请号：US12952110
申请日：2010-11-22
申请人： Yasuo Tokunaga , Yoshio Komoto
发明人： Yasuo Tokunaga , Yoshio Komoto
IPC分类号： G01R31/02
CPC分类号： G01R31/318511 , G01R31/2889 , G11C29/006 , G11C29/56 , G11C29/56016 , G11C2029/5602
摘要： A test system for testing a plurality of semiconductor chips formed on a semiconductor wafer includes: a test wafer on which a plurality of test circuits corresponding to the plurality of semiconductor chips are formed, each test circuit testing a corresponding one of the plurality of semiconductor chips based on test data provided to the test circuit; where each of the plurality of test circuits includes a nonvolatile and rewritable pattern memory for storing the test data such as pattern data and sequence data, and the test system writes the same test data to all the plurality of test circuits in parallel.
摘要翻译：用于测试形成在半导体晶片上的多个半导体芯片的测试系统包括：测试晶片，其上形成有与多个半导体芯片对应的多个测试电路，每个测试电路测试多个半导体芯片中的相应一个半导体芯片基于提供给测试电路的测试数据; 其中多个测试电路中的每一个包括用于存储诸如模式数据和序列数据的测试数据的非易失性和可重写模式存储器，并且测试系统并行地向所有多个测试电路写入相同的测试数据。

4. 发明申请

US20120214261A1 TEST APPARATUS, TEST METHOD AND MANUFACTURING METHOD 有权
标题翻译：测试装置，测试方法和制造方法
公开(公告)号：US20120214261A1
公开(公告)日：2012-08-23
申请号：US13208350
申请日：2011-08-12
申请人： Yoshio Komoto
发明人： Yoshio Komoto
IPC分类号： H01L21/66 , G01R31/26
CPC分类号： G01R1/0735 , G01R1/0408
摘要： Provided is a test apparatus for testing a device under test, comprising a dicing section that dices a wafer on which a plurality of devices under test are formed to separate each of the devices under test; a test packaging section that packages each of the devices under test resulting from the dicing by the dicing section in an individual test package; a testing section that tests the devices under test packaged in the test packages; a removing section that removes the devices under test that have been tested from the test packages; and a commercial packaging section that packages the devices under test removed from the test packages in commercial packages.
摘要翻译：提供了一种用于测试被测器件的测试装置，包括：切割部分，其切割形成有多个被测器件的晶片，以分离每个被测器件; 一个测试包装部分，用于在每个测试包装中对通过切割部分切割的每个被测器件进行封装; 一个测试部分，测试包装在测试包中的被测设备; 一个去除部分，从测试包中移除被测试的器件; 以及将商业包装中的被测设备从测试包中包装的商业包装部分。

5. 发明申请

US20110115519A1 TEST SYSTEM AND WRITE WAFER 有权
标题翻译：测试系统和写波形
公开(公告)号：US20110115519A1
公开(公告)日：2011-05-19
申请号：US12952110
申请日：2010-11-22
申请人： Yasuo TOKUNAGA , Yoshio KOMOTO
发明人： Yasuo TOKUNAGA , Yoshio KOMOTO
IPC分类号： G01R31/26
CPC分类号： G01R31/318511 , G01R31/2889 , G11C29/006 , G11C29/56 , G11C29/56016 , G11C2029/5602
摘要： A test system for testing a plurality of semiconductor chips formed on a semiconductor wafer includes: a test wafer on which a plurality of test circuits corresponding to the plurality of semiconductor chips are formed, each test circuit testing a corresponding one of the plurality of semiconductor chips based on test data provided to the test circuit; where each of the plurality of test circuits includes a nonvolatile and rewritable pattern memory for storing the test data such as pattern data and sequence data, and the test system writes the same test data to all the plurality of test circuits in parallel.
摘要翻译：用于测试形成在半导体晶片上的多个半导体芯片的测试系统包括：测试晶片，其上形成有与多个半导体芯片对应的多个测试电路，每个测试电路测试多个半导体芯片中的相应一个半导体芯片基于提供给测试电路的测试数据; 其中多个测试电路中的每一个包括用于存储诸如模式数据和序列数据的测试数据的非易失性和可重写模式存储器，并且测试系统并行地向所有多个测试电路写入相同的测试数据。

6. 发明申请

US20110095777A1 TEST WAFER UNIT AND TEST SYSTEM 有权
标题翻译：测试波形单元和测试系统
公开(公告)号：US20110095777A1
公开(公告)日：2011-04-28
申请号：US12947721
申请日：2010-11-16
申请人： Yoshio KOMOTO , Yoshiharu UMEMURA , Shinichi HAMAGUCHI , Yasushi KAWAGUCHI
发明人： Yoshio KOMOTO , Yoshiharu UMEMURA , Shinichi HAMAGUCHI , Yasushi KAWAGUCHI
IPC分类号： G01R31/00
CPC分类号： G01R31/2874 , G01R31/2863 , G01R31/2867
摘要： A wafer unit for testing is electrically connected to a plurality of chips to be tested formed on a wafer to be tested, the wafer unit for testing including: a connecting wafer provided to face the wafer to be tested, and to be electrically connected to each of the plurality of chips to be tested; and a temperature distribution adjusting section provided on the connecting wafer, and to adjust a temperature distribution of the wafer to be tested.
摘要翻译：用于测试的晶片单元电连接到待测试的晶片上形成的待测试的多个芯片，用于测试的晶片单元包括：设置成面对待测晶片的连接晶片，并与每个芯片电连接的待测试的多个芯片; 以及温度分布调整部，设置在连接晶片上，并调整被测试晶片的温度分布。

7. 发明授权

US08667669B2 Apparatus and method for manufacturing a packaged device 失效
标题翻译：用于制造包装装置的装置和方法
公开(公告)号：US08667669B2
公开(公告)日：2014-03-11
申请号：US13208352
申请日：2011-08-12
申请人： Yoshio Komoto
发明人： Yoshio Komoto
IPC分类号： B23P19/00
CPC分类号： G01R31/01 , G01R31/2886 , H01L22/20 , H01L2924/0002 , H01L2924/014 , Y10T29/4913 , Y10T29/49149 , Y10T29/53039 , Y10T29/53061 , Y10T29/5317 , Y10T29/53174 , Y10T29/53178 , H01L2924/00
摘要： It is an objective of the present invention to eliminate wafer testing. Provided is a manufacturing apparatus comprising a detecting section that detects a position of a device terminal of a device; a generating section that generates a substrate-side terminal, which connects to the device terminal, on a substrate at a position corresponding to the device terminal; and a mounting section that mounts the device on the substrate and connects the device terminal to the substrate-side terminal. The detecting section captures an image of the device and detects the position of the device terminal based on the captured image, and the generating section prints a pattern of the substrate-side terminal on the substrate at a position corresponding to the device terminal.
摘要翻译：本发明的目的是消除晶片测试。提供一种制造装置，包括检测部件，其检测装置的装置端子的位置; 生成部，其在与所述装置端子对应的位置处，在基板上产生与所述装置端子连接的基板侧端子; 以及将该装置安装在基板上并将装置端子与基板侧端子连接的安装部。检测部分捕获设备的图像，并基于拍摄图像检测设备终端的位置，并且生成部件在与设备终端对应的位置处在基板上印刷基板侧端子的图案。

8. 发明授权

US08652857B2 Test apparatus, test method and manufacturing method for testing a device under test packaged in a test package 有权
标题翻译：用于测试包装在测试包中的被测器件的测试装置，测试方法和制造方法
公开(公告)号：US08652857B2
公开(公告)日：2014-02-18
申请号：US13208350
申请日：2011-08-12
申请人： Yoshio Komoto
发明人： Yoshio Komoto
IPC分类号： H01L21/66
CPC分类号： G01R1/0735 , G01R1/0408
摘要： Provided is a test apparatus for testing a device under test, including a dicing section that dices a wafer on which a plurality of devices under test are formed to separate each of the devices under test, a test packaging section that packages each of the devices under test resulting from the dicing by the dicing section in an individual test package, a testing section that tests the devices under test packaged in the test packages, a removing section that removes the devices under test that have been tested from the test packages, and a commercial packaging section that packages the devices under test removed from the test packages in commercial packages.
摘要翻译：提供了一种用于测试被测设备的测试设备，包括：切割部分，其切割形成有多个待测设备的晶片，以分离每个被测器件;测试封装部件，其将每个器件封装在在单独的测试包中由切割部分切割产生的测试，测试包装在测试包中的被测器件的测试部分，从测试包中去除被测试的器件的去除部分，以及商业包装部分，将待测设备包装在商业包装中的测试包中。

9. 发明授权

US08427187B2 Probe wafer, probe device, and testing system 有权
标题翻译：探头晶圆，探针装置和测试系统
公开(公告)号：US08427187B2
公开(公告)日：2013-04-23
申请号：US12857483
申请日：2010-08-16
申请人： Yoshio Komoto , Yoshiharu Umemura
发明人： Yoshio Komoto , Yoshiharu Umemura
IPC分类号： G01R31/00
CPC分类号： G01R31/2889
摘要： There is provided a testing system for testing a plurality of semiconductor chips formed on a single semiconductor wafer. The testing system includes a wafer substrate, a plurality of wafer connector terminals that are provided on the wafer substrate in such a manner that one or more wafer connector terminals correspond to each of the semiconductor chips, where each wafer connector terminal is to be electrically connected to an input/output terminal of a corresponding semiconductor chip, a plurality of circuit units that are provided on the wafer substrate in such a manner that one or more circuit units corresponds to each of the semiconductor chips, where each circuit unit generates a test signal to be used for testing a corresponding semiconductor chip and supplies the test signal to the corresponding semiconductor chip to test the corresponding semiconductor chip, and a controller that generates a control signal used to control the plurality of circuit units.
摘要翻译：提供了一种用于测试形成在单个半导体晶片上的多个半导体芯片的测试系统。测试系统包括晶片衬底，设置在晶片衬底上的多个晶片连接器端子，使得一个或多个晶片连接器端子对应于每个晶片连接器端子要电连接的每个半导体芯片连接到相应的半导体芯片的输入/输出端子，多个电路单元，其设置在晶片基板上，使得一个或多个电路单元对应于每个半导体芯片，其中每个电路单元产生测试信号用于测试对应的半导体芯片，并将测试信号提供给相应的半导体芯片以测试对应的半导体芯片;以及控制器，其产生用于控制多个电路单元的控制信号。

10. 发明申请

US20110062979A1 TEST SYSTEM AND PROBE APPARATUS 有权
标题翻译：测试系统和探测器
公开(公告)号：US20110062979A1
公开(公告)日：2011-03-17
申请号：US12901484
申请日：2010-10-08
申请人： Yoshiharu UMEMURA , Yoshio KOMOTO
发明人： Yoshiharu UMEMURA , Yoshio KOMOTO
IPC分类号： G01R1/067
CPC分类号： G01R31/2891 , G01R1/0491 , G01R31/2893
摘要： A probe apparatus includes a wire substrate with terminals; a wafer tray forming a hermetically sealed space with the wire substrate and for mounting a semiconductor wafer; a probe wafer provided between the wire substrate and the wafer tray, having an apparatus connection terminal electrically connected to a terminal of the wire substrate and wafer connection terminals electrically connected to the semiconductor chips respectively and collectively; an apparatus anisotropic conductive sheet provided between the wire substrate and the probe wafer; a wafer anisotropic conductive sheet provided between the probe wafer and the semiconductor wafer; and a decompressing section that decompresses the hermetically sealed space between the wire substrate and the wafer tray, to cause the wafer tray to move to a predetermined position from the wire substrate, to electrically connect the wire substrate and the probe wafer, and to electrically connect the probe wafer and the semiconductor wafer.
摘要翻译：探针装置包括具有端子的线基板; 晶片托盘，用丝线基板形成密封空间并安装半导体晶片; 设置在所述线基板和所述晶片托盘之间的探针晶片，具有与所述线基板的端子电连接的装置连接端子和分别电连接到所述半导体芯片的晶片连接端子; 设置在线基板和探针晶片之间的装置各向异性导电片; 设置在探针晶片和半导体晶片之间的晶片各向异性导电片; 以及减压部，其对所述线基板和所述晶片托盘之间的密封空间进行减压，以使所述晶片托盘从所述线基板移动到预定位置，以电连接所述线基板和所述探针晶片，并且电连接探针晶片和半导体晶片。

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