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1. 发明授权

US06403453B1 Dose control technique for plasma doping in ultra-shallow junction formations 有权
标题翻译：用于等离子体掺杂在超浅结结构中的剂量控制技术
公开(公告)号：US06403453B1
公开(公告)日：2002-06-11
申请号：US09626837
申请日：2000-07-27
申请人： Yoshi Ono , Yanjun Ma , Sheng Teng Hsu
发明人： Yoshi Ono , Yanjun Ma , Sheng Teng Hsu
IPC分类号： H01L2126
CPC分类号： H01L21/2236
摘要： A method of plasma doping substrates is provided. The substrate is covered with photoresist and placed within a plasma chamber. A doping gas is introduced into the chamber and ionized. A dilutant gas is also introduced to provide better control of the total amount of dosage associated with a given duration of exposure. The dilutant gas is preferably monatomic to reduce, or eliminate, affects associated with pressure variations within the chamber caused by dissociation of elements within the plasma chamber. The dilutant gas preferably contains lighter elements so as to reduce, or eliminate, damage to the photoresist caused by ion impacts. The dilutant gas is preferably neon or helium. The present method provides a means to better control the dosage and reduce photoresist damage and contamination.
摘要翻译：提供了一种等离子体掺杂衬底的方法。衬底被光致抗蚀剂覆盖并置于等离子体室内。将掺杂气体引入室并离子化。还引入稀释气体以更好地控制与给定的暴露持续时间相关的剂量的总量。稀释气体优选是单原子的，以减少或消除由等离子体室内的元素解离引起的室内压力变化的影响。稀释气体优选含有较轻的元素，以便减少或消除由离子冲击引起的光致抗蚀剂的损伤。稀释气体优选为氖气或氦气。本方法提供了更好地控制剂量并减少光致抗蚀剂损伤和污染的方法。

2. 发明授权

US06632731B2 Structure and method of making a sub-micron MOS transistor 失效
标题翻译：制造亚微米MOS晶体管的结构和方法
公开(公告)号：US06632731B2
公开(公告)日：2003-10-14
申请号：US09783760
申请日：2001-02-14
申请人： Yanjun Ma , David Russell Evans , Yoshi Ono , Sheng Teng Hsu
发明人： Yanjun Ma , David Russell Evans , Yoshi Ono , Sheng Teng Hsu
IPC分类号： H01L213205
CPC分类号： H01L29/6659 , H01L21/28088 , H01L21/28097 , H01L21/76895 , H01L21/76897 , H01L21/82385 , H01L29/42376 , H01L29/4966 , H01L29/4975 , H01L29/66545
摘要： A method of fabricating a sub-micron MOS transistor includes preparing a substrate, including isolating an active region therein; depositing a gate oxide layer; depositing a first selective etchable layer over the gate oxide layer; depositing a second selective etchable layer over the first selective etchable layer; etching the structure to undercut the first selective etchable layer; implanting ions in the active region to form a source region and a drain region; depositing and planarizing the oxide; removing the remaining first selective etchable layer and the second selective etchable layer; depositing a gate electrode; and depositing oxide and metallizing the structure. A sub-micron MOS transistor includes a substrate; and an active region, including a gate region having a length of less than one micron; a source region including a LDD source region; and a drain region including a LDD drain region.
摘要翻译：制造亚微米MOS晶体管的方法包括制备衬底，包括在其中分离有源区; 沉积栅氧化层; 在所述栅极氧化物层上沉积第一选择性可蚀刻层; 在第一选择性可蚀刻层上沉积第二选择性可蚀刻层; 蚀刻结构以切割第一选择性可蚀刻层; 在有源区中注入离子以形成源区和漏区; 沉积和平坦化氧化物; 去除剩余的第一选择性可蚀刻层和第二选择性可蚀刻层; 沉积栅电极; 并沉积氧化物并金属化该结构。亚微米MOS晶体管包括基板; 和有源区，包括具有小于1微米长度的栅区; 源区域，包括LDD源区域; 以及包括LDD漏极区域的漏极区域

3. 发明授权

US06573134B2 Dual metal gate CMOS devices and method for making the same 失效
公开(公告)号：US06573134B2
公开(公告)日：2003-06-03
申请号：US09817834
申请日：2001-03-27
申请人： Yanjun Ma , Yoshi Ono , David R. Evans , Sheng Teng Hsu
发明人： Yanjun Ma , Yoshi Ono , David R. Evans , Sheng Teng Hsu
IPC分类号： H01L218238
CPC分类号： H01L21/823842 , H01L27/092
摘要： A method of fabricating a dual metal gate CMOS includes forming a gate oxide in a gate region and depositing a place-holder gate in each of a n-well and p-well; removing the place-holder gate and gate oxide; depositing a high-k dielectric in the gate region; depositing a first metal in the gate region of the p-well; depositing a second metal in the gate region of each of the n-well and p-well; and insulating and metallizing the structure. A dual metal gate CMOS of the invention includes PMOS transistor and a NMOS transistor. In the NMOS, a gate includes a high-k cup, a first metal cup formed in the high-k cup, and a second metal gate formed in the first metal cup. In the PMOS, a gate includes a high-k cup and a second metal gate formed in the high-k cup.

4. 发明授权

US07811837B2 Terbium-doped, silicon-rich oxide electroluminescent devices and method of making the same 有权
标题翻译：铽掺杂，富硅氧化物电致发光器件及其制造方法
公开(公告)号：US07811837B2
公开(公告)日：2010-10-12
申请号：US11582275
申请日：2006-10-16
申请人： Tingkai Li , Wei Gao , Yoshi Ono , Sheng Teng Hsu
发明人： Tingkai Li , Wei Gao , Yoshi Ono , Sheng Teng Hsu
IPC分类号： H01L29/00
CPC分类号： H01L27/15 , H01L33/0004 , H01L33/343
摘要： A method of fabricating an electroluminescent device includes, on a prepared substrate, depositing a rare earth-doped silicon-rich layer on gate oxide layer as a light emitting layer; and annealing and oxidizing the structure to repair any damage caused to the rare earth-doped silicon-rich layer; and incorporating the electroluminescent device into a CMOS IC. An electroluminescent device fabricated according to the method of the invention includes a substrate, a rare earth-doped silicon-rich layer formed on the gate oxide layer for emitting a light of a pre-determined wavelength; a top electrode formed on the rare earth-doped silicon-rich layer; and associated CMOS IC structures fabricated thereabout.
摘要翻译：一种制造电致发光器件的方法包括：在制备的衬底上，在作为发光层的栅极氧化物层上沉积稀土掺杂的富硅层; 并对该结构进行退火和氧化以修复对稀土掺杂的富硅层造成的任何损伤; 并将电致发光器件并入CMOS IC。根据本发明的方法制造的电致发光器件包括：衬底，形成在栅极氧化物层上的用于发射预定波长的光的稀土掺杂富硅层; 在稀土掺杂的富硅层上形成的顶部电极; 并在其附近制造相关的CMOS IC结构。

5. 发明授权

US07462499B2 Carbon nanotube with ZnO asperities 失效
标题翻译：具有ZnO粗糙度的碳纳米管
公开(公告)号：US07462499B2
公开(公告)日：2008-12-09
申请号：US11262439
申请日：2005-10-28
申请人： John F. Conley, Jr. , Yoshi Ono , Lisa H. Stecker , Sheng Teng Hsu , Josh M. Green , Lifeng Dong , Jun Jiao
发明人： John F. Conley, Jr. , Yoshi Ono , Lisa H. Stecker , Sheng Teng Hsu , Josh M. Green , Lifeng Dong , Jun Jiao
IPC分类号： H01L21/00
CPC分类号： H01J9/025 , B82Y10/00 , B82Y30/00 , B82Y40/00 , C01B32/162 , C01B32/168 , C01B2202/34 , C01B2202/36 , H01J1/304 , H01J2201/30469 , H01L21/0237 , H01L21/02381 , H01L21/02444 , H01L21/02472 , H01L21/02483 , H01L21/02513 , H01L21/02554 , H01L21/02601 , Y10S977/754
摘要： A ZnO asperity-covered carbon nanotube (CNT) device has been provided, along with a corresponding fabrication method. The method comprises: forming a substrate; growing CNTs from the substrate; conformally coating the CNTs with ZnO; annealing the ZnO-coated CNTs; and, forming ZnO asperities on the surface of the CNTs in response to the annealing. In one aspect, the ZnO asperities have a density in the range of about 100 to 1000 ZnO asperities per CNT. The density is dependent upon the deposited ZnO film thickness and annealing parameters. The CNTs are conformally coating with ZnO using a sputtering, chemical vapor deposition (CVD), spin-on, or atomic layer deposition (ALD). For example, an ALD process can be to deposit a layer of ZnO over the CNTs having a thickness in the range of 1.2 to 200 nanometers (nm).
摘要翻译：已经提供了ZnO微粒覆盖碳纳米管（CNT）器件，以及相应的制造方法。该方法包括：形成衬底; 从底物生长CNT; 用ZnO共形涂覆CNT; 退火ZnO涂层的CNT; 并且响应于退火在CNT的表面上形成ZnO粗糙度。在一个方面，ZnO粗糙度的密度在每个CNT约100-1000nm的ZnO粗糙度的范围内。密度取决于沉积的ZnO膜厚度和退火参数。使用溅射，化学气相沉积（CVD），旋涂或原子层沉积（ALD），使用ZnO共形涂覆CNT。例如，ALD工艺可以在厚度在1.2至200纳米（nm）范围内的CNT上沉积ZnO层。

6. 发明授权

US06590243B2 Ferroelastic lead germanate thin film and deposition method 失效
公开(公告)号：US06590243B2
公开(公告)日：2003-07-08
申请号：US09301434
申请日：1999-04-28
申请人： Tingkai Li , Fengyan Zhang , Yoshi Ono , Sheng Teng Hsu
发明人： Tingkai Li , Fengyan Zhang , Yoshi Ono , Sheng Teng Hsu
IPC分类号： H01L2976
CPC分类号： H01L21/02197 , C23C16/40 , H01L21/02271 , H01L21/31604 , H01L21/31691
摘要： A Pb3GeO5 phase PGO thin film is provided. This film has ferroelastic properties that make it ideal for many microelectromechanical applications or as decoupling capacitors in high speed multichip modules. This PGO film is uniquely formed in a MOCVD process that permits a thin film, less than 1 mm, of material to be deposited. The process mixes Pd and germanium in a solvent. The solution is heated to form a precursor vapor which is decomposed. The method provides deposition temperatures and pressures. The as-deposited film is also annealed to enhanced the film's ferroelastic characteristics. A ferroelastic capacitor made from the present invention PGO film is also provided.

7. 发明授权

US07470573B2 Method of making CMOS devices on strained silicon on glass 失效
标题翻译：在玻璃上的应变硅上制造CMOS器件的方法
公开(公告)号：US07470573B2
公开(公告)日：2008-12-30
申请号：US11060878
申请日：2005-02-18
申请人： Jong-Jan Lee , Jer-Shen Maa , Douglas J. Tweet , Yoshi Ono , Sheng Teng Hsu
发明人： Jong-Jan Lee , Jer-Shen Maa , Douglas J. Tweet , Yoshi Ono , Sheng Teng Hsu
IPC分类号： H01L21/30 , H01L21/84
CPC分类号： H01L27/127 , H01L27/1214 , H01L27/1266 , H01L29/7842 , H01L29/78621
摘要： A method of making CMOS devices on strained silicon on glass includes preparing a glass substrate, including forming a strained silicon layer on the glass substrate; forming a silicon oxide layer by plasma oxidation of the strained silicon layer; depositing a layer of doped polysilicon on the silicon oxide layer; forming a polysilicon gate; implanting ions to form a LDD structure; depositing and forming a spacer dielectric on the gate structure; implanting and activation ions to form source and drain structures; depositing a layer of metal film; annealing the layer of metal film to form salicide on the source, drain and gate structures; removing any unreacted metal film; depositing a layer of interlayer dielectric; and forming contact holes and metallizing.
摘要翻译：在玻璃上的应变硅上制造CMOS器件的方法包括制备玻璃衬底，包括在玻璃衬底上形成应变硅层; 通过应变硅层的等离子体氧化形成氧化硅层; 在氧化硅层上沉积掺杂多晶硅层; 形成多晶硅栅极; 注入离子以形成LDD结构; 在栅极结构上沉积和形成间隔电介质; 植入和激活离子以形成源和漏结构; 沉积一层金属膜; 退火金属膜层，在源极，漏极和栅极结构上形成硅化物; 去除任何未反应的金属膜; 沉积层间电介质层; 并形成接触孔和金属化。

8. 发明申请

US20080164569A1 Terbium-doped, silicon-rich oxide electroluminescent devices and method of making the same 有权
标题翻译：铽掺杂，富硅氧化物电致发光器件及其制造方法
公开(公告)号：US20080164569A1
公开(公告)日：2008-07-10
申请号：US11582275
申请日：2006-10-16
申请人： Tingkai Li , Wei Gao , Yoshi Ono , Sheng Teng Hsu
发明人： Tingkai Li , Wei Gao , Yoshi Ono , Sheng Teng Hsu
IPC分类号： H01L29/00
CPC分类号： H01L27/15 , H01L33/0004 , H01L33/343
摘要： A method of fabricating an electroluminescent device includes, on a prepared substrate, depositing a rare earth-doped silicon-rich layer on gate oxide layer as a light emitting layer; and annealing and oxidizing the structure to repair any damage caused to the rare earth-doped silicon-rich layer; and incorporating the electroluminescent device into a CMOS IC. An electroluminescent device fabricated according to the method of the invention includes a substrate, a rare earth-doped silicon-rich layer formed on the gate oxide layer for emitting a light of a pre-determined wavelength; a top electrode formed on the rare earth-doped silicon-rich layer; and associated CMOS IC structures fabricated thereabout.
摘要翻译：一种制造电致发光器件的方法包括：在制备的衬底上，在作为发光层的栅极氧化物层上沉积稀土掺杂的富硅层; 并对该结构进行退火和氧化以修复对稀土掺杂的富硅层造成的任何损伤; 并将电致发光器件并入CMOS IC。根据本发明的方法制造的电致发光器件包括：衬底，形成在栅极氧化物层上的用于发射预定波长的光的稀土掺杂富硅层; 在稀土掺杂的富硅层上形成的顶部电极; 并在其附近制造相关的CMOS IC结构。

9. 发明授权

US07364989B2 Strain control of epitaxial oxide films using virtual substrates 有权
标题翻译：使用虚拟衬底的外延氧化膜的应变控制
公开(公告)号：US07364989B2
公开(公告)日：2008-04-29
申请号：US11174350
申请日：2005-07-01
申请人： Douglas J. Tweet , Yoshi Ono , David R. Evans , Sheng Teng Hsu
发明人： Douglas J. Tweet , Yoshi Ono , David R. Evans , Sheng Teng Hsu
IPC分类号： H01L21/20
CPC分类号： H01L21/02192 , H01L21/02197 , H01L21/0228 , H01L21/3147
摘要： A method of controlling strain in a single-crystal, epitaxial oxide film, includes preparing a silicon substrate; forming a silicon alloy layer taken from the group of silicon alloy layer consisting of Si1-xGex and Si1-yCy on the silicon substrate; adjusting the lattice constant of the silicon alloy layer by selecting the alloy material content to adjust and to select a type of strain for the silicon alloy layer; depositing a single-crystal, epitaxial oxide film, by atomic layer deposition, taken from the group of oxide films consisting of perovskite manganite materials, single crystal rare-earth oxides and perovskite oxides, not containing manganese; and rare earth binary and ternary oxides, on the silicon alloy layer; and completing a desired device.
摘要翻译：一种控制单晶外延氧化膜中的应变的方法包括制备硅衬底; 从由Si 1-x Ge x Si和Si 1-y C C组成的硅合金层组形成硅合金层 > y ; 通过选择合金材料含量来调整硅合金层的晶格常数，并选择一种用于硅合金层的应变; 从由不含锰的钙钛矿亚锰酸盐材料，单晶稀土氧化物和钙钛矿氧化物组成的氧化膜组中，通过原子层沉积法沉积单晶外延氧化膜; 和稀土二元和三元氧化物，在硅合金层上; 并完成所需的设备。

10. 发明授权

US06833572B2 Electrode materials with improved hydrogen degradation resistance 失效
标题翻译：具有改善耐氢降解性的电极材料
公开(公告)号：US06833572B2
公开(公告)日：2004-12-21
申请号：US10229603
申请日：2002-08-27
申请人： Fengyan Zhang , Tingkai Li , Hong Ying , Yoshi Ono , Sheng Teng Hsu
发明人： Fengyan Zhang , Tingkai Li , Hong Ying , Yoshi Ono , Sheng Teng Hsu
IPC分类号： H01L2976
CPC分类号： H01L28/75 , H01L21/31604 , H01L21/31683 , H01L28/55
摘要： An electrode for use in a ferroelectric device includes a bottom electrode; a ferroelectric layer; and a top electrode formed on the ferroelectric layer and formed of a combination of metals, including a first metal take from the group of metals consisting of platinum and iridium, and a second metal taken from the group of metals consisting of aluminum and titanium; wherein the top electrode acts as a passivation layer and wherein the top electrode remains conductive following high temperature annealing in a hydrogen atmosphere. A method of forming a hydrogen-resistant electrode in a ferroelectric device includes forming a bottom electrode; forming a ferroelectric layer on the bottom electrode; depositing a top electrode on the ferroelectric layer; including depositing, simultaneously, a first metal taken from the group of metals consisting of platinum and iridium; and a second metal taken from the group of metals consisting of aluminum and titanium; and forming a passivation layer by annealing the structure in an oxygen atmosphere to form an oxide passivation layer on the top electrode.
摘要翻译：用于铁电体器件的电极包括底部电极; 铁电层以及形成在强电介质层上并由金属组合形成的顶部电极，其包括从由铂和铱组成的金属组中的第一金属取得的金属和从由铝和钛组成的金属组中的第二金属; 其中所述顶部电极用作钝化层，并且其中所述顶部电极在氢气氛中的高温退火之后保持导电。在铁电体器件中形成耐氢电极的方法包括形成底电极; 在底部电极上形成铁电层; 在铁电层上沉积顶部电极; 包括同时从由铂和铱组成的金属组中取出的第一金属; 和从由铝和钛组成的金属组中获取的第二金属; 以及通过在氧气氛中对所述结构退火以在所述顶部电极上形成氧化物钝化层来形成钝化层。

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