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1. 发明授权

US07364989B2 Strain control of epitaxial oxide films using virtual substrates 有权
标题翻译：使用虚拟衬底的外延氧化膜的应变控制
公开(公告)号：US07364989B2
公开(公告)日：2008-04-29
申请号：US11174350
申请日：2005-07-01
申请人： Douglas J. Tweet , Yoshi Ono , David R. Evans , Sheng Teng Hsu
发明人： Douglas J. Tweet , Yoshi Ono , David R. Evans , Sheng Teng Hsu
IPC分类号： H01L21/20
CPC分类号： H01L21/02192 , H01L21/02197 , H01L21/0228 , H01L21/3147
摘要： A method of controlling strain in a single-crystal, epitaxial oxide film, includes preparing a silicon substrate; forming a silicon alloy layer taken from the group of silicon alloy layer consisting of Si1-xGex and Si1-yCy on the silicon substrate; adjusting the lattice constant of the silicon alloy layer by selecting the alloy material content to adjust and to select a type of strain for the silicon alloy layer; depositing a single-crystal, epitaxial oxide film, by atomic layer deposition, taken from the group of oxide films consisting of perovskite manganite materials, single crystal rare-earth oxides and perovskite oxides, not containing manganese; and rare earth binary and ternary oxides, on the silicon alloy layer; and completing a desired device.
摘要翻译：一种控制单晶外延氧化膜中的应变的方法包括制备硅衬底; 从由Si 1-x Ge x Si和Si 1-y C C组成的硅合金层组形成硅合金层 > y ; 通过选择合金材料含量来调整硅合金层的晶格常数，并选择一种用于硅合金层的应变; 从由不含锰的钙钛矿亚锰酸盐材料，单晶稀土氧化物和钙钛矿氧化物组成的氧化膜组中，通过原子层沉积法沉积单晶外延氧化膜; 和稀土二元和三元氧化物，在硅合金层上; 并完成所需的设备。

2. 发明授权

US07470573B2 Method of making CMOS devices on strained silicon on glass 失效
标题翻译：在玻璃上的应变硅上制造CMOS器件的方法
公开(公告)号：US07470573B2
公开(公告)日：2008-12-30
申请号：US11060878
申请日：2005-02-18
申请人： Jong-Jan Lee , Jer-Shen Maa , Douglas J. Tweet , Yoshi Ono , Sheng Teng Hsu
发明人： Jong-Jan Lee , Jer-Shen Maa , Douglas J. Tweet , Yoshi Ono , Sheng Teng Hsu
IPC分类号： H01L21/30 , H01L21/84
CPC分类号： H01L27/127 , H01L27/1214 , H01L27/1266 , H01L29/7842 , H01L29/78621
摘要： A method of making CMOS devices on strained silicon on glass includes preparing a glass substrate, including forming a strained silicon layer on the glass substrate; forming a silicon oxide layer by plasma oxidation of the strained silicon layer; depositing a layer of doped polysilicon on the silicon oxide layer; forming a polysilicon gate; implanting ions to form a LDD structure; depositing and forming a spacer dielectric on the gate structure; implanting and activation ions to form source and drain structures; depositing a layer of metal film; annealing the layer of metal film to form salicide on the source, drain and gate structures; removing any unreacted metal film; depositing a layer of interlayer dielectric; and forming contact holes and metallizing.
摘要翻译：在玻璃上的应变硅上制造CMOS器件的方法包括制备玻璃衬底，包括在玻璃衬底上形成应变硅层; 通过应变硅层的等离子体氧化形成氧化硅层; 在氧化硅层上沉积掺杂多晶硅层; 形成多晶硅栅极; 注入离子以形成LDD结构; 在栅极结构上沉积和形成间隔电介质; 植入和激活离子以形成源和漏结构; 沉积一层金属膜; 退火金属膜层，在源极，漏极和栅极结构上形成硅化物; 去除任何未反应的金属膜; 沉积层间电介质层; 并形成接触孔和金属化。

3. 发明授权

US06720258B2 Method of fabricating a nickel silicide on a substrate 有权
标题翻译：在衬底上制造硅化镍的方法
公开(公告)号：US06720258B2
公开(公告)日：2004-04-13
申请号：US10319313
申请日：2002-12-12
申请人： Jer-shen Maa , Douglas J. Tweet , Yoshi Ono , Fengyan Zhang , Sheng Teng Hsu
发明人： Jer-shen Maa , Douglas J. Tweet , Yoshi Ono , Fengyan Zhang , Sheng Teng Hsu
IPC分类号： H01L2144
CPC分类号： H01L21/28518 , H01L29/456
摘要： An integrated circuit device, and a method of manufacturing the same, comprises an epitaxial nickel silicide on (100) Si, or a stable nickel silicide on amorphous Si, fabricated with a cobalt interlayer. In one embodiment the method comprises depositing a cobalt (Co) interface layer between the Ni and Si layers prior to the silicidation reaction. The cobalt interlayer regulates the flux of the Ni atoms through the cobalt/nickel/silicon alloy layer formed from the reaction of the cobalt interlayer with the nickel and the silicon so that the Ni atoms reach the Si interface at a similar rate, i.e., without any orientation preference, so as to form a uniform layer of nickel silicide. The nickel silicide may be annealed to form a uniform crystalline nickel disilicide. Accordingly, a single crystal nickel silicide on (100) Si or on amorphous Si is achieved wherein the nickel silicide has improved stability and may be utilized in ultra-shallow junction devices.
摘要翻译：集成电路器件及其制造方法包括在（100）Si上的外延硅化镍，或者由钴中间层制造的在非晶Si上的稳定的硅化镍。在一个实施方案中，该方法包括在硅化反应之前在Ni和Si层之间沉积钴（Co）界面层。钴中间层通过由钴中间层与镍和硅的反应形成的钴/镍/硅合金层调节Ni原子的通量，使得Ni原子以相似的速率到达Si界面，即没有任何取向偏好，从而形成均匀的硅化镍层。可以将镍硅化物退火以形成均匀的结晶二硅化镍。因此，实现了（100）Si或非晶Si上的单晶硅化镍，其中硅化镍具有改进的稳定性并可用于超浅结结器件中。

4. 发明授权

US06534871B2 Device including an epitaxial nickel silicide on (100) Si or stable nickel silicide on amorphous Si and a method of fabricating the same 失效
公开(公告)号：US06534871B2
公开(公告)日：2003-03-18
申请号：US09855391
申请日：2001-05-14
申请人： Jer-shen Maa , Douglas J. Tweet , Yoshi Ono , Fengyan Zhang , Sheng Teng Hsu
发明人： Jer-shen Maa , Douglas J. Tweet , Yoshi Ono , Fengyan Zhang , Sheng Teng Hsu
IPC分类号： H01L2348
CPC分类号： H01L21/28518 , H01L29/456
摘要： An integrated circuit device, and a method of manufacturing the same, comprises an epitaxial nickel silicide on (100) Si, or a stable nickel silicide on amorphous Si, fabricated with a cobalt interlayer. In one embodiment the method comprises depositing a cobalt (Co) interface layer between the Ni and Si layers prior to the silicidation reaction. The cobalt interlayer regulates the flux of the Ni atoms through the cobalt/nickel/silicon alloy layer formed from the reaction of the cobalt interlayer with the nickel and the silicon so that the Ni atoms reach the Si interface at a similar rate, i.e., without any orientation preference, so as to form a uniform layer of nickel silicide. The nickel silicide may be annealed to form a uniform crystalline nickel disilicide. Accordingly, a single crystal nickel silicide on (100) Si or on amorphous Si is achieved wherein the nickel silicide has improved stability and may be utilized in ultra-shallow junction devices.

5. 发明授权

US08264081B2 Multilayered barrier metal thin-films 有权
标题翻译：多层阻隔金属薄膜
公开(公告)号：US08264081B2
公开(公告)日：2012-09-11
申请号：US11311546
申请日：2005-12-19
申请人： Wei Pan , Yoshi Ono , David R. Evans , Sheng Teng Hsu
发明人： Wei Pan , Yoshi Ono , David R. Evans , Sheng Teng Hsu
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L21/28562 , H01L21/76841 , H01L2221/1078
摘要： A multi-layered barrier metal thin film is deposited on a substrate by atomic layer chemical vapor deposition (ALCVD). The multi-layer film may comprise several different layers of a single chemical species, or several layers each of distinct or alternating chemical species. In a preferred embodiment, the multi-layer barrier thin film comprises a Tantalum Nitride layer on a substrate, with a Titanium Nitride layer deposited thereon. The thickness of the entire multi-layer film may be approximately fifty Angstroms. The film has superior film characteristics, such as anti-diffusion capability, low resistivity, high density, and step coverage, when compared to films deposited by conventional chemical vapor deposition (CVD). The multi-layered barrier metal thin film of the present invention has improved adhesion characteristics and is particularly suited for metallization of a Copper film thereon.
摘要翻译：通过原子层化学气相沉积（ALCVD）将多层阻挡金属薄膜沉积在衬底上。多层膜可以包括单个化学物质的几个不同层，或者各个不同的或交替的化学物质的几个层。在优选实施例中，多层阻挡薄膜包括在衬底上的氮化钽层，其上沉积有氮化钛层。整个多层膜的厚度可以是大约50埃。当与通过常规化学气相沉积（CVD）沉积的膜相比时，该膜具有优异的膜特性，例如抗扩散能力，低电阻率，高密度和台阶覆盖。本发明的多层阻挡金属薄膜具有改善的粘合特性，特别适用于其上的铜膜的金属化。

6. 发明授权

US07015138B2 Multi-layered barrier metal thin films for Cu interconnect by ALCVD 有权
公开(公告)号：US07015138B2
公开(公告)日：2006-03-21
申请号：US09819296
申请日：2001-03-27
申请人： Wei Pan , Yoshi Ono , David R. Evans , Sheng Teng Hsu
发明人： Wei Pan , Yoshi Ono , David R. Evans , Sheng Teng Hsu
IPC分类号： H01L21/44
CPC分类号： H01L21/28562 , H01L21/76841 , H01L2221/1078
摘要： A multi-layered barrier metal thin film is deposited on a substrate by atomic layer chemical vapor deposition (ALCVD). The multi-layer film may comprise several different layers of a single chemical species, or several layers each of distinct or alternating chemical species. In a preferred embodiment, the multi-layer barrier thin film comprises a Tantalum Nitride layer on a substrate, with a Titanium Nitride layer deposited thereon. The thickness of the entire multi-layer film may be approximately fifty Angstroms. The film has superior film characteristics, such as anti-diffusion capability, low resistivity, high density, and step coverage, when compared to films deposited by conventional chemical vapor deposition (CVD). The multi-layered barrier metal thin film of the present invention has improved adhesion characteristics and is particularly suited for metallization of a Copper film thereon.

7. 发明授权

US06573134B2 Dual metal gate CMOS devices and method for making the same 失效
公开(公告)号：US06573134B2
公开(公告)日：2003-06-03
申请号：US09817834
申请日：2001-03-27
申请人： Yanjun Ma , Yoshi Ono , David R. Evans , Sheng Teng Hsu
发明人： Yanjun Ma , Yoshi Ono , David R. Evans , Sheng Teng Hsu
IPC分类号： H01L218238
CPC分类号： H01L21/823842 , H01L27/092
摘要： A method of fabricating a dual metal gate CMOS includes forming a gate oxide in a gate region and depositing a place-holder gate in each of a n-well and p-well; removing the place-holder gate and gate oxide; depositing a high-k dielectric in the gate region; depositing a first metal in the gate region of the p-well; depositing a second metal in the gate region of each of the n-well and p-well; and insulating and metallizing the structure. A dual metal gate CMOS of the invention includes PMOS transistor and a NMOS transistor. In the NMOS, a gate includes a high-k cup, a first metal cup formed in the high-k cup, and a second metal gate formed in the first metal cup. In the PMOS, a gate includes a high-k cup and a second metal gate formed in the high-k cup.

8. 发明授权

US06200866B1 Use of silicon germanium and other alloys as the replacement gate for the fabrication of MOSFET 有权
标题翻译：使用硅锗等合金作为制造MOSFET的替代栅极
公开(公告)号：US06200866B1
公开(公告)日：2001-03-13
申请号：US09410346
申请日：1999-09-30
申请人： Yanjun Ma , Douglas J. Tweet , David R. Evans , Yoshi Ono
发明人： Yanjun Ma , Douglas J. Tweet , David R. Evans , Yoshi Ono
IPC分类号： H01L21338
CPC分类号： H01L21/31053 , H01L21/2807 , H01L21/28194 , H01L21/28202 , H01L21/76801 , H01L21/76804 , H01L21/76834 , H01L29/41733 , H01L29/41775 , H01L29/41783 , H01L29/4908 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66545 , H01L29/66575 , H01L29/66772 , H01L29/78684
摘要： A method of fabricating a MOSFET is provided, including: depositing an oxide layer on a silicon substrate for device isolation; forming a silicon based alloy island above a gate region in the substrate, wherein the silicon based alloy comprises a silicon germanium alloy or a silicon tin alloy or another alloy of Group IV-B elements; building a sidewall about the silicon based alloy island; forming a source region and a drain region in the substrate; removing the silicon based alloy island, thereby leaving a void over the gate region; filing the void and the areas over the source region and the drain region; and planarizing the upper surface of the structure by chemical mechanical polishing. Alternative embodiments providing conventional and raised source/drain structures are disclosed.
摘要翻译：提供一种制造MOSFET的方法，包括：在硅衬底上沉积氧化层用于器件隔离; 在所述基板的栅极区域的上方形成硅基合金岛，其中所述硅基合金包含硅锗合金或硅锡合金或第IV-B族元素的另一种合金; 围绕硅基合金岛构建侧壁; 在衬底中形成源区和漏区; 去除硅基合金岛，从而在栅极区域上留下空隙; 填充空隙和源区域和漏区域上的区域; 并通过化学机械抛光对结构的上表面进行平面化。公开了提供常规和凸起的源极/漏极结构的替代实施例。

9. 发明授权

US07811837B2 Terbium-doped, silicon-rich oxide electroluminescent devices and method of making the same 有权
标题翻译：铽掺杂，富硅氧化物电致发光器件及其制造方法
公开(公告)号：US07811837B2
公开(公告)日：2010-10-12
申请号：US11582275
申请日：2006-10-16
申请人： Tingkai Li , Wei Gao , Yoshi Ono , Sheng Teng Hsu
发明人： Tingkai Li , Wei Gao , Yoshi Ono , Sheng Teng Hsu
IPC分类号： H01L29/00
CPC分类号： H01L27/15 , H01L33/0004 , H01L33/343
摘要： A method of fabricating an electroluminescent device includes, on a prepared substrate, depositing a rare earth-doped silicon-rich layer on gate oxide layer as a light emitting layer; and annealing and oxidizing the structure to repair any damage caused to the rare earth-doped silicon-rich layer; and incorporating the electroluminescent device into a CMOS IC. An electroluminescent device fabricated according to the method of the invention includes a substrate, a rare earth-doped silicon-rich layer formed on the gate oxide layer for emitting a light of a pre-determined wavelength; a top electrode formed on the rare earth-doped silicon-rich layer; and associated CMOS IC structures fabricated thereabout.
摘要翻译：一种制造电致发光器件的方法包括：在制备的衬底上，在作为发光层的栅极氧化物层上沉积稀土掺杂的富硅层; 并对该结构进行退火和氧化以修复对稀土掺杂的富硅层造成的任何损伤; 并将电致发光器件并入CMOS IC。根据本发明的方法制造的电致发光器件包括：衬底，形成在栅极氧化物层上的用于发射预定波长的光的稀土掺杂富硅层; 在稀土掺杂的富硅层上形成的顶部电极; 并在其附近制造相关的CMOS IC结构。

10. 发明授权

US07462499B2 Carbon nanotube with ZnO asperities 失效
标题翻译：具有ZnO粗糙度的碳纳米管
公开(公告)号：US07462499B2
公开(公告)日：2008-12-09
申请号：US11262439
申请日：2005-10-28
申请人： John F. Conley, Jr. , Yoshi Ono , Lisa H. Stecker , Sheng Teng Hsu , Josh M. Green , Lifeng Dong , Jun Jiao
发明人： John F. Conley, Jr. , Yoshi Ono , Lisa H. Stecker , Sheng Teng Hsu , Josh M. Green , Lifeng Dong , Jun Jiao
IPC分类号： H01L21/00
CPC分类号： H01J9/025 , B82Y10/00 , B82Y30/00 , B82Y40/00 , C01B32/162 , C01B32/168 , C01B2202/34 , C01B2202/36 , H01J1/304 , H01J2201/30469 , H01L21/0237 , H01L21/02381 , H01L21/02444 , H01L21/02472 , H01L21/02483 , H01L21/02513 , H01L21/02554 , H01L21/02601 , Y10S977/754
摘要： A ZnO asperity-covered carbon nanotube (CNT) device has been provided, along with a corresponding fabrication method. The method comprises: forming a substrate; growing CNTs from the substrate; conformally coating the CNTs with ZnO; annealing the ZnO-coated CNTs; and, forming ZnO asperities on the surface of the CNTs in response to the annealing. In one aspect, the ZnO asperities have a density in the range of about 100 to 1000 ZnO asperities per CNT. The density is dependent upon the deposited ZnO film thickness and annealing parameters. The CNTs are conformally coating with ZnO using a sputtering, chemical vapor deposition (CVD), spin-on, or atomic layer deposition (ALD). For example, an ALD process can be to deposit a layer of ZnO over the CNTs having a thickness in the range of 1.2 to 200 nanometers (nm).
摘要翻译：已经提供了ZnO微粒覆盖碳纳米管（CNT）器件，以及相应的制造方法。该方法包括：形成衬底; 从底物生长CNT; 用ZnO共形涂覆CNT; 退火ZnO涂层的CNT; 并且响应于退火在CNT的表面上形成ZnO粗糙度。在一个方面，ZnO粗糙度的密度在每个CNT约100-1000nm的ZnO粗糙度的范围内。密度取决于沉积的ZnO膜厚度和退火参数。使用溅射，化学气相沉积（CVD），旋涂或原子层沉积（ALD），使用ZnO共形涂覆CNT。例如，ALD工艺可以在厚度在1.2至200纳米（nm）范围内的CNT上沉积ZnO层。

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