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1. 发明授权

US09105317B2 Memory system capable of calibrating output voltage level of semiconductor memory device and method of calibrating output voltage level of semiconductor memory device 有权
标题翻译：能够校准半导体存储器件的输出电压电平的存储器系统和校准半导体存储器件的输出电压电平的方法
公开(公告)号：US09105317B2
公开(公告)日：2015-08-11
申请号：US13611867
申请日：2012-09-12
申请人： Yoon-Joo Eom , Young-Jin Jeon , Yong-Cheol Bae , Young-Chul Cho
发明人： Yoon-Joo Eom , Young-Jin Jeon , Yong-Cheol Bae , Young-Chul Cho
IPC分类号： H03K19/003 , G11C7/10 , H03K19/00 , G11C29/02
CPC分类号： G11C7/1057 , G11C29/021 , G11C29/028 , G11C2207/2254 , H03K19/0005
摘要： Provided are a semiconductor memory device and a memory system including the same, which may calibrate a level of an output voltage in consideration of channel environment and a mismatch in on-die termination (ODT) resistance of a memory controller. The memory system includes a memory controller and a semiconductor memory device. The semiconductor memory device is configured to generate a reference voltage based on driving information of the memory controller, and calibrate an output voltage level based on a reference voltage when the semiconductor memory device is electrically connected to the memory controller.
摘要翻译：提供了一种半导体存储器件和包括该半导体存储器件的存储器系统，其可以考虑到沟道环境和存储器控制器的管芯端接（ODT）电阻的不匹配来校准输出电压的电平。存储器系统包括存储器控制器和半导体存储器件。半导体存储器件被配置为基于存储器控制器的驱动信息生成参考电压，并且当半导体存储器件电连接到存储器控制器时，基于参考电压校准输出电压电平。

2. 发明授权

US09076510B2 Power mixing circuit and semiconductor memory device including the same 有权
标题翻译：功率混合电路和包括其的半导体存储器件
公开(公告)号：US09076510B2
公开(公告)日：2015-07-07
申请号：US13619793
申请日：2012-09-14
申请人： Young-Chul Cho , Young-Jin Jeon , Yong-Cheol Bae
发明人： Young-Chul Cho , Young-Jin Jeon , Yong-Cheol Bae
IPC分类号： G11C5/14 , G11C7/02 , G11C7/10 , G11C7/20 , G11C5/04
CPC分类号： G11C5/147 , G11C5/04 , G11C5/148 , G11C7/02 , G11C7/1012 , G11C7/1057 , G11C7/20
摘要： A power mixing circuit capable of maintaining a stable output voltage in a deep-power-down mode is provided. The power mixing circuit includes an input buffer, a power mixing control circuit, a power mixing driver and an output buffer. The input buffer is configured to operate using a first supply voltage, and to generate a first voltage signal in response to an input signal. The power mixing control circuit is configured to generate a power mixing control signal based on a power-up signal and a deep-power-down mode signal. The power mixing driver is configured to operate using an external supply voltage and a second supply voltage, to perform power mixing on the external supply voltage and the second supply voltage, and to generate a second voltage signal. The output buffer is configured to operate using the second supply voltage, and to generate an output signal.
摘要翻译：提供了能够在深度掉电模式下保持稳定的输出电压的功率混合电路。功率混合电路包括输入缓冲器，功率混合控制电路，功率混合驱动器和输出缓冲器。输入缓冲器被配置为使用第一电源电压进行操作，并且响应于输入信号产生第一电压信号。功率混合控制电路被配置为基于上电信号和深度掉电模式信号来产生功率混合控制信号。功率混合驱动器被配置为使用外部电源电压和第二电源电压进行操作，以对外部电源电压和第二电源电压进行功率混合，并产生第二电压信号。输出缓冲器被配置为使用第二电源电压进行操作，并且产生输出信号。

3. 发明申请

US20130201765A1 POWER MIXING CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 有权
标题翻译：功率混合电路和包括其的半导体存储器件
公开(公告)号：US20130201765A1
公开(公告)日：2013-08-08
申请号：US13619793
申请日：2012-09-14
申请人： Young-Chul Cho , Young-Jin Jeon , Yong-Cheol Bae
发明人： Young-Chul Cho , Young-Jin Jeon , Yong-Cheol Bae
IPC分类号： G11C5/14 , G11C7/10 , G06G7/12
CPC分类号： G11C5/147 , G11C5/04 , G11C5/148 , G11C7/02 , G11C7/1012 , G11C7/1057 , G11C7/20
摘要： A power mixing circuit capable of maintaining a stable output voltage in a deep-power- down mode is provided. The power mixing circuit includes an input buffer, a power mixing control circuit, a power mixing driver and an output buffer. The input buffer is configured to operate using a first supply voltage, and to generate a first voltage signal in response to an input signal. The power mixing control circuit is configured to generate a power mixing control signal based on a power-up signal and a deep-power-down mode signal. The power mixing driver is configured to operate using an external supply voltage and a second supply voltage, to perform power mixing on the external supply voltage and the second supply voltage, and to generate a second voltage signal. The output buffer is configured to operate using the second supply voltage, and to generate an output signal.
摘要翻译：提供了能够在深度断电模式下保持稳定的输出电压的功率混合电路。功率混合电路包括输入缓冲器，功率混合控制电路，功率混合驱动器和输出缓冲器。输入缓冲器被配置为使用第一电源电压进行操作，并且响应于输入信号产生第一电压信号。功率混合控制电路被配置为基于上电信号和深度掉电模式信号来产生功率混合控制信号。功率混合驱动器被配置为使用外部电源电压和第二电源电压进行操作，以对外部电源电压和第二电源电压进行功率混合，并产生第二电压信号。输出缓冲器被配置为使用第二电源电压进行操作，并且产生输出信号。

4. 发明授权

US06487132B2 Integrated circuit memory devices having multiple input/output buses and precharge circuitry for precharging the input/output buses between write operations 有权
标题翻译：具有多个输入/输出总线和预充电电路的集成电路存储器件，用于在写入操作之间预充电输入/输出总线
公开(公告)号：US06487132B2
公开(公告)日：2002-11-26
申请号：US09773780
申请日：2001-01-31
申请人： Yong-Cheol Bae , Jung-Hwa Lee
发明人： Yong-Cheol Bae , Jung-Hwa Lee
IPC分类号： G11C700
CPC分类号： G11C7/1006 , G11C7/1048
摘要： Integrated circuit memory devices include precharge controller circuit, which generates a precharge control signal in response to completion of a write operation on a first input/output bus. A precharge circuit drives the first and a input/output buses to a predetermined voltage level in response to the precharge control signal. Multiple switches may be used to couple the first and second input/output buses to the memory cell array and these switches may also be coupled to a column select line. The switches may be responsive to a column select signal carried on the column select line such that one or more memory cells are coupled to the first input/output bus and one or more memory cells are coupled to the second input/output bus simultaneously. Because both of the input/output buses are coupled to the memory cell array in response to the column select signal, the memory cell array may be susceptible to bit line disturbance in which charges remaining on one input/output bus from a previous write operation corrupt memory cells during a write operation on a second input/output bus. By driving the first and second input/output buses to a predetermined voltage level after completing a write operation on one of the two input/output buses, bit line disturbance may be prevented.
摘要翻译：集成电路存储器件包括预充电控制器电路，其响应于在第一输入/输出总线上的写入操作的完成而产生预充电控制信号。预充电电路响应于预充电控制信号将第一输入/输出总线驱动到预定的电压电平。可以使用多个开关将第一和第二输入/输出总线耦合到存储单元阵列，并且这些开关也可以耦合到列选择线。开关可以响应于列选择线上承载的列选择信号，使得一个或多个存储器单元耦合到第一输入/输出总线，并且一个或多个存储器单元同时耦合到第二输入/输出总线。因为响应于列选择信号而将输入/输出总线都耦合到存储单元阵列，所以存储单元阵列可能容易受到位线干扰，其中一个输入/输出总线上剩余的电荷从先前的写操作损坏在第二输入/输出总线上的写操作期间的存储器单元。通过在两个输入/输出总线中的一个完成写入操作之后，通过将第一和第二输入/输出总线驱动到预定的电压电平，可以防止位线干扰。

5. 发明授权

US5781494A Voltage pumping circuit for semiconductor memory device 失效
标题翻译：半导体存储器件的电压泵浦电路
公开(公告)号：US5781494A
公开(公告)日：1998-07-14
申请号：US782896
申请日：1996-12-27
申请人： Yong-Cheol Bae , Sei-Seung Yoon , Dong-Il Seo
发明人： Yong-Cheol Bae , Sei-Seung Yoon , Dong-Il Seo
IPC分类号： G11C11/413 , G11C5/14 , G11C11/401 , G11C11/407 , H01L21/8242 , H01L27/108 , G11C8/00
CPC分类号： G11C5/145
摘要： A semiconductor memory device comprising a memory cell array including at least two banks and a desired number of voltage pumping circuits each for pumping an input voltage to a desired level. The voltage pumping circuits are driven in response to at least two bank selection control signals. The voltage pumping circuits are arranged in the semiconductor memory device in a proper manner to efficiently perform the voltage pumping operation, so as to increase the pumping efficiency. Further, the proper arrangement of the voltage pumping circuits contributes to the integration of the semiconductor memory device.
摘要翻译：一种半导体存储器件，包括存储单元阵列，该存储单元阵列包括至少两个存储体和所需数量的电压泵浦电路，每个用于将输入电压泵送到期望的电平。电压泵浦电路响应于至少两个存储体选择控制信号被驱动。电压泵浦电路以适当的方式布置在半导体存储器件中，以有效地执行电压泵送操作，从而提高泵送效率。此外，电压泵浦电路的适当布置有助于半导体存储器件的集成。

6. 发明授权

US6087891A Integrated power supply voltage generators having reduced susceptibility to parasitic latch-up during set-up mode operation 有权
标题翻译：集成电源电压发生器在安装模式操作期间具有降低的寄生闩锁敏感性
公开(公告)号：US6087891A
公开(公告)日：2000-07-11
申请号：US160073
申请日：1998-09-24
申请人： Sei-Seung Yoon , Yong-Cheol Bae
发明人： Sei-Seung Yoon , Yong-Cheol Bae
IPC分类号： G11C11/413 , G05F1/46 , G11C11/407 , G05F1/10
CPC分类号： G05F1/465
摘要： Integrated power supply voltage generators include a boosted voltage generator which generates a boosted voltage signal (Vpp) at a first level on a boosted voltage signal line during a set-up time interval, in response to an internal power supply voltage signal (VINTA*), and a circuit which is responsive to a first reference voltage (VREFA) and the boosted voltage signal (Vpp) and generates the internal power supply voltage signal (VINTA*) at a second level which is less than the first level throughout the set-up time interval.
摘要翻译：集成电源电压发生器包括升压电压发生器，其响应于内部电源电压信号（VINTA *），在建立时间间隔期间在升压电压信号线上产生在第一电平上的升压电压信号（Vpp），以及响应于第一参考电压（VREFA）和升压电压信号（Vpp）的电路，并且在整个设定值小于第一电平的第二电平处产生内部电源电压信号（VINTA *），上班时间间隔。

7. 发明授权

US08928349B2 On-die termination circuit, semiconductor memory device and memory system 有权
标题翻译：片上终端电路，半导体存储器件和存储器系统
公开(公告)号：US08928349B2
公开(公告)日：2015-01-06
申请号：US13755418
申请日：2013-01-31
申请人： Ki-Seok Oh , Joon-Young Park , Yong-Hun Ahn , Yong-Cheol Bae , Yong-Gwon Jeong , Jong-Hyun Choi
发明人： Ki-Seok Oh , Joon-Young Park , Yong-Hun Ahn , Yong-Cheol Bae , Yong-Gwon Jeong , Jong-Hyun Choi
IPC分类号： H03K17/16 , H03K19/003 , H03K19/0175 , H04L25/02 , G11C7/10
CPC分类号： H03K19/017545 , G11C7/1057 , G11C2207/2272 , H03K19/0175 , H04L25/0264
摘要： An ODT circuit is activated/deactivated in response to a latency control signal or a clock enable signal. The ODT circuit includes an ODT control circuit and an ODT section. The ODT control circuit determines an ODT status based on a read latency control signal (RL) and/or a write latency control signal (WL) to generate an ODT control signal. The ODT section is activated/deactivated in response to the ODT control signal.
摘要翻译：响应延迟控制信号或时钟使能信号，ODT电路被激活/去激活。 ODT电路包括ODT控制电路和ODT部分。 ODT控制电路基于读等待时间控制信号（RL）和/或写等待时间控制信号（WL）来确定ODT状态，以产生ODT控制信号。响应于ODT控制信号，ODT部分被激活/去激活。

8. 发明授权

US06184078B2 Method for fabricating a capacitor for a dynamic random access memory cell 有权
标题翻译：制造用于动态随机存取存储单元的电容器的方法
公开(公告)号：US06184078B2
公开(公告)日：2001-02-06
申请号：US09170086
申请日：1998-10-13
申请人： Sei-Seung Yoon , Yong-Cheol Bae
发明人： Sei-Seung Yoon , Yong-Cheol Bae
IPC分类号： H01L218242
CPC分类号： H01L27/10855 , H01L27/10814
摘要： A method for fabricating a DRAM cell capacitor is applicable to a high density dynamic random access memory (DRAM) device on a semiconductor substrate wherein a storage node is formed on a buried contact pad in self-alignment. The method comprises forming a second insulator layer on the first insulator layer including the buried contact pad. An etching stopper layer is next formed on the second insulator layer. Sequentially, a third insulator layer and a first polysilicon layer are formed on the etching stopper layer. A masking layer is formed on the first polysilicon layer to define a storage node. The first polysilicon layer and the third insulator layer are sequentially etched using the masking layer until the etching stopper layer is exposed, so as to form a top via hole. A sidewall spacer is formed on both sidewalls of the top via hole. After removal of the masking layer, the etching stopper layer and the second insulator layer are sequentially etched using a combination of the first polysilicon layer and the sidewall spacer as a mask until the contact pad is exposed, so as to form a bottom via hole beneath the top via hole. A second polysilicon layer is deposited filling up the bottom and top via holes. The semiconductor substrate is planarized by CMP procedure until the third insulator layer is exposed. Finally, the third insulator layer is etched to form the cylindrical storage node having the sidewall spacer and the second polysilicon layer in self-alignment.
摘要翻译：一种用于制造DRAM单元电容器的方法可应用于半导体衬底上的高密度动态随机存取存储器（DRAM）器件，其中存储节点以自对准方式形成在埋地接触焊盘上。该方法包括在包括埋入接触垫的第一绝缘体层上形成第二绝缘体层。接着在第二绝缘体层上形成蚀刻阻挡层。接着，在蚀刻阻挡层上形成第三绝缘体层和第一多晶硅层。在第一多晶硅层上形成掩模层以限定存储节点。使用掩模层依次蚀刻第一多晶硅层和第三绝缘体层，直到蚀刻停止层露出为止，形成顶部通孔。侧壁间隔件形成在顶部通孔的两个侧壁上。在去除掩模层之后，使用第一多晶硅层和侧壁间隔物的组合作为掩模，依次蚀刻蚀刻停止层和第二绝缘体层，直到接触焊盘露出，以便在下面形成底部通孔顶部通孔。沉积第二多晶硅层，填充底部和顶部通孔。半导体衬底通过CMP工艺平坦化，直到暴露第三绝缘体层。最后，蚀刻第三绝缘体层以形成具有侧壁间隔物和第二多晶硅层自对准的圆柱形存储节点。

9. 发明授权

US6079023A Multi-bank memory devices having common standby voltage generator for powering a plurality of memory array banks in response to memory array bank enable signals 有权
标题翻译：具有用于响应于存储器阵列组使能信号为多个存储器阵列组供电的共同备用电压发生器的多存储体存储器件
公开(公告)号：US6079023A
公开(公告)日：2000-06-20
申请号：US222853
申请日：1998-12-30
申请人： Sei-Seung Yoon , Yong-Cheol Bae
发明人： Sei-Seung Yoon , Yong-Cheol Bae
IPC分类号： G11C11/413 , G11C5/14 , G11C8/12 , G11C11/401 , G11C11/407 , G11C11/4193 , G06F1/30
CPC分类号： G11C8/12 , G11C5/14
摘要： A semiconductor memory device having a plurality of memory array banks, a plurality of active array voltage generators, a standby array voltage generator and a plurality of switching means is provided. The semiconductor memory device includes a plurality of memory array banks in which information is stored, a plurality of active array voltage generators connected to the memory array banks, for generating predetermined active voltages in response to memory array bank enable signals for activating the memory array banks, a standby array voltage generator for generating a predetermined standby voltage so that the memory array banks are maintained in a standby state for operation, and a plurality of switching means connected between the memory array banks and the standby array voltage generator, for disconnecting the output of the standby array voltage generator from memory array banks in response to memory array bank enable signals for activating the memory array banks. The power consumption of the semiconductor memory device is reduced.
摘要翻译：提供具有多个存储器阵列组，多个有源阵列电压发生器，备用阵列电压发生器和多个开关装置的半导体存储器件。半导体存储器件包括存储有信息的多个存储器阵列组，连接到存储器阵列组的多个有源阵列电压发生器，用于响应用于激活存储器阵列组的存储器阵列组使能信号而产生预定有效电压备用阵列电压发生器，用于产生预定的待机电压，使得存储器阵列组保持在待机状态以用于操作;以及多个开关装置，连接在存储器阵列组和备用阵列电压发生器之间，用于断开输出响应于用于激活存储器阵列组的存储器阵列组使能信号，来自存储器阵列组的备用阵列电压发生器。半导体存储器件的功耗降低。

10. 发明授权

US5796293A Voltage boosting circuits having backup voltage boosting capability 失效
标题翻译：具有备用升压能力的升压电路
公开(公告)号：US5796293A
公开(公告)日：1998-08-18
申请号：US748189
申请日：1996-11-12
申请人： Sei-Seung Yoon , Yong-Cheol Bae
发明人： Sei-Seung Yoon , Yong-Cheol Bae
IPC分类号： G11C11/413 , G11C5/14 , G11C8/08 , G11C11/407 , H01L21/8242 , H01L27/108 , H02M3/07 , G05F1/10
CPC分类号： G11C5/145 , G11C8/08
摘要： Voltage boosting circuits include backup voltage boosting circuits which are enabled during high current loading conditions when voltage sags in the potential of a boosted signal line(s) are encountered, and which provide independent level detection capability to bypass main voltage level detectors when relatively severe voltage sags are anticipated. In particular, voltage boosting circuits are provided which contain a main voltage boosting circuit and a backup voltage boosting circuit therein. The main voltage boosting circuit is typically powered at a first reference potential (e.g., Vcc) and preferably contains a main level detector, a built-in oscillator and a main pump coupled in series to drive a signal line (e.g., Vpp) to a boosted reference potential which is greater than the first reference potential, if a potential of the signal line drops below a second reference potential. To supplement the voltage boosting capability of the main pump, a backup voltage boosting circuit is provided containing an independent voltage level detector and at least one backup pump coupled in series therewith, to drive the signal line to the boosted reference potential, if the potential of the signal line drops below a third reference potential which may be greater than or equal to the second reference potential. Accordingly, the occurrence of relatively small voltage sags in the potential of the boosted signal line (e.g., Vpp) can trigger the backup pump during anticipated high current loading conditions, while the occurrence of larger voltage sags in the potential can trigger the main pump to assist the backup pump.
摘要翻译：升压电路包括备用升压电路，其在高电流负载状态期间能够在遇到升压信号线的电位的电压骤降时使能，并且当相对严重的电压时提供独立的电平检测能力来旁路主电压电平检测器预计会下滑。特别地，提供了在其中包含主升压电路和备用升压电路的升压电路。主升压电路通常以第一参考电位（例如，Vcc）供电，并且优选地包含主电平检测器，内置振荡器和串联耦合的主泵，以将信号线（例如Vpp）驱动到如果信号线的电位低于第二参考电位，则升高参考电位大于第一参考电位。为了补充主泵的升压能力，提供备用升压电路，其包含独立的电压电平检测器和与串联耦合的至少一个备用泵，以将信号线驱动到升压的参考电位，如果电压信号线下降到可能大于或等于第二参考电位的第三参考电位以下。因此，在预期的高电流负载条件期间，升压信号线的电位（例如，Vpp）中的相对小的电压下降的发生可以触发备用泵，而在电位中较大的电压下降的发生可以触发主泵协助备用泵。

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