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1. 发明授权

US08605536B2 Power-on-reset (POR) circuits for resetting memory devices, and related circuits, systems, and methods 失效
标题翻译：用于复位存储器件的上电复位（POR）电路，以及相关电路，系统和方法
公开(公告)号：US08605536B2
公开(公告)日：2013-12-10
申请号：US13460862
申请日：2012-05-01
申请人： Esin Terzioglu , Balachander Ganesan , Alex Dongkyu Park , Sei Seung Yoon
发明人： Esin Terzioglu , Balachander Ganesan , Alex Dongkyu Park , Sei Seung Yoon
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C7/20
摘要： Power-on-reset (POR) circuits for resetting memory devices, and related circuits, systems, and methods are disclosed. In one embodiment, a POR circuit is provided. The POR circuit is configured to receive as input, a plurality of decoded address outputs from at least one memory decoding device. The POR circuit is further configured to generate a POR reset if any of the plurality of decoded address outputs are active. As a result, memory decoding device latches can be reset to a known, default condition to avoid causing an unintentional word line selection in the memory during power-on state before an external reset is available. Because the POR circuit can generate the POR reset without need of an external reset, the memory decoding devices can be reset quickly to allow for quicker availability of memory after a power-on condition.
摘要翻译：公开了用于重置存储器件的上电复位（POR）电路以及相关电路，系统和方法。在一个实施例中，提供了一个POR电路。 POR电路被配置为从至少一个存储器解码装置接收多个解码的地址输出作为输入。 POR电路还被配置为如果多个解码的地址输出中的任一个是有效的，则产生POR复位。结果，存储器解码装置锁存器可以被重置为已知的默认条件，以避免在外部复位可用之前在上电状态期间在存储器中引起无意的字线选择。由于POR电路可以在不需要外部复位的情况下生成POR复位，所以可以快速复位存储器解码器件，以便在上电状态后可以更快地提供存储器的可用性。

2. 发明授权

US08498169B2 Code-based differential charging of bit lines of a sense amplifier 有权
标题翻译：读出放大器的位线的基于码的差分充电
公开(公告)号：US08498169B2
公开(公告)日：2013-07-30
申请号：US13224562
申请日：2011-09-02
申请人： Hari M. Rao , Esin Terzioglu , Sei Seung Yoon
发明人： Hari M. Rao , Esin Terzioglu , Sei Seung Yoon
IPC分类号： G11C29/00 , G11C16/28
CPC分类号： G11C16/28 , G11C11/41 , G11C29/026 , G11C29/028 , G11C2029/1204
摘要： A circuit includes a plurality of capacitors responsive to a plurality of latches that store a test code. A first bit line is coupled to a bit cell and coupled to a sense amplifier. A second bit line is coupled to the bit cell and coupled to the sense amplifier. A differential charge from a set of the plurality of capacitors is applied to the first bit line and to the second bit line. The set of the plurality of capacitors is determined based on the test code and the test code is independent of an output of the sense amplifier.
摘要翻译：电路包括响应于存储测试码的多个锁存器的多个电容器。第一位线耦合到位单元并耦合到读出放大器。第二位线耦合到位单元并耦合到读出放大器。来自一组多个电容器的差分电荷被施加到第一位线和第二位线。基于测试代码确定多个电容器的集合，并且测试代码独立于读出放大器的输出。

3. 发明授权

US08438433B2 Registers with full scan capability 失效
标题翻译：注册全扫描功能
公开(公告)号：US08438433B2
公开(公告)日：2013-05-07
申请号：US12886620
申请日：2010-09-21
申请人： Hari M. Rao , Sei Seung Yoon , Nan Chen
发明人： Hari M. Rao , Sei Seung Yoon , Nan Chen
IPC分类号： G11C29/00
CPC分类号： G01R31/318541 , G11C11/417 , G11C29/32
摘要： A scan test of a first latch and a second latch couples a given scan value to the input of the first latch, to switch the first latch to a state corresponding to the scan value, uncouples the scan value from the first latch to latch the first latch at that state, couples the output of the first latch while latched at that state to the input of the second latch to switch the second latch to that state, and uncoupling the output of the first latch from the input of the second latch to latch the second latch at that state.
摘要翻译：第一锁存器和第二锁存器的扫描测试将给定扫描值耦合到第一锁存器的输入，以将第一锁存器切换到与扫描值对应的状态，将扫描值从第一锁存器解耦合以锁定第一锁存器在该状态下锁存，将锁定在该状态的第一锁存器的输出耦合到第二锁存器的输入端，以将第二锁存器切换到该状态，并且将第一锁存器的输出与第二锁存器的输入端分离在该状态下的第二个闩锁。

4. 发明授权

US08228714B2 Memory device for resistance-based memory applications 有权
标题翻译：用于基于电阻的存储器应用的存储器件
公开(公告)号：US08228714B2
公开(公告)日：2012-07-24
申请号：US12206933
申请日：2008-09-09
申请人： Anosh B. Davierwalla , Cheng Zhong , Dongkyu Park , Mohamed Hassan Abu-Rahma , Mehdi Hamidi Sani , Sei Seung Yoon
发明人： Anosh B. Davierwalla , Cheng Zhong , Dongkyu Park , Mohamed Hassan Abu-Rahma , Mehdi Hamidi Sani , Sei Seung Yoon
IPC分类号： G11C11/00
CPC分类号： G11C11/1673
摘要： In a particular embodiment, a memory device is disclosed that includes a memory cell including a resistance-based memory element coupled to an access transistor. The access transistor has a first oxide thickness to enable operation of the memory cell at an operating voltage. The memory device also includes a first amplifier configured to couple the memory cell to a supply voltage that is greater than a voltage limit to generate a data signal based on a current through the memory cell. The first amplifier includes a clamp transistor that has a second oxide thickness that is greater than the first oxide thickness. The clamp transistor is configured to prevent the operating voltage at the memory cell from exceeding the voltage limit.
摘要翻译：在特定实施例中，公开了一种存储器件，其包括存储单元，该存储单元包括耦合到存取晶体管的基于电阻的存储元件。存取晶体管具有第一氧化物厚度，以使得能够在工作电压下操作存储单元。存储器件还包括第一放大器，其被配置为将存储器单元耦合到大于电压限制的电源电压，以基于通过存储器单元的电流来产生数据信号。第一放大器包括具有大于第一氧化物厚度的第二氧化物厚度的钳位晶体管。钳位晶体管被配置为防止存储器单元处的工作电压超过电压限制。

5. 发明授权

US08130535B2 Flexible word-line pulsing for STT-MRAM 有权
标题翻译：灵活的字线脉冲STT-MRAM
公开(公告)号：US08130535B2
公开(公告)日：2012-03-06
申请号：US12551874
申请日：2009-09-01
申请人： Hari M. Rao , Sei Seung Yoon , Medhi Sani , Seung Duk Lee , Sung Cho
发明人： Hari M. Rao , Sei Seung Yoon , Medhi Sani , Seung Duk Lee , Sung Cho
IPC分类号： G11C11/00
CPC分类号： G11C29/56 , G11C29/12015 , G11C29/56012
摘要： A method for generating a variable pulse width signal on an integrated circuit (IC) chip, includes receiving a first clock signal on the IC chip and receiving a second clock signal on the IC chip having a variable delay relative to the first clock signal. A signal having a rising edge triggered by a rising edge of the first clock signal and a falling edge triggered by a rising edge of the second clock signal is output. The output signal is provided to circuitry on the chip, such as a magnetoresistive junction (MTJ) cell of a spin torque transfer magnetic random access memory (STT-MRAM).
摘要翻译：一种用于在集成电路（IC）芯片上产生可变脉冲宽度信号的方法，包括在IC芯片上接收第一时钟信号，并且在IC芯片上接收相对于第一时钟信号具有可变延迟的第二时钟信号。输出具有由第一时钟信号的上升沿触发的上升沿和由第二时钟信号的上升沿触发的下降沿的信号。输出信号被提供给芯片上的电路，例如自旋扭矩传递磁随机存取存储器（STT-MRAM）的磁阻结（MTJ）单元。

6. 发明授权

US08130534B2 System and method to read and write data a magnetic tunnel junction element 有权
标题翻译：在磁性隧道结元件上读取和写入数据的系统和方法
公开(公告)号：US08130534B2
公开(公告)日：2012-03-06
申请号：US12350304
申请日：2009-01-08
申请人： Mohamed Hassan Abu-Rahma , Seung-Chul Song , Sei Seung Yoon , Dongkyu Park , Cheng Zhong , Anosh B. Davierwalla
发明人： Mohamed Hassan Abu-Rahma , Seung-Chul Song , Sei Seung Yoon , Dongkyu Park , Cheng Zhong , Anosh B. Davierwalla
IPC分类号： G11C11/00
CPC分类号： G11C11/1675 , G11C11/1657 , G11C11/1659 , G11C11/1673
摘要： A system and method to read and write data in magnetic random access memories are disclosed. In a particular embodiment, a device includes a spin transfer torque magnetic tunnel junction (STT-MTJ) element and a transistor with a first gate and a second gate coupled to the STT-MTJ element.
摘要翻译：公开了一种在磁随机存取存储器中读取和写入数据的系统和方法。在特定实施例中，器件包括自旋转移转矩磁隧道结（STT-MTJ）元件和具有耦合到STT-MTJ元件的第一栅极和第二栅极的晶体管。

7. 发明授权

US08027206B2 Bit line voltage control in spin transfer torque magnetoresistive random access memory 有权
标题翻译：自旋传输转矩磁阻随机存取存储器中的位线电压控制
公开(公告)号：US08027206B2
公开(公告)日：2011-09-27
申请号：US12362500
申请日：2009-01-30
申请人： Sei Seung Yoon , Seung H. Kang
发明人： Sei Seung Yoon , Seung H. Kang
IPC分类号： G11C7/10
CPC分类号： G11C11/1673 , G11C11/1659
摘要： A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) and associated read operations are disclosed. A bit cell includes a magnetic tunnel junction (MTJ) and a word line transistor, the bit cell being coupled to a bit line and a source line. A clamping circuit is coupled to the bit line and is configured to clamp the bit line voltage to a desired voltage level during a read operation of the STT-MRAM to prevent the bit line voltage from exceeding the desired voltage level. The desired voltage level is less than a write voltage threshold associated with a write operation of the STT-MRAM.
摘要翻译：公开了一种自旋转移力矩磁阻随机存取存储器（STT-MRAM）和相关读取操作。位单元包括磁性隧道结（MTJ）和字线晶体管，位单元耦合到位线和源极线。钳位电路耦合到位线，并且被配置为在STT-MRAM的读取操作期间将位线电压钳位到期望的电压电平，以防止位线电压超过期望的电压电平。期望的电压电平小于与STT-MRAM的写入操作相关联的写入电压阈值。

8. 发明授权

US08004880B2 Read disturb reduction circuit for spin transfer torque magnetoresistive random access memory 有权
标题翻译：用于自旋转移磁阻随机存取存储器的读干扰减小电路
公开(公告)号：US08004880B2
公开(公告)日：2011-08-23
申请号：US11771065
申请日：2007-06-29
申请人： Sei Seung Yoon , Seung H Kang , Medi Hamidi Sani
发明人： Sei Seung Yoon , Seung H Kang , Medi Hamidi Sani
IPC分类号： G11C11/00
CPC分类号： G11C7/02 , G11C7/062 , G11C7/067 , G11C7/12 , G11C11/1673
摘要： Systems, circuits and methods for reducing read disturbances in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A resistive element can be used during the read operation to control the read current and control read disturbances. An isolation element can be used to isolate the resistive element from the circuit during write operations.
摘要翻译：公开了用于减小转移转矩磁阻随机存取存储器（STT-MRAM）中的读取干扰的系统，电路和方法。在读取操作期间可以使用电阻元件来控制读取电流并控制读取干扰。隔离元件可用于在写入操作期间将电阻元件与电路隔离。

9. 发明授权

US07936590B2 Digitally-controllable delay for sense amplifier 有权
标题翻译：读数放大器的数字可控延时
公开(公告)号：US07936590B2
公开(公告)日：2011-05-03
申请号：US12329941
申请日：2008-12-08
申请人： Dongkyu Park , Anosh B. Davierwalla , Cheng Zhong , Mohamed Hassan Soliman Abu-Rahma , Sei Seung Yoon
发明人： Dongkyu Park , Anosh B. Davierwalla , Cheng Zhong , Mohamed Hassan Soliman Abu-Rahma , Sei Seung Yoon
IPC分类号： G11C11/00
CPC分类号： G11C7/22 , G11C7/06 , G11C11/1673 , G11C11/1693 , G11C2207/065 , G11C2207/2281
摘要： Circuits, apparatuses, and methods of interposing a selectable delay in reading a magnetic random access memory (MRAM) device are disclosed. In a particular embodiment, a circuit includes a sense amplifier, having a first input, a second input, and an enable input. A first amplifier coupled to an output of a magnetic resistance-based memory cell and a second amplifier coupled to a reference output of the cell also are provided. The circuit further includes a digitally-controllable amplifier coupled to a tracking circuit cell. The tracking circuit cell includes at least one element that is similar to the cell of the magnetic resistance-based memory. The first input of the sense amplifier is coupled to the first amplifier, the second input of the sense amplifier is coupled to the second amplifier, and the enable input is coupled to the third digitally-controllable amplifier via a logic circuit. The sense amplifier may generate an output value based on the amplified values received from the output of the magnetic resistance-based memory cell and the reference cell once the sense amplifier receives an enable signal from the digitally-controllable amplifier via the logic circuit.
摘要翻译：公开了在读取磁随机存取存储器（MRAM）装置中插入可选延迟的电路，装置和方法。在特定实施例中，电路包括具有第一输入，第二输入和使能输入的读出放大器。还提供耦合到基于磁阻的存储器单元的输出的第一放大器和耦合到单元的参考输出的第二放大器。电路还包括耦合到跟踪电路单元的数字可控放大器。跟踪电路单元包括与基于磁阻的存储器的单元相似的至少一个元件。读出放大器的第一输入耦合到第一放大器，读出放大器的第二输入耦合到第二放大器，并且使能输入经由逻辑电路耦合到第三数字可控放大器。一旦读出放大器经由逻辑电路接收到来自数字可控放大器的使能信号，读出放大器可以基于从基于磁阻的存储单元和参考单元的输出接收的放大值产生输出值。

10. 发明授权

US07929334B2 In-situ resistance measurement for magnetic random access memory (MRAM) 有权
标题翻译：磁性随机存取存储器（MRAM）的原位电阻测量
公开(公告)号：US07929334B2
公开(公告)日：2011-04-19
申请号：US12361588
申请日：2009-01-29
申请人： Hari Rao , Sei Seung Yoon , Xiaochun Zhu , Mohamed Abu-Rahma
发明人： Hari Rao , Sei Seung Yoon , Xiaochun Zhu , Mohamed Abu-Rahma
IPC分类号： G11C11/00 , G11C11/14 , G11C7/00 , G11C7/02
CPC分类号： G11C11/1653 , G11C7/14 , G11C11/1655 , G11C11/1673
摘要： A method of measuring resistance of a magnetic tunnel junction (MTJ) of an MRAM memory cell includes applying a voltage of a selected level to a memory cell comprising an MTJ in series with a memory cell transistor in a conducting state. A current through the memory cell is determined. A variable voltage is applied to a replica cell not having an MTJ and comprising a replica cell transistor in a conducting state. A value of the variable voltage is determined, wherein a resulting current through the replica cell is substantially the same as the current through the memory cell. The MTJ resistance is computed by taking the difference of the memory cell voltage and the determined variable replica cell voltage and dividing the result by the determined memory cell current.
摘要翻译：一种测量MRAM存储单元的磁性隧道结（MTJ）的电阻的方法包括将一个所选电平的电压施加到一个与导通状态的存储单元晶体管串联的MTJ的存储单元。确定通过存储单元的电流。可变电压被施加到不具有MTJ并且包括处于导通状态的复制单元晶体管的复制单元。确定可变电压的值，其中通过复制单元的结果电流与通过存储单元的电流基本相同。通过取存储单元电压和确定的可变副本单元电压的差值并将结果除以所确定的存储单元电流来计算MTJ电阻。

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