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1. 发明授权

US09575923B2 Input/output interface 有权
标题翻译：输入/输出接口
公开(公告)号：US09575923B2
公开(公告)日：2017-02-21
申请号：US14818586
申请日：2015-08-05
申请人： Young Chul Cho , Jung Bae Lee , Jung Hwan Choi
发明人： Young Chul Cho , Jung Bae Lee , Jung Hwan Choi
IPC分类号： H03K19/003 , G06F13/42 , H03K19/00 , G05F1/625
CPC分类号： G06F13/16 , G05F1/625 , G06F1/3287 , G06F13/4068 , G06F13/4221 , H03K19/0005 , Y02D10/14 , Y02D10/151
摘要： A method of operating an input/output interface includes selecting one of a plurality of output driver circuits according to a mode selection signal, and outputting a data signal using the selected one of the plurality of output driver circuits. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an on-die termination (ODT) circuit included in the input/output interface according to the mode selection signal. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an ODT circuit included in the input/output interface according to the mode selection signal.
摘要翻译：操作输入/输出接口的方法包括根据模式选择信号选择多个输出驱动器电路中的一个，并且使用多个输出驱动器电路中选择的一个输出驱动器电路来输出数据信号。另一种操作方法包括根据所接收的命令信号产生模式选择信号，并根据模式选择信号控制输入/输出接口中包括的片上终端（ODT）电路。另一种操作方法包括基于接收的命令信号产生模式选择信号，并根据模式选择信号控制输入/输出接口中包括的ODT电路。

2. 发明授权

US09349155B2 Computing apparatus and method using X-Y stack memory 有权
标题翻译：使用X-Y堆栈存储器的计算设备和方法
公开(公告)号：US09349155B2
公开(公告)日：2016-05-24
申请号：US13171772
申请日：2011-06-29
申请人： Soo-Jung Ryu , Sung-Bae Park , Woong Seo , Young-Chul Cho , Jeong-Wook Kim , Moo-Kyoung Chung , Ho-Young Kim
发明人： Soo-Jung Ryu , Sung-Bae Park , Woong Seo , Young-Chul Cho , Jeong-Wook Kim , Moo-Kyoung Chung , Ho-Young Kim
IPC分类号： G06T1/60 , G06F13/00 , G06F12/02
CPC分类号： G06T1/60
摘要： A computing apparatus is provided. The computing apparatus includes a memory unit configured to have an address space defined as a multidimensional space having at least two axes, and a memory access unit configured to include a first pointer register storing a first pointer pointing to a row corresponding to the first axis and a second pointer register storing a second pointer pointing to a column corresponding to the second axis.
摘要翻译：提供了一种计算装置。计算装置包括存储单元，其被配置为具有被定义为具有至少两个轴的多维空间的地址空间，以及存储器访问单元，其被配置为包括存储指向与第一轴对应的行的第一指针的第一指针寄存器，以及存储指向对应于第二轴的列的第二指针的第二指针寄存器。

3. 发明授权

US09105317B2 Memory system capable of calibrating output voltage level of semiconductor memory device and method of calibrating output voltage level of semiconductor memory device 有权
标题翻译：能够校准半导体存储器件的输出电压电平的存储器系统和校准半导体存储器件的输出电压电平的方法
公开(公告)号：US09105317B2
公开(公告)日：2015-08-11
申请号：US13611867
申请日：2012-09-12
申请人： Yoon-Joo Eom , Young-Jin Jeon , Yong-Cheol Bae , Young-Chul Cho
发明人： Yoon-Joo Eom , Young-Jin Jeon , Yong-Cheol Bae , Young-Chul Cho
IPC分类号： H03K19/003 , G11C7/10 , H03K19/00 , G11C29/02
CPC分类号： G11C7/1057 , G11C29/021 , G11C29/028 , G11C2207/2254 , H03K19/0005
摘要： Provided are a semiconductor memory device and a memory system including the same, which may calibrate a level of an output voltage in consideration of channel environment and a mismatch in on-die termination (ODT) resistance of a memory controller. The memory system includes a memory controller and a semiconductor memory device. The semiconductor memory device is configured to generate a reference voltage based on driving information of the memory controller, and calibrate an output voltage level based on a reference voltage when the semiconductor memory device is electrically connected to the memory controller.
摘要翻译：提供了一种半导体存储器件和包括该半导体存储器件的存储器系统，其可以考虑到沟道环境和存储器控制器的管芯端接（ODT）电阻的不匹配来校准输出电压的电平。存储器系统包括存储器控制器和半导体存储器件。半导体存储器件被配置为基于存储器控制器的驱动信息生成参考电压，并且当半导体存储器件电连接到存储器控制器时，基于参考电压校准输出电压电平。

4. 发明申请

US20120158394A1 SIMULATION APPARATUS AND METHOD FOR MULTICORE SYSTEM 有权
标题翻译：模拟装置及其制作方法
公开(公告)号：US20120158394A1
公开(公告)日：2012-06-21
申请号：US13171017
申请日：2011-06-28
申请人： Young Chul Cho , Soo-Jung Ryu , Moo-Kyoung Chung , Ho-Young Kim , Woong Seo
发明人： Young Chul Cho , Soo-Jung Ryu , Moo-Kyoung Chung , Ho-Young Kim , Woong Seo
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F17/5022 , G06F17/5031 , G06F2217/84
摘要： A simulation apparatus and method for a multicore system are provided. The simulation apparatus may prevent the occurrence of a data collision during the communication between modules and may reduce the overhead generated during simulation. The simulation apparatus may select a plurality of modules to be synchronized in terms of function execution timing based on timing information and may configure a multicore system architecture model using the selected modules. The simulation apparatus may acquire function execution timing information of the modules, control the execution of functions by the modules based on the acquired function execution timing information, and output the results of the control of the execution of functions by the modules.
摘要翻译：提供了一种用于多核系统的模拟装置和方法。模拟装置可以防止在模块之间的通信期间发生数据冲突，并且可以减少模拟期间产生的开销。模拟装置可以基于定时信息来选择要在功能执行定时上同步的多个模块，并且可以使用所选择的模块来配置多核系统体系结构模型。模拟装置可以获取模块的功能执行定时信息，基于所获取的功能执行定时信息控制模块的功能的执行，并且输出模块执行功能的控制结果。

5. 发明申请

US20110202704A1 MEMORY CONTROLLER, METHOD OF CONTROLLING MEMORY ACCESS, AND COMPUTING APPARATUS INCORPORATING MEMORY CONTROLLER 有权
标题翻译：存储器控制器，控制存储器访问的方法以及计算机存储器控制器
公开(公告)号：US20110202704A1
公开(公告)日：2011-08-18
申请号：US13006382
申请日：2011-01-13
申请人： Woong Seo , Soo-Jung Ryu , Yoon-Jin Kim , Young-Chul Cho , II-Hyun Park , Tae-Wook Oh
发明人： Woong Seo , Soo-Jung Ryu , Yoon-Jin Kim , Young-Chul Cho , II-Hyun Park , Tae-Wook Oh
IPC分类号： G06F12/00
CPC分类号： G06F13/1673 , Y02D10/14
摘要： A computing apparatus for accessing a multiple bank memory is provided. The computing apparatus includes a processor, a memory and a memory controller which is configured to store data in a data buffer by accessing the memory in an aligned word unit and output, in response to a request for an unaligned memory access by the processor, requested data by extracting the request data from the data buffer.
摘要翻译：提供一种用于访问多存储体存储器的计算装置。计算装置包括处理器，存储器和存储器控制器，其被配置为通过以对准的字单元访问存储器并且响应于处理器对未对齐的存储器访问的请求而输出来存储数据在数据缓冲器中数据通过从数据缓冲器提取请求数据。

6. 发明授权

US5712686A Inverse quantizer for use in MPEG-2 decoder 失效
标题翻译：用于MPEG-2解码器的逆量化器
公开(公告)号：US5712686A
公开(公告)日：1998-01-27
申请号：US774831
申请日：1996-12-27
申请人： Young-Chul Cho
发明人： Young-Chul Cho
IPC分类号： G06T9/00 , H04N19/126 , H04N19/42 , H04N19/423 , H04N19/46 , H04N19/60 , H04N19/70 , H04N7/40
CPC分类号： H04N19/45 , H04N19/126 , H04N19/60 , H04N19/61 , H04N19/124
摘要： An inverse quantizer, for use in an MPEG-2 video signal decoder, provides a 23-bit inverse quantized transform coefficient F in response to 13-bit (2QF+K), according to F=�(2QF+K).times.(W.times.quantizer.sub.-- scale )!/32 wherein QF is a quantized transform coefficient, W is an element of a predetermined weight matrix, and the quantizer.sub.-- scale is an integer ranging from 1 to 112 as given in MPEG-2 scheme. The inverse quantizer comprises a quantizer.sub.-- scale providing block for providing a (7-L)-bit modified quantizer.sub.-- scale and a selection signal based on the quantizer.sub.-- scale; a first multiplier for multiplying the modified quantizer.sub.-- scale with W, to provide a (15-L)-bit quantization step size; a second multiplier for multiplying (2QF+K) with the quantization step size, to provide a (28-L) bit output; a bit appending block for appending L zero bits to the output of the second multiplier, to provide a set of (L+1) 28-bit values; a multiplexor for selecting one of the (L+) 28-bit values in response to the selection signal; and a divider for dividing the selected 28-bit value by "2.sup.5 ", to thereby provide 23-bit F.
摘要翻译：根据F = [（2QF + K）×（W×量化器）），用于MPEG-2视频信号解码器的逆量化器响应13位（2QF + K）提供23位逆量化变换系数F -scale）] / 32其中QF是量化变换系数，W是预定权重矩阵的元素，并且量化器尺度是在MPEG-2方案中给出的范围从1到112的整数。逆量化器包括量化器尺度提供块，用于提供基于量化器尺度的（7-L）位修改量化器量表和选择信号; 用于将修改的量化器尺度与W相乘的第一乘法器，以提供（15-L）位量化步长; 用于将（2QF + K）与量化步长相乘的第二乘法器，以提供（28-L）位输出; 一个附加块，用于将L个零比特附加到第二个乘法器的输出，以提供一组（L + 1）个28比特值; 多路复用器，用于响应于选择信号选择一个（L +）28位值; 以及用于将所选择的28位值除以“25”的分频器，从而提供23位F.

7. 发明申请

US20180122741A1 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME 审中-公开
公开(公告)号：US20180122741A1
公开(公告)日：2018-05-03
申请号：US15679662
申请日：2017-08-17
申请人： Young-Chul CHO , Min-Su AHN , Jung-Hwan CHOI
发明人： Young-Chul CHO , Min-Su AHN , Jung-Hwan CHOI
IPC分类号： H01L23/522 , H01L23/00 , H01L23/532
CPC分类号： H01L23/5226 , H01L23/5227 , H01L23/525 , H01L23/53295 , H01L24/05 , H01L24/08 , H01L24/48 , H01L27/0248 , H01L2224/02166 , H01L2224/02331 , H01L2224/05024 , H01L2224/05554 , H01L2224/06135 , H01L2224/48227 , H01L2224/48463 , H01L2224/49171 , H01L2924/00014 , H01L2224/45099
摘要： A semiconductor device includes a substrate having a cell region and a circuit region, an upper wiring layer on the substrate, and a redistribution wiring layer on the upper wiring layer. The upper wiring layer includes a secondary uppermost wiring in the circuit region and an uppermost wiring on the secondary uppermost wiring. The uppermost wiring includes an uppermost chip pad electrically connected to the secondary uppermost wiring. At least a portion of the uppermost chip pad in the cell region. The redistribution wiring layer includes a redistribution wiring electrically connected to the uppermost chip pad. At least a portion of the redistribution wiring serving as a landing pad connected to an external connector.

8. 发明申请

US20120151154A1 LATENCY MANAGEMENT SYSTEM AND METHOD FOR MULTIPROCESSOR SYSTEM 有权
标题翻译：多处理器系统的延期管理系统和方法
公开(公告)号：US20120151154A1
公开(公告)日：2012-06-14
申请号：US13163948
申请日：2011-06-20
申请人： Woong Seo , Soo-Jung Ryu , Moo-Kyoung Chung , HoYoung Kim , Young-Chul Cho
发明人： Woong Seo , Soo-Jung Ryu , Moo-Kyoung Chung , HoYoung Kim , Young-Chul Cho
IPC分类号： G06F12/08
CPC分类号： G06F15/167
摘要： A latency management apparatus and method are provided. A latency management apparatus for a multiprocessor system having a plurality of processors and shared memory, when the shared memory and each of the processors is configured to generate a delayed signal, includes a delayed signal detector configured to detect the generated delayed signal; and one or more latency managers configured to manage an operation latency of any one of the processors upon detection of the delayed signal.
摘要翻译：提供了延迟管理装置和方法。一种用于具有多个处理器和共享存储器的多处理器系统的等待时间管理装置，当所述共享存储器和每个所述处理器被配置为产生延迟信号时，包括被配置为检测所生成的延迟信号的延迟信号检测器; 以及一个或多个延迟管理器，被配置为在检测到延迟的信号时管理任一个处理器的操作等待时间。

9. 发明申请

US20120092987A1 ROUTING APPARATUS AND NETWORK APPARATUS 有权
标题翻译：路由设备和网络设备
公开(公告)号：US20120092987A1
公开(公告)日：2012-04-19
申请号：US13092919
申请日：2011-04-23
申请人： Moo-Kyoung CHUNG , Soo-Jung RYU , Woong SEO , Ho-Young KIM , Young-Chul CHO
发明人： Moo-Kyoung CHUNG , Soo-Jung RYU , Woong SEO , Ho-Young KIM , Young-Chul CHO
IPC分类号： H04L12/56 , H04L12/26
CPC分类号： H04L45/60
摘要： A routing apparatus and a network apparatus that are capable of improving general system performance by compressing/decompressing data and transmitting the result of the compression/decompression, are provided. The routing apparatus may compress and/or decompress input data, and may transmit the compressed and/or decompressed input data.
摘要翻译：提供能够通过压缩/解压缩数据和发送压缩/解压缩的结果来提高一般系统性能的路由设备和网络设备。路由设备可以压缩和/或解压缩输入数据，并且可以传送压缩和/或解压缩的输入数据。

10. 发明申请

US20110218795A1 SIMULATOR OF MULTI-CORE SYSTEM EMPLOYING RECONFIGURABLE PROCESSOR CORES AND METHOD OF SIMULATING MULTI-CORE SYSTEM EMPLOYING RECONFIGURABLE PROCESSOR CORES 有权
标题翻译：使用可重构处理器线的多核系统的仿真器和模拟使用可重构处理器的多核系统的方法
公开(公告)号：US20110218795A1
公开(公告)日：2011-09-08
申请号：US13006730
申请日：2011-01-14
申请人： Young-Chul CHO , Soo-Jung Ryu , Yoon-Jin Kim , Woong Seo , Il-Hyun Park , Tae-Wook Oh
发明人： Young-Chul CHO , Soo-Jung Ryu , Yoon-Jin Kim , Woong Seo , Il-Hyun Park , Tae-Wook Oh
IPC分类号： G06F17/50 , G06F9/44
CPC分类号： G06F17/5045 , G06F9/44 , G06F17/50 , G06F17/5022 , G06F2217/68
摘要： Provided are a simulator of a multi-core system employing reconfigurable processor (RP) cores and a method of simulating a multi-core system employing RP cores. The simulator includes a structure builder to receive a structure definition file defining a structure of a system, select components described in the structure definition file from a component library, and fill a data structure with the selected components to generate a structure model of a multi-core system, and a simulation engine to execute an application program according to the structure model and output the result.
摘要翻译：提供了一种采用可重配置处理器（RP）核心的多核系统的模拟器和一种模拟采用RP核心的多核系统的方法。模拟器包括结构构建器，用于接收定义系统结构的结构定义文件，从组件库中选择在结构定义文件中描述的组件，并且用所选择的组件填充数据结构以生成多模式的结构模型，核心系统和模拟引擎，根据结构模型执行应用程序并输出结果。

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