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1. 发明授权

US08928349B2 On-die termination circuit, semiconductor memory device and memory system 有权
标题翻译：片上终端电路，半导体存储器件和存储器系统
公开(公告)号：US08928349B2
公开(公告)日：2015-01-06
申请号：US13755418
申请日：2013-01-31
申请人： Ki-Seok Oh , Joon-Young Park , Yong-Hun Ahn , Yong-Cheol Bae , Yong-Gwon Jeong , Jong-Hyun Choi
发明人： Ki-Seok Oh , Joon-Young Park , Yong-Hun Ahn , Yong-Cheol Bae , Yong-Gwon Jeong , Jong-Hyun Choi
IPC分类号： H03K17/16 , H03K19/003 , H03K19/0175 , H04L25/02 , G11C7/10
CPC分类号： H03K19/017545 , G11C7/1057 , G11C2207/2272 , H03K19/0175 , H04L25/0264
摘要： An ODT circuit is activated/deactivated in response to a latency control signal or a clock enable signal. The ODT circuit includes an ODT control circuit and an ODT section. The ODT control circuit determines an ODT status based on a read latency control signal (RL) and/or a write latency control signal (WL) to generate an ODT control signal. The ODT section is activated/deactivated in response to the ODT control signal.
摘要翻译：响应延迟控制信号或时钟使能信号，ODT电路被激活/去激活。 ODT电路包括ODT控制电路和ODT部分。 ODT控制电路基于读等待时间控制信号（RL）和/或写等待时间控制信号（WL）来确定ODT状态，以产生ODT控制信号。响应于ODT控制信号，ODT部分被激活/去激活。

2. 发明授权

US07994813B2 Semiconductor device capable of testing a transmission line for an impedance calibration code 有权
标题翻译：能够测试用于阻抗校准码的传输线的半导体器件
公开(公告)号：US07994813B2
公开(公告)日：2011-08-09
申请号：US12719953
申请日：2010-03-09
申请人： Young-Hoon Sohn , Kwang-Il Park , Yong-Gwon Jeong , Si-Hong Kim
发明人： Young-Hoon Sohn , Kwang-Il Park , Yong-Gwon Jeong , Si-Hong Kim
IPC分类号： H03K19/0175
CPC分类号： H04L25/0278
摘要： A semiconductor device includes a plurality of pads, where an external reference resistor is connected to a first one of the pads, an impedance calibrating unit configured to generate an impedance calibration code corresponding to an impedance of the reference resistor and output the impedance calibration code to a code transmitting line during a normal operating mode, and an impedance matching unit configured to perform an impedance matching operation in response to the impedance calibration code during the normal operating mode. The impedance calibrating unit is configured to output a test code to the code transmitting line in response to a test signal during a test operating mode. The impedance matching unit is configured to serialize the test code to output the serialized test code to each of the other pads in response to the test signal during the test operating mode.
摘要翻译：半导体器件包括多个焊盘，其中外部参考电阻器连接到焊盘的第一焊盘，阻抗校准单元被配置为产生对应于参考电阻器的阻抗的阻抗校准代码，并将阻抗校准代码输出到在正常操作模式期间的代码传输线，以及阻抗匹配单元，被配置为在正常操作模式期间响应于阻抗校准码执行阻抗匹配操作。阻抗校准单元被配置为在测试操作模式期间响应于测试信号将测试代码输出到代码传输线。阻抗匹配单元被配置为串行化测试代码，以在测试操作模式期间响应于测试信号将串行测试代码输出到每个其它焊盘。

3. 发明授权

US07656718B2 Semiconductor device having output buffer initialization circuit and output buffer initialization method 有权
标题翻译：半导体器件具有输出缓冲器初始化电路和输出缓冲器初始化方法
公开(公告)号：US07656718B2
公开(公告)日：2010-02-02
申请号：US11747041
申请日：2007-05-10
申请人： Yong-Gwon Jeong
发明人： Yong-Gwon Jeong
IPC分类号： G11C11/00
CPC分类号： G11C7/1051 , G11C7/1057 , G11C7/20
摘要： A semiconductor device has at least two semiconductor memory devices, each of which includes a memory cell array arranged in a matrix of rows and columns, a peripheral circuit writing data to a cell of the memory cell array and reading out and amplifying the written data, and an output buffer outputting cell data amplified by the peripheral circuit. The output buffer includes an output buffer initialization circuit activating an output buffer reset signal in response to the power up or power down of the semiconductor memory device and deactivating the output buffer reset signal in response to a first command signal output from a controller of the semiconductor memory device, and an output driver generating output data based on a data signal in response to a clock signal, a data enable signal, and the output buffer reset signal.
摘要翻译：半导体器件具有至少两个半导体存储器件，每个半导体存储器件包括排列成行和列的矩阵的存储单元阵列，外围电路将数据写入存储单元阵列的单元并读出并放大写入的数据，以及输出缓冲器，输出由外围电路放大的单元数据。输出缓冲器包括响应于半导体存储器件的上电或断电而激活输出缓冲器复位信号的输出缓冲器初始化电路，并且响应于从半导体的控制器输出的第一命令信号而去激活输出缓冲器复位信号存储器件和输出驱动器，其响应于时钟信号，数据使能信号和输出缓冲器复位信号，基于数据信号产生输出数据。

4. 发明申请

US20080037334A1 SEMICONDUCTOR DEVICE HAVING OUTPUT BUFFER INITIALIZATION CIRCUIT AND OUTPUT BUFFER INITIALIZATION METHOD 有权
标题翻译：具有输出缓冲器初始化电路和输出缓冲器初始化方法的半导体器件
公开(公告)号：US20080037334A1
公开(公告)日：2008-02-14
申请号：US11747041
申请日：2007-05-10
申请人： Yong-Gwon Jeong
发明人： Yong-Gwon Jeong
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G11C7/1057 , G11C7/20
摘要： A semiconductor device has at least two semiconductor memory devices, each of which includes a memory cell array arranged in a matrix of rows and columns, a peripheral circuit writing data to a cell of the memory cell array and reading out and amplifying the written data, and an output buffer outputting cell data amplified by the peripheral circuit. The output buffer includes an output buffer initialization circuit activating an output buffer reset signal in response to the power up or power down of the semiconductor memory device and deactivating the output buffer reset signal in response to a first command signal output from a controller of the semiconductor memory device, and an output driver generating output data based on a data signal in response to a clock signal, a data enable signal, and the output buffer reset signal.
摘要翻译：半导体器件具有至少两个半导体存储器件，每个半导体存储器件包括排列成行和列的矩阵的存储单元阵列，外围电路将数据写入存储单元阵列的单元并读出并放大写入的数据，以及输出缓冲器，输出由外围电路放大的单元数据。输出缓冲器包括响应于半导体存储器件的上电或断电而激活输出缓冲器复位信号的输出缓冲器初始化电路，并且响应于从半导体的控制器输出的第一命令信号而去激活输出缓冲器复位信号存储器件和输出驱动器，其响应于时钟信号，数据使能信号和输出缓冲器复位信号，基于数据信号产生输出数据。

5. 发明申请

US20100237902A1 SEMICONDUCTOR DEVICE CAPABLE OF TESTING A TRANSMISSION LINE FOR AN IMPEDANCE CALIBRATION CODE 有权
标题翻译：用于测试用于阻抗校准码的传输线的半导体器件
公开(公告)号：US20100237902A1
公开(公告)日：2010-09-23
申请号：US12719953
申请日：2010-03-09
申请人： Young-Hoon Sohn , Kwang-Il Park , Yong-Gwon Jeong , Si-Hong Kim
发明人： Young-Hoon Sohn , Kwang-Il Park , Yong-Gwon Jeong , Si-Hong Kim
IPC分类号： H03K19/003 , G01R35/00
CPC分类号： H04L25/0278
摘要： A semiconductor device includes a plurality of pads, where an external reference resistor is connected to a first one of the pads, an impedance calibrating unit configured to generate an impedance calibration code corresponding to an impedance of the reference resistor and output the impedance calibration code to a code transmitting line during a normal operating mode, and an impedance matching unit configured to perform an impedance matching operation in response to the impedance calibration code during the normal operating mode. The impedance calibrating unit is configured to output a test code to the code transmitting line in response to a test signal during a test operating mode. The impedance matching unit is configured to serialize the test code to output the serialized test code to each of the other pads in response to the test signal during the test operating mode.
摘要翻译：半导体器件包括多个焊盘，其中外部参考电阻器连接到焊盘的第一焊盘，阻抗校准单元被配置为产生对应于参考电阻器的阻抗的阻抗校准代码，并将阻抗校准代码输出到在正常操作模式期间的代码传输线，以及阻抗匹配单元，被配置为在正常操作模式期间响应于阻抗校准码执行阻抗匹配操作。阻抗校准单元被配置为在测试操作模式期间响应于测试信号将测试代码输出到代码传输线。阻抗匹配单元被配置为串行化测试代码，以在测试操作模式期间响应于测试信号将串行测试代码输出到每个其它焊盘。

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