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1. 发明申请

US20090045389A1 PHASE CHANGE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US20090045389A1
公开(公告)日：2009-02-19
申请号：US12169612
申请日：2008-07-08
申请人： Yong Seok Eun , Su Jin Chae , Keum Bum Lee , Heon Yong Chang , Min Yong Lee
发明人： Yong Seok Eun , Su Jin Chae , Keum Bum Lee , Heon Yong Chang , Min Yong Lee
IPC分类号： H01L47/00 , H01L21/00
CPC分类号： H01L45/1233 , G11C13/0004 , H01L45/06 , H01L45/1253 , H01L45/16
摘要： A phase change memory device and a method for manufacturing the same. The method includes the steps of defining bottom electrode contact holes by removing portions of an insulation layer, to expose bottom electrodes, on a semiconductor substrate on which the bottom electrodes and the insulation layer are sequentially formed; forming amorphous silicon spacers on inner sidewalls of the bottom electrode contact holes; and forming bottom electrode contacts in the bottom electrode contact holes.
摘要翻译：相变存储装置及其制造方法。该方法包括以下步骤：通过去除绝缘层的一部分来暴露底部电极，在其上依次形成底部电极和绝缘层的半导体衬底上限定底部电极接触孔; 在底部电极接触孔的内侧壁上形成非晶硅间隔物; 以及在底部电极接触孔中形成底部电极接触。

2. 发明授权

US08049199B2 Phase change memory device and method for manufacturing the same 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US08049199B2
公开(公告)日：2011-11-01
申请号：US12169612
申请日：2008-07-08
申请人： Yong Seok Eun , Su Jin Chae , Keum-Bum Lee , Heon-Yong Chang , Min-Yong Lee
发明人： Yong Seok Eun , Su Jin Chae , Keum-Bum Lee , Heon-Yong Chang , Min-Yong Lee
IPC分类号： H01L47/00 , H01L21/00
CPC分类号： H01L45/1233 , G11C13/0004 , H01L45/06 , H01L45/1253 , H01L45/16
摘要： A phase change memory device and a method for manufacturing the same. The method includes the steps of defining bottom electrode contact holes by removing portions of an insulation layer, to expose bottom electrodes, on a semiconductor substrate on which the bottom electrodes and the insulation layer are sequentially formed; forming amorphous silicon spacers on inner sidewalls of the bottom electrode contact holes; and forming bottom electrode contacts in the bottom electrode contact holes.
摘要翻译：相变存储装置及其制造方法。该方法包括以下步骤：通过去除绝缘层的一部分来暴露底部电极，在其上依次形成底部电极和绝缘层的半导体衬底上限定底部电极接触孔; 在底部电极接触孔的内侧壁上形成非晶硅间隔物; 以及在底部电极接触孔中形成底部电极接触。

3. 发明申请

US20090256209A1 Gate Structure of Semiconductor Device 有权
标题翻译：半导体器件的栅极结构
公开(公告)号：US20090256209A1
公开(公告)日：2009-10-15
申请号：US12485649
申请日：2009-06-16
申请人： Young Bog Kim , Jun Soo Chang , Min Yong Lee , Yong Seok Eun
发明人： Young Bog Kim , Jun Soo Chang , Min Yong Lee , Yong Seok Eun
IPC分类号： H01L27/088
CPC分类号： H01L27/10876 , H01L21/2815 , H01L29/66636
摘要： A gate structure of a semiconductor device comprising a silicon substrate having a field oxide film, a plurality of gates formed by sequentially stacking a first gate dielectric film, a first gate conductive film, and a gate silicide film on the silicon substrate. a thermal oxide film formed on a side of the first gate conductive film, a plurality of trenches formed between the gates, a second gate oxide film formed on an interior wall of each trench; and a second conductive film formed in a spacer shape on a predetermined region of the second gate oxide film, and on a side of the first gate conductive film, the gate silicide film and the thermal oxide film.
摘要翻译：一种半导体器件的栅极结构，包括具有场氧化物膜的硅衬底，通过在硅衬底上依次层叠第一栅极电介质膜，第一栅极导电膜和栅极硅化物膜而形成的多个栅极。形成在第一栅极导电膜的一侧的热氧化膜，形成在栅极之间的多个沟槽，形成在每个沟槽的内壁上的第二栅极氧化膜; 以及在所述第二栅极氧化膜的预定区域上形成间隔物形状的第二导电膜，以及在所述第一栅极导电膜，所述栅极硅化物膜和所述热氧化物膜的一侧。

4. 发明授权

US07563673B2 Method of forming gate structure of semiconductor device 失效
标题翻译：形成半导体器件栅极结构的方法
公开(公告)号：US07563673B2
公开(公告)日：2009-07-21
申请号：US11268846
申请日：2005-11-08
申请人： Young Bog Kim , Jun Soo Chang , Min Yong Lee , Yong Seok Eun
发明人： Young Bog Kim , Jun Soo Chang , Min Yong Lee , Yong Seok Eun
IPC分类号： H01L21/336
CPC分类号： H01L27/10876 , H01L21/2815 , H01L29/66636
摘要： Disclosed herein is a method for forming a gate structure of a semiconductor device. The method comprises forming a plurality of gates including a first gate dielectric film, a first gate conductive film, and a gate silicide film sequentially stacked on a silicon substrate having a field oxide film, forming a thermal oxide film on a side of the first gate conductive film, etching the silicon substrate exposed between the plurality of gates to a predetermined depth to form a plurality of trenches, forming a second gate oxide film on the interior wall of the trenches, and forming a second gate conductive film in a spacer shape on a predetermined region of the second gate oxide film, and on a side of the first gate conductive film, the gate silicide film, and the thermal oxide film.
摘要翻译：本文公开了一种用于形成半导体器件的栅极结构的方法。该方法包括形成多个栅极，其包括依次层叠在具有场氧化膜的硅基板上的第一栅极电介质膜，第一栅极导电膜和栅极硅化物膜，在第一栅极的一侧形成热氧化膜将暴露在所述多个栅极之间的硅衬底蚀刻到预定深度以形成多个沟槽，在所述沟槽的内壁上形成第二栅极氧化膜，并且形成间隔物形状的第二栅极导电膜第二栅极氧化膜的预定区域，以及第一栅极导电膜，栅极硅化物膜和热氧化物膜的一侧。

5. 发明授权

US07859041B2 Gate structure of semiconductor device 有权
标题翻译：半导体器件的栅极结构
公开(公告)号：US07859041B2
公开(公告)日：2010-12-28
申请号：US12485649
申请日：2009-06-16
申请人： Young Bog Kim , Jun Soo Chang , Min Yong Lee , Yong Seok Eun
发明人： Young Bog Kim , Jun Soo Chang , Min Yong Lee , Yong Seok Eun
IPC分类号： H01L29/76
CPC分类号： H01L27/10876 , H01L21/2815 , H01L29/66636
摘要： A gate structure of a semiconductor device comprising a silicon substrate having a field oxide film, a plurality of gates formed by sequentially stacking a first gate dielectric film, a first gate conductive film, and a gate silicide film on the silicon substrate. a thermal oxide film formed on a side of the first gate conductive film, a plurality of trenches formed between the gates, a second gate oxide film formed on an interior wall of each trench; and a second conductive film formed in a spacer shape on a predetermined region of the second gate oxide film, and on a side of the first gate conductive film, the gate silicide film and the thermal oxide film.
摘要翻译：一种半导体器件的栅极结构，包括具有场氧化物膜的硅衬底，通过在硅衬底上依次层叠第一栅极电介质膜，第一栅极导电膜和栅极硅化物膜而形成的多个栅极。形成在第一栅极导电膜的一侧的热氧化膜，形成在栅极之间的多个沟槽，形成在每个沟槽的内壁上的第二栅极氧化膜; 以及在所述第二栅极氧化膜的预定区域上形成间隔物形状的第二导电膜，以及在所述第一栅极导电膜，所述栅极硅化物膜和所述热氧化物膜的一侧。

6. 发明申请

US20080160699A1 Method for Fabricating Semiconductor Device Having Bulb-Type Recessed Channel 审中-公开
标题翻译：制造具有灯泡型嵌入式通道的半导体器件的方法
公开(公告)号：US20080160699A1
公开(公告)日：2008-07-03
申请号：US11759930
申请日：2007-06-07
申请人： Min Yong Lee , Yong Seok Eun , Dong Su Park , Jun Soo Chang
发明人： Min Yong Lee , Yong Seok Eun , Dong Su Park , Jun Soo Chang
IPC分类号： H01L21/336
CPC分类号： H01L29/66537 , H01L21/26586 , H01L29/66621 , H01L29/78
摘要： A method for fabricating a semiconductor device having a bulb-type recessed channel including forming a mask layer on the semiconductor substrate to expose a region where a trench for a bulb-type recessed channel can be formed, forming the trench in the semiconductor substrate, implanting dopant ions in three-dimensional radial directions with a predetermined tilt angle in the exposed region of the semiconductor substrate, removing the mask layer, forming a gate stack in the region including the trench, and forming a source/drain in the semiconductor substrate.
摘要翻译：一种制造具有灯泡型凹槽的半导体器件的方法，包括在半导体衬底上形成掩模层，以暴露可形成用于灯泡型凹槽的沟槽的区域，在半导体衬底中形成沟槽，掺杂剂离子在半导体衬底的暴露区域中具有预定倾斜角的三维径向方向，去除掩模层，在包括沟槽的区域中形成栅叠层，并在半导体衬底中形成源/漏。

7. 发明授权

US06974745B2 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06974745B2
公开(公告)日：2005-12-13
申请号：US10657871
申请日：2003-09-09
申请人： Min Yong Lee , Yong Seok Eun
发明人： Min Yong Lee , Yong Seok Eun
IPC分类号： H01L21/8234 , H01L21/8242
CPC分类号： H01L27/10888 , H01L21/823418 , H01L21/823475
摘要： Disclosed is a method of manufacturing semiconductor devices, which can improve electrical characteristics of semiconductor devices. The method of manufacturing comprises the following steps of: forming a plurality of gates on a semiconductor substrate; forming an insulation layer on an entire surface of the semiconductor substrate to coat the plurality of gates; selectively removing the insulation layer by using a first mask pattern to form a contact hole, which exposes a source/drain junction and a conductive layer in a portion of the gates in the semiconductor substrate; removing the first mask pattern and forming a second mask pattern on the selectively removed insulation layer, the second mask pattern exposing the p+ source/drain junction in the semiconductor substrate; implanting ion into the p+ source/drain junction in the semiconductor substrate by using the second mask pattern as a mask; removing the second mask pattern and rapid thermal annealing the entire substrate in a activation temperature range of dopant which is implanted in the ion implantation step; and burying the contact hole with conductive material to form a bit line contact plug. The invention can effectively reduce bit line contact resistance but raise resistance uniformity without variation in related techniques such as etching and contact material for forming contacts.
摘要翻译：公开了可以改善半导体器件的电气特性的半导体器件的制造方法。制造方法包括以下步骤：在半导体衬底上形成多个栅极; 在所述半导体衬底的整个表面上形成绝缘层以涂覆所述多个栅极; 通过使用第一掩模图案来形成接触孔来选择性地去除绝缘层，所述接触孔在半导体衬底中的栅极的一部分中暴露出源极/漏极结和导电层; 去除所述第一掩模图案并在所述选择性去除的绝缘层上形成第二掩模图案，所述第二掩模图案暴露所述半导体衬底中的所述p +源极/漏极结; 通过使用第二掩模图案作为掩模将离子注入半导体衬底中的p +源极/漏极结; 在离子注入步骤中注入的掺杂剂的活化温度范围内去除第二掩模图案并对整个基板进行快速热退火; 并用导电材料掩埋接触孔以形成位线接触塞。本发明可以有效地降低位线接触电阻，但是提高电阻均匀性，而不会在诸如用于形成触点的蚀刻和接触材料等相关技术中发生变化。

8. 发明授权

US07723189B2 Method for manufacturing semiconductor device having recess gate 失效
标题翻译：具有凹槽的半导体器件的制造方法
公开(公告)号：US07723189B2
公开(公告)日：2010-05-25
申请号：US11618565
申请日：2006-12-29
申请人： Yong Seok Eun , Su Ho Kim , An Bae Lee , Hai Won Kim
发明人： Yong Seok Eun , Su Ho Kim , An Bae Lee , Hai Won Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L21/76224 , H01L29/66583
摘要： A method for manufacturing a semiconductor device having recess gates includes forming an etch stop film on a semiconductor substrate; forming an etch stop film pattern selectively exposing the semiconductor substrate by patterning the etch stop film; forming a semiconductor layer on the semiconductor substrate; forming a hard mask film pattern exposing regions, for forming trenches for recess gates, on the semiconductor substrate; removing the semiconductor layer using the hard mask film pattern as a mask until the etch stop film pattern is exposed; forming the trenches for recess gates by removing the etch stop film pattern from the semiconductor substrate; and forming gate stacks, each of which is formed in the corresponding one of the trenches for recess gates.
摘要翻译：一种用于制造具有凹槽的半导体器件的方法包括在半导体衬底上形成蚀刻停止膜; 通过图案化所述蚀刻停止膜形成选择性地暴露所述半导体衬底的蚀刻停止膜图案; 在半导体衬底上形成半导体层; 在半导体衬底上形成用于形成用于凹槽的沟槽的暴露区域的硬掩模膜图案; 使用硬掩模膜图案作为掩模去除半导体层，直到蚀刻停止膜图案被曝光; 通过从半导体衬底去除蚀刻停止膜图案来形成凹槽的沟槽; 以及形成栅极堆叠，每个栅极堆叠形成在用于凹槽的相应的一个沟槽中。

9. 发明授权

US06949480B2 Method for depositing silicon nitride layer of semiconductor device 失效
公开(公告)号：US06949480B2
公开(公告)日：2005-09-27
申请号：US10889477
申请日：2004-07-12
申请人： Hyung Kyun Kim , Sung Hoon Jung , Yong Seok Eun
发明人： Hyung Kyun Kim , Sung Hoon Jung , Yong Seok Eun
IPC分类号： H01L21/205 , C23C16/34 , H01L21/302 , H01L21/318 , H01L21/44 , H01L21/461
CPC分类号： H01L21/02271 , C23C16/345 , H01L21/0217 , H01L21/3185
摘要： Disclosed is a method for depositing a silicon nitride layer of a semiconductor device. The method includes the steps of providing Al-based compound as a catalyst, and reacting DCS with NH3 by using the Al catalyst, thereby depositing the silicon nitride layer. DCS is reacted with NH3 by using the Al catalyst when depositing the silicon nitride layer, so dissolution of DCS is promoted by means of the Al catalyst, so that the silicon nitride layer is deposited at a high speed, thereby improving productivity of semiconductor devices. The silicon nitride layer is deposited by using DCS under a low-temperature condition of about 500 to 800° C., without deteriorating device characteristics.

10. 发明授权

US08481431B2 Method for opening one-side contact region of vertical transistor and method for fabricating one-side junction region using the same 有权
标题翻译：用于开放垂直晶体管的单面接触区域的方法及使用该方法制造单面接合区域的方法
公开(公告)号：US08481431B2
公开(公告)日：2013-07-09
申请号：US13161846
申请日：2011-06-16
申请人： Kyong Bong Rouh , Yong Seok Eun , Eun Shil Park
发明人： Kyong Bong Rouh , Yong Seok Eun , Eun Shil Park
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/32155 , H01L21/2236 , H01L21/2257 , H01L21/26586 , H01L21/31144 , H01L21/32134 , H01L27/10876 , H01L27/10888 , H01L29/66666 , H01L29/7827
摘要： A method for opening a one-side contact region of a vertical transistor is provided. The one-side contact region of the vertical transistor is opened using a polysilicon layer, a certain portion of which can be selectively removed by a selective ion implantation process. In order to selectively remove the polysilicon layer formed on one of both sides of an active region, at which the one-side contact is to be formed, impurity ion implantation is performed in a direction vertical to the polysilicon layer by a plasma doping process, and a tilt ion implantation using an existing ion implantation process is performed. In this manner, the polysilicon layer is selectively doped, and the undoped portion of the polysilicon layer is selectively removed.
摘要翻译：提供了一种用于打开垂直晶体管的单侧接触区域的方法。使用多晶硅层打开垂直晶体管的单面接触区域，通过选择性离子注入工艺可以选择性地去除其中的一部分。为了选择性地去除形成在要形成单面接触的有源区的两侧的多晶硅层，通过等离子体掺杂工艺在与多晶硅层垂直的方向上进行杂质离子注入，并且使用现有的离子注入工艺进行倾斜离子注入。以这种方式，选择性地掺杂多晶硅层，并且选择性地去除多晶硅层的未掺杂部分。

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