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1. 发明申请

US20090045389A1 PHASE CHANGE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US20090045389A1
公开(公告)日：2009-02-19
申请号：US12169612
申请日：2008-07-08
申请人： Yong Seok Eun , Su Jin Chae , Keum Bum Lee , Heon Yong Chang , Min Yong Lee
发明人： Yong Seok Eun , Su Jin Chae , Keum Bum Lee , Heon Yong Chang , Min Yong Lee
IPC分类号： H01L47/00 , H01L21/00
CPC分类号： H01L45/1233 , G11C13/0004 , H01L45/06 , H01L45/1253 , H01L45/16
摘要： A phase change memory device and a method for manufacturing the same. The method includes the steps of defining bottom electrode contact holes by removing portions of an insulation layer, to expose bottom electrodes, on a semiconductor substrate on which the bottom electrodes and the insulation layer are sequentially formed; forming amorphous silicon spacers on inner sidewalls of the bottom electrode contact holes; and forming bottom electrode contacts in the bottom electrode contact holes.
摘要翻译：相变存储装置及其制造方法。该方法包括以下步骤：通过去除绝缘层的一部分来暴露底部电极，在其上依次形成底部电极和绝缘层的半导体衬底上限定底部电极接触孔; 在底部电极接触孔的内侧壁上形成非晶硅间隔物; 以及在底部电极接触孔中形成底部电极接触。

2. 发明授权

US08450772B2 Phase change RAM device and method for manufacturing the same 有权
标题翻译：相变RAM装置及其制造方法
公开(公告)号：US08450772B2
公开(公告)日：2013-05-28
申请号：US12362605
申请日：2009-01-30
申请人： Heon Yong Chang , Suk Kyoung Hong , Hae Chan Park
发明人： Heon Yong Chang , Suk Kyoung Hong , Hae Chan Park
IPC分类号： H01L29/02
CPC分类号： H01L45/144 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： A phase change RAM device includes a semiconductor substrate having a phase change cell area and a voltage application area; a first oxide layer, a nitride layer and a second oxide layer sequentially formed on the semiconductor substrate; a first plug formed in the first oxide layer, the nitride layer and the second oxide layer of the phase change cell area; a second plug formed in the first oxide layer and the nitride layer of the voltage application area; a conductive line formed in the second oxide layer; a third oxide layer formed on the second oxide layer; a lower electrode shaped like a plug, the lower electrode being formed so as to directly make contact with the first plug; and a phase change layer and an upper electrode sequentially formed on the lower electrode in a pattern form.
摘要翻译：相变RAM装置包括具有相变单元区域和电压施加区域的半导体基板; 依次形成在所述半导体衬底上的第一氧化物层，氮化物层和第二氧化物层; 形成在第一氧化物层中的第一插塞，相变单元区域的氮化物层和第二氧化物层; 形成在第一氧化物层和电压施加区域的氮化物层中的第二插塞; 形成在所述第二氧化物层中的导电线; 形成在所述第二氧化物层上的第三氧化物层; 形成为塞子的下部电极，所述下部电极形成为直接与所述第一插塞接触; 以及以图案形式依次形成在下电极上的相变层和上电极。

3. 发明授权

US08416616B2 Phase change memory device and method for manufacturing the same 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US08416616B2
公开(公告)日：2013-04-09
申请号：US13036916
申请日：2011-02-28
申请人： Heon Yong Chang , Myoung Sub Kim , Gap Sok Do
发明人： Heon Yong Chang , Myoung Sub Kim , Gap Sok Do
IPC分类号： G11C11/00
CPC分类号： H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/128 , H01L45/144
摘要： A phase change memory device includes a silicon substrate having a bar-type active region and an N-type impurity region formed in a surface of the active region. A first insulation layer is formed on the silicon substrate, and the first insulation layer includes a plurality of first contact holes and second contact holes. PN diodes are formed in the first contact holes. Heat sinks are formed in the first contact holes on the PN diodes, and contact plugs fill the second contact holes. A second insulation layer having third contact holes is formed on the first insulation layer. Heaters fill the third contact holes. A stack pattern of a phase change layer and a top electrode is formed to contact the heaters. The heat sink quickly cools heat transferred from the heater to the phase change layer.
摘要翻译：相变存储器件包括具有棒状有源区和形成在有源区的表面中的N型杂质区的硅衬底。第一绝缘层形成在硅衬底上，第一绝缘层包括多个第一接触孔和第二接触孔。 PN二极管形成在第一接触孔中。在PN二极管上的第一接触孔中形成散热片，接触塞填充第二接触孔。具有第三接触孔的第二绝缘层形成在第一绝缘层上。加热器填充第三个接触孔。形成相变层和顶部电极的堆叠图案以接触加热器。散热片快速冷却从加热器传递到相变层的热量。

4. 发明授权

US08293650B2 Phase change memory device in which a phase change layer is stably formed and prevented from lifting and method for manufacturing the same 有权
标题翻译：其中稳定地形成和防止相变层提升的相变存储装置及其制造方法
公开(公告)号：US08293650B2
公开(公告)日：2012-10-23
申请号：US13026408
申请日：2011-02-14
申请人： Heon Yong Chang
发明人： Heon Yong Chang
IPC分类号： H01L21/02
CPC分类号： H01L45/1675 , H01L27/2463 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144
摘要： A phase change memory device includes a semiconductor substrate having a plurality of phase change cell regions; a lower electrode formed in each of the phase change cell regions on the semiconductor substrate; an insulation layer formed on the semiconductor substrate to cover the lower electrode and defined with a contact hole which exposes the lower electrode; a heater formed in the contact hole; a conductive pattern formed on the insulation layer to be spaced apart from the heater; a phase change layer formed on the heater, the conductive pattern, and portions of the insulation layer between the heater and the conductive pattern; and an upper electrode formed on the phase change layer. This phase change memory device allows the phase change layer to be stably formed and prevents the phase change layer from lifting.
摘要翻译：相变存储器件包括具有多个相变单元区域的半导体衬底; 形成在所述半导体衬底上的每个相变单元区域中的下电极; 形成在所述半导体衬底上以覆盖所述下电极并且限定有暴露所述下电极的接触孔的绝缘层; 形成在所述接触孔中的加热器; 形成在所述绝缘层上以与所述加热器间隔开的导电图案; 形成在加热器上的相变层，导电图案，以及加热器和导电图案之间的绝缘层的部分; 以及形成在所述相变层上的上电极。该相变存储器件允许稳定地形成相变层，并防止相变层提升。

5. 发明授权

US08258002B2 Phase change memory device resistant to stack pattern collapse and a method for manufacturing the same 有权
标题翻译：耐堆叠图案塌陷的相变存储器件及其制造方法
公开(公告)号：US08258002B2
公开(公告)日：2012-09-04
申请号：US12782215
申请日：2010-05-18
申请人： Heon Yong Chang
发明人： Heon Yong Chang
IPC分类号： H01L21/00
CPC分类号： H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1675
摘要： A phase change memory device resistant to stack pattern collapse is presented. The phase change memory device includes a silicon substrate, switching elements, heaters, stack patterns, bit lines and word lines. The silicon substrate has a plurality of active areas. The switching elements are connected to the active areas. The heaters are connected to the switching elements. The stack patterns are connected to the heaters. The bit lines are connected to the stack patterns. The word lines are connected to the active areas of the silicon substrate.
摘要翻译：提出了一种耐堆叠模式崩溃的相变存储器件。相变存储器件包括硅衬底，开关元件，加热器，堆叠图案，位线和字线。硅衬底具有多个有源区域。开关元件连接到有源区。加热器连接到开关元件。堆叠图案连接到加热器。位线连接到堆栈模式。字线连接到硅衬底的有源区。

6. 发明授权

US08216941B2 Method for manufacturing phase change memory device 有权
标题翻译：相变存储器件的制造方法
公开(公告)号：US08216941B2
公开(公告)日：2012-07-10
申请号：US12211418
申请日：2008-09-16
申请人： Heon Yong Chang
发明人： Heon Yong Chang
IPC分类号： H01L21/302
CPC分类号： H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/165 , H01L45/1675
摘要： A method for manufacturing a phase change memory device that prevents or minimizes adverse performance characteristics associated with inadequate overlap between top electrode contacts and top electrodes. The method prevents or minimizes unwanted chemical changes and etch losses of the phase change material when building the top electrode. The method includes forming spacers on sidewalls of remaining portions of the insulation layer and the hard masks so that subsequent etching of the conductive layer and the phase change material layer uses the spacers and the hard masks as an etch mask to form top electrodes and a phase change layer. Accordingly, the method promises to provide a way of achieving a high level of integration for the resultant phase change memory devices.
摘要翻译：一种用于制造相变存储器件的方法，其防止或最小化与顶部电极接触件和顶部电极之间的不充分重叠相关联的不良性能特性。该方法防止或最小化构建顶部电极时相变材料的不希望的化学变化和蚀刻损失。该方法包括在绝缘层和硬掩模的剩余部分的侧壁上形成间隔物，使得导电层和相变材料层的后续蚀刻使用间隔物和硬掩模作为蚀刻掩模来形成顶电极和相改变层。因此，该方法有助于提供一种实现所得到的相变存储器件的高集成度的方法。

7. 发明授权

US08071968B2 Phase change memory device and method for manufacturing the same 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US08071968B2
公开(公告)日：2011-12-06
申请号：US12431885
申请日：2009-04-29
申请人： Heon Yong Chang
发明人： Heon Yong Chang
IPC分类号： H01L29/02
CPC分类号： H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/128 , H01L45/144 , H01L45/16
摘要： A phase change memory device and a method of manufacturing the same are presented. The phase change memory device includes a silicon substrate, a first insulation layer, cell switching elements, heaters, a gate, a second insulation layer, a barrier layer, a phase change layer and top electrodes. The first insulation layer has first holes. The cell switching elements are in the first holes. The heaters are on the cell switching elements. The gate is higher than the cell switching elements. The second insulation layer having second holes which expose the heaters, and exposes a hard mask layer of the gate. The barrier layer is on sidewalls of the second holes and on the second insulation layer. The phase change layer is formed in and over the second holes in which the barrier layer is formed. The top electrodes are formed on the phase change layer.
摘要翻译：提出了一种相变存储器件及其制造方法。相变存储器件包括硅衬底，第一绝缘层，电池开关元件，加热器，栅极，第二绝缘层，势垒层，相变层和顶电极。第一绝缘层具有第一孔。电池开关元件位于第一个孔中。加热器在电池开关元件上。门高于单元开关元件。第二绝缘层具有暴露加热器的第二孔，并露出门的硬掩模层。阻挡层位于第二孔的侧壁和第二绝缘层上。相变层形成在其中形成阻挡层的第二孔中和上方。上电极形成在相变层上。

8. 发明授权

US07880159B2 Phase change memory device in which a distance between a lower electrode and a ground line is increased to secure the sensing margin of a cell and method for manufacturing the same 有权
标题翻译：相位改变存储装置，其中下电极和接地线之间的距离增加以确保电池的感测余量及其制造方法
公开(公告)号：US07880159B2
公开(公告)日：2011-02-01
申请号：US12559736
申请日：2009-09-15
申请人： Heon Yong Chang
发明人： Heon Yong Chang
IPC分类号： H01L29/02
CPC分类号： H01L45/144 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： A phase change memory device includes a semiconductor substrate having active regions and an isolation structure; gate lines extending in a direction perpendicular to the active regions; a source region and a drain region formed in a surface of each active region; a dot type lower electrode including a first contact plug formed in the drain region; second contact plugs formed in the source region and the isolation structure forming a line parallel to the gate line; a lower electrode contact formed on the lower electrode; a phase change layer and an upper electrode formed on the lower electrode contact; an upper electrode contact formed on the upper electrode; contacts for ground lines, formed between the active regions to come into contact with the second contact plugs; a bit line formed in the active region; and ground lines formed between the active regions.
摘要翻译：相变存储器件包括具有有源区的半导体衬底和隔离结构; 栅极线在垂直于有源区的方向上延伸; 形成在每个有源区的表面中的源区和漏区; 点状下电极，其包括形成在漏极区域中的第一接触插塞; 形成在源极区域中的第二接触插塞和形成与栅极线平行的线路的隔离结构; 形成在下电极上的下电极接触; 形成在下电极接点上的相变层和上电极; 形成在上电极上的上电极接触; 用于接地线的触点，形成在有源区域之间以与第二接触插塞接触; 在有源区中形成位线; 以及在活性区域之间形成的接地线。

9. 发明授权

US07687310B2 Method for manufacturing phase change memory device which can stably form an interface between a lower electrode and a phase change layer 有权
标题翻译：一种可以稳定地形成下电极和相变层之间的界面的相变存储器件的制造方法
公开(公告)号：US07687310B2
公开(公告)日：2010-03-30
申请号：US11855664
申请日：2007-09-14
申请人： Heon Yong Chang
发明人： Heon Yong Chang
IPC分类号： H01L21/06 , H01L21/44
CPC分类号： H01L45/1683 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1675
摘要： A phase change memory device is manufactured by forming a sacrificial layer and a hard mask layer on a lower electrode; performing a first etching these layers and forming on the lower electrode a first stack pattern having a first width less than a width of the lower electrode; performing a second etching the first stack pattern and forming a second stack pattern having a second width less than the first width; forming an insulation to cover the second stack pattern; CMPing the insulation layer to expose the sacrificial layer; removing the sacrificial layer to define a contact hole; forming a lower electrode contact in the contact hole; and forming a phase change layer and an upper electrode on the insulation layer including the lower electrode contact. By manufacturing the phase change memory device in this manner, the size of the contact hole can be decreased and uniformly defined.
摘要翻译：通过在下电极上形成牺牲层和硬掩模层来制造相变存储器件; 执行第一蚀刻这些层并在下电极上形成具有小于下电极的宽度的第一宽度的第一堆叠图案; 执行第二蚀刻第一堆叠图案并形成具有小于第一宽度的第二宽度的第二堆叠图案; 形成绝缘体以覆盖第二堆叠图案; 对绝缘层进行CMP以露出牺牲层; 去除牺牲层以限定接触孔; 在接触孔中形成下电极接触; 以及在包括下电极接触件的绝缘层上形成相变层和上电极。通过以这种方式制造相变存储器件，可以减小并均匀地限定接触孔的尺寸。

10. 发明授权

US07570512B2 Phase change memory device with reduced unit cell size and improved transistor current flow and method for manufacturing the same 有权
标题翻译：具有减小的单位电池尺寸和改进的晶体管电流的相变存储器件及其制造方法
公开(公告)号：US07570512B2
公开(公告)日：2009-08-04
申请号：US11778141
申请日：2007-07-16
申请人： Heon Yong Chang
发明人： Heon Yong Chang
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/003 , G11C13/004 , G11C2013/0054 , G11C2213/74 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： A phase change memory device includes: a semiconductor substrate having active areas; a pair of word lines formed over the active areas and connected with each other at each end thereof; source areas formed in the respective active areas at both sides of the pair of word lines; drain areas formed in the respective active areas between the word lines of the pair of word lines connected with each other at each end thereof; ground lines and cell selection lines formed so as to make contact with the respective source areas respectively; lower electrodes formed so as to make contact with the drain areas; phase change layers and upper electrodes stacked over the respective lower electrodes; and bit lines formed over upper portion of the active areas so as to make contact to the upper electrodes.
摘要翻译：相变存储器件包括：具有有源区的半导体衬底; 一对字线形成在有效区域上并在其两端相互连接; 源区域形成在该对字线对的两侧的相应有效区域中; 漏极区域形成在其两端彼此连接的一对字线对的字线之间的各有效区域中; 形成的接地线和电池选择线分别与各个源极区域接触; 形成为与漏区接触的下电极; 叠层在相应的下电极上的相变层和上电极; 以及在有源区的上部形成的位线，以便与上电极接触。

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