专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20140190410A1 EQUIPMENT FOR MANUFACTURING SEMICONDUCTOR 审中-公开
标题翻译：制造半导体设备
公开(公告)号：US20140190410A1
公开(公告)日：2014-07-10
申请号：US14235896
申请日：2012-07-31
申请人： Young Dae Kim , Jun Jin Hyon , Sang Ho Woo , Seung Woo Shin , Hai Won Kim
发明人： Young Dae Kim , Jun Jin Hyon , Sang Ho Woo , Seung Woo Shin , Hai Won Kim
IPC分类号： C30B25/10
CPC分类号： C30B25/10 , C30B25/08 , C30B29/06 , C30B35/00 , H01L21/02046 , H01L21/67178 , H01L21/67207 , H01L21/67757
摘要： Provided is an equipment for manufacturing a semiconductor. The equipment for manufacturing a semiconductor includes a cleaning chamber in which a cleaning process is performed on substrates, an epitaxial chamber in which an epitaxial process for forming an epitaxial layer on each of the substrates is performed, and a transfer chamber to which the cleaning chamber and the epitaxial chamber are connected to sides surfaces thereof, the transfer chamber including a substrate handler for transferring the substrates, on which the cleaning process is completed, into the epitaxial chamber.
摘要翻译：提供了一种用于制造半导体的设备。用于制造半导体的设备包括其中对基板进行清洁处理的清洁室，其中执行在每个基板上形成外延层的外延工艺的外延室，以及清洁室并且外延室连接到其侧表面，转移室包括用于将完成清洁处理的基板转移到外延室中的基板处理器。

2. 发明申请

US20130178066A1 METHOD AND APPARATUS FOR MANUFACTURING THREE-DIMENSIONAL-STRUCTURE MEMORY DEVICE 有权
标题翻译：用于制造三维结构存储器件的方法和装置
公开(公告)号：US20130178066A1
公开(公告)日：2013-07-11
申请号：US13823131
申请日：2011-10-06
申请人： Sung Kil Cho , Hai Won Kim , Sang Ho Woo , Seung Woo Shin , Gil Sun Jang , Wan Suk Oh
发明人： Sung Kil Cho , Hai Won Kim , Sang Ho Woo , Seung Woo Shin , Gil Sun Jang , Wan Suk Oh
IPC分类号： H01L21/306
CPC分类号： H01L21/306 , C23C16/4585 , H01L21/02126 , H01L21/02129 , H01L21/02164 , H01L21/0217 , H01L21/02211 , H01L21/02271 , H01L21/30604 , H01L21/31111 , H01L27/11578 , H01L27/11582 , H01L29/66833 , H01L29/7926
摘要： Provided is a method of manufacturing a memory device having a 3-dimensional structure, which includes alternately stacking one or more dielectric layers and one or more sacrificial layers on a substrate, forming a through hole passing through the dielectric layers and the sacrificial layers, forming a pattern filling the through hole, forming an opening passing through the dielectric layers and the sacrificial layers, and supplying an etchant through the opening to remove the sacrificial layers. The stacking of the dielectric layers includes supplying the substrate with one or more gases selected from the group consisting of SiH4, Si2H6, Si3H8, and Si4H10, to deposit a silicon oxide layer. The stacking of the sacrificial layers includes supplying the substrate with one or more gases selected from the group consisting of SiH4, Si2H6, Si3H8, Si4H10, and dichloro silane (SiCl2H2), and ammonia-based gas, to deposit a silicon nitride layer.
摘要翻译：提供一种制造具有三维结构的存储器件的方法，其包括在衬底上交替堆叠一个或多个电介质层和一个或多个牺牲层，形成通过电介质层和牺牲层的通孔，形成填充通孔的图案，形成穿过电介质层和牺牲层的开口，以及通过开口提供蚀刻剂以除去牺牲层。电介质层的堆叠包括向衬底供给选自由SiH 4，Si 2 H 6，Si 3 H 8和Si 4 H 10组成的组中的一种或多种气体，以沉积氧化硅层。牺牲层的堆叠包括向基板供应一种或多种选自SiH 4，Si 2 H 6，Si 3 H 8，Si 4 H 10和二氯硅烷（SiCl 2 H 2）的气体和氨基气体，以沉积氮化硅层。

3. 发明申请

US20120040520A1 ULTRA-FINE-GRAINED POLYSILICON THIN FILM VAPOUR-DEPOSITION METHOD 审中-公开
标题翻译：超细晶粒多晶硅薄膜蒸发沉积法
公开(公告)号：US20120040520A1
公开(公告)日：2012-02-16
申请号：US13266423
申请日：2010-04-12
申请人： Hai Won Kim , Sang Ho Woo , Sung Gil Cho
发明人： Hai Won Kim , Sang Ho Woo , Sung Gil Cho
IPC分类号： H01L21/20
CPC分类号： H01L21/02532 , H01L21/02579 , H01L21/02595 , H01L21/0262
摘要： Provided is a method of depositing an ultra-fine grain polysilicon thin film. The method includes forming a nitrogen atmosphere in a chamber loaded with a substrate, and supplying a source gas into the chamber to deposit a polysilicon thin film on the substrate, in which the source gas includes a silicon-based gas, a nitrogen-based gas, and a phosphorous-based gas. The forming of the nitrogen atmosphere may include supplying a nitrogen-based gas into the chamber.
摘要翻译：提供了沉积超细晶粒多晶硅薄膜的方法。该方法包括在装载有基板的室中形成氮气氛，并将源气体供应到室中以在基板上沉积多晶硅薄膜，其中源气体包括硅基气体，氮气体，和基于磷的气体。氮气氛的形成可以包括将氮基气体供应到室中。

4. 发明申请

US20070264770A1 CAPACITOR FORMING METHOD 审中-公开
标题翻译：电容成型方法
公开(公告)号：US20070264770A1
公开(公告)日：2007-11-15
申请号：US11618796
申请日：2006-12-30
申请人： Keum Bum Lee , Hai Won Kim , Ho Jin Cho , Jun Soo Chang , Eun A. Lee , Dong Su Park
发明人： Keum Bum Lee , Hai Won Kim , Ho Jin Cho , Jun Soo Chang , Eun A. Lee , Dong Su Park
IPC分类号： H01L21/8242 , H01L29/92
CPC分类号： H01L21/3141 , H01L21/02178 , H01L21/02189 , H01L21/022 , H01L21/0228 , H01L21/0234 , H01L27/10852 , H01L28/91
摘要： A method for forming a capacitor includes forming a concave mold over a semiconductor substrate. A storage node is formed on the concave mold. A dielectric layer including a zirconium oxide (ZrO2) layer is deposited over the storage node at a first temperature. A radical pile-up treatment on the dielectric layer is performed in an atmosphere including radicals at a second temperature higher than the first temperature to induce crystallization of the dielectric layer. A plate node is formed over the dielectric layer.
摘要翻译：形成电容器的方法包括在半导体衬底上形成凹模。存储节点形成在凹模上。包含氧化锆（ZrO 2）层的电介质层在第一温度下沉积在存储节点上。在包括自由基的气氛中，在高于第一温度的第二温度下进行介电层上的自由基堆积处理，以诱导电介质层的结晶。在该电介质层上形成一个平板节点。

5. 发明授权

US08937012B2 Production method for semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US08937012B2
公开(公告)日：2015-01-20
申请号：US13814533
申请日：2011-08-30
申请人： Hai Won Kim , Sang Ho Woo , Sung Kil Cho , Gil Sun Jang
发明人： Hai Won Kim , Sang Ho Woo , Sung Kil Cho , Gil Sun Jang
IPC分类号： H01L21/44 , H01L21/02 , H01L21/8238 , H01L21/3205 , H01L29/49 , C01B33/06 , H01L27/115 , H01L29/66 , C23C16/02 , C23C16/04 , C23C16/24 , H01L21/28
CPC分类号： H01L21/02697 , C01B33/06 , C23C16/0227 , C23C16/04 , C23C16/24 , H01L21/28273 , H01L21/28282 , H01L21/32051 , H01L21/823835 , H01L27/11521 , H01L27/11568 , H01L29/4975 , H01L29/66825 , H01L29/66833
摘要： Provided is a production method for a semiconductor device comprising a metal silicide layer. According to one embodiment of the present invention, the production method for a semiconductor device comprises the steps of: forming an insulating layer on a substrate, on which a polysilicon pattern has been formed, in such a way that the polysilicon pattern is exposed; forming a silicon seed layer on the exposed polysilicon pattern that has been selectively exposed with respect to the insulating layer; forming a metal layer on the substrate on which the silicon seed layer has been formed; and forming a metal silicide layer by carrying out a heat treatment on the substrate on which the metal layer has been formed.
摘要翻译：提供了一种包括金属硅化物层的半导体器件的制造方法。根据本发明的一个实施例，半导体器件的制造方法包括以下步骤：在已经形成多晶硅图案的衬底上形成绝缘层，以使多晶硅图案暴露; 在已经相对于绝缘层选择性地暴露的暴露的多晶硅图案上形成硅籽晶层; 在已经形成有硅籽晶层的基板上形成金属层; 以及通过在其上形成有金属层的基板上进行热处理而形成金属硅化物层。

6. 发明申请

US20140209024A1 EQUIPMENT FOR MANUFACTURING SEMICONDUCTOR 审中-公开
标题翻译：制造半导体设备
公开(公告)号：US20140209024A1
公开(公告)日：2014-07-31
申请号：US14235901
申请日：2012-07-31
申请人： Young Dae Kim , Jun Jin Hyon , Sang Ho Woo , Seung Woo Shin , Hai Won Kim
发明人： Young Dae Kim , Jun Jin Hyon , Sang Ho Woo , Seung Woo Shin , Hai Won Kim
IPC分类号： H01L21/67
CPC分类号： H01L21/67184 , C30B25/08 , C30B29/06 , C30B35/005 , H01L21/02046 , H01L21/67051 , H01L21/67178 , H01L21/67757
摘要： Provided is an equipment for manufacturing a semiconductor. The equipment for manufacturing a semiconductor includes a cleaning chamber in which a cleaning process is performed on substrates, an epitaxial chamber in which an epitaxial process for forming an epitaxial layer on each of the substrates is performed, a buffer chamber having a storage space for storing the substrates, and a transfer chamber to which the cleaning chamber, the buffer chamber, and the epitaxial chamber are connected to side surfaces thereof, the transfer chamber comprising a substrate handler for transferring the substrates between the cleaning chamber, the buffer chamber, and the epitaxial chamber. The substrate handler successively transfers the substrates, on which the cleaning process is completed, into the buffer chamber, transfers the substrates stacked within the buffer chamber the epitaxial chamber, and successively transfers the substrates, on which the epitaxial layers are respectively formed, into the buffer chamber.
摘要翻译：提供了一种用于制造半导体的设备。用于制造半导体的设备包括其中对基板进行清洁处理的清洁室，其中执行在每个基板上形成外延层的外延工艺的外延室，具有用于存储的存储空间的缓冲室所述基板和所述清洁室，所述缓冲室和所述外延室连接到其侧表面的传送室，所述传送室包括用于在所述清洁室，所述缓冲室和所述缓冲室之间传送所述基板的基板处理器外延室。衬底处理器将完成清洁处理的衬底连续地传送到缓冲室中，将堆叠在缓冲室内的衬底传送到外延室，并且将分别形成有外延层的衬底依次传送到缓冲室。

7. 发明申请

US20110294284A1 METHOD FOR DEPOSITING ULTRA FINE GRAIN POLYSILICON THIN FILM 审中-公开
标题翻译：沉积超细晶粒多晶硅薄膜的方法
公开(公告)号：US20110294284A1
公开(公告)日：2011-12-01
申请号：US12990628
申请日：2009-04-29
申请人： Hai Won Kim , Sang Ho Woo , Sung Gil Cho , Song Hwan Park , Kyung Soo Jung
发明人： Hai Won Kim , Sang Ho Woo , Sung Gil Cho , Song Hwan Park , Kyung Soo Jung
IPC分类号： H01L21/383 , H01L21/443
CPC分类号： C23C16/24
摘要： According to the present invention, a method for depositing an ultra-fine crystal particle polysilicon thin film supplies a source gas in a chamber loaded with a substrate to deposit a polysilicon thin film on the substrate, wherein the source gas contains a silicon-based gas, a nitrogen-based gas and a phosphorous-based gas. The mixture ratio of the nitrogen-based gas to the silicon-based gas among the source gas may be 0.03 or lower (but, excluding zero). Nitrogen in the thin film may be 11.3 atomic percent or lower (but, excluding zero).
摘要翻译：根据本发明，用于沉积超细晶粒多晶硅薄膜的方法在负载有衬底的室中提供源气体，以在衬底上沉积多晶硅薄膜，其中源气体包含硅基气体，氮系气体和磷系气体。源气体中的氮系气体与硅系气体的混合比可以为0.03以下（但不包括零）。薄膜中的氮可以为11.3原子％以下（但不包括零）。

8. 发明授权

US07463476B2 Capacitor with nanotubes and method for fabricating the same 失效
标题翻译：纳米管电容器及其制造方法
公开(公告)号：US07463476B2
公开(公告)日：2008-12-09
申请号：US11148057
申请日：2005-06-07
申请人： Eun-A Lee , Ho-Jin Cho , Young-Dae Kim , Jun-Soo Chang , Su-Jin Chae , Hai-Won Kim
发明人： Eun-A Lee , Ho-Jin Cho , Young-Dae Kim , Jun-Soo Chang , Su-Jin Chae , Hai-Won Kim
IPC分类号： H01G4/06
CPC分类号： B82Y10/00 , H01G4/005 , H01G4/33 , H01L23/5223 , H01L27/10852 , H01L28/82 , H01L28/84 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： A capacitor with nanotubes and a method for fabricating the same are provided. The capacitor includes: a lower electrode including a patterned conductive layer and a plurality of nanotubes formed on the patterned conductive layer in the shape of whiskers without using a catalytic layer; a dielectric layer formed on the lower electrode; and an upper electrode formed on the dielectric layer. The method includes the steps of: forming a conductive layer for forming a lower electrode; forming a nanotube array including a plurality of nanotubes formed on the conductive layer without using a catalytic layer; forming a dielectric layer on the nanotube array; and forming an upper electrode on the dielectric layer.
摘要翻译：提供了一种具有纳米管的电容器及其制造方法。所述电容器包括：下电极，其包括图案化导电层和形成在所述图案化导电层上的多个纳米管，所述多个纳米管不需要使用催化剂层; 形成在下电极上的电介质层; 以及形成在电介质层上的上电极。该方法包括以下步骤：形成用于形成下电极的导电层; 在不使用催化剂层的情况下形成包括形成在所述导电层上的多个纳米管的纳米管阵列; 在纳米管阵列上形成介电层; 以及在所述电介质层上形成上电极。

9. 发明申请

US20060221548A1 Capacitor with nanotubes and method for fabricating the same 失效
公开(公告)号：US20060221548A1
公开(公告)日：2006-10-05
申请号：US11148057
申请日：2005-06-07
申请人： Eun-A Lee , Ho-Jin Cho , Young-Dae Kim , Jun-Soo Chang , Su-Jin Chae , Hai-Won Kim
发明人： Eun-A Lee , Ho-Jin Cho , Young-Dae Kim , Jun-Soo Chang , Su-Jin Chae , Hai-Won Kim
IPC分类号： H01G4/228
CPC分类号： B82Y10/00 , H01G4/005 , H01G4/33 , H01L23/5223 , H01L27/10852 , H01L28/82 , H01L28/84 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： A capacitor with nanotubes and a method for fabricating the same are provided. The capacitor includes: a lower electrode including a patterned conductive layer and a plurality of nanotubes formed on the patterned conductive layer in the shape of whiskers without using a catalytic layer; a dielectric layer formed on the lower electrode; and an upper electrode formed on the dielectric layer. The method includes the steps of: forming a conductive layer for forming a lower electrode; forming a nanotube array including a plurality of nanotubes formed on the conductive layer without using a catalytic layer; forming a dielectric layer on the nanotube array; and forming an upper electrode on the dielectric layer.

10. 发明授权

US06869874B2 Method for fabricating contact plug with low contact resistance 失效
标题翻译：具有低接触电阻的接触插头的制造方法
公开(公告)号：US06869874B2
公开(公告)日：2005-03-22
申请号：US10330303
申请日：2002-12-30
申请人： Hai-Won Kim , Su-Jin Chae
发明人： Hai-Won Kim , Su-Jin Chae
IPC分类号： H01L21/28 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L21/44
CPC分类号： H01L27/10888 , H01L21/76897
摘要： The present invention provides a method for forming a contact plug of a semiconductor device with a low contact resistance. The inventive method includes the steps of: forming a contact hole in an inter-layer insulating layer formed on a silicon substrate; removing a native oxide layer formed in the contact hole; forming a single crystal silicon layer on a surface of the silicon substrate in the contact hole, wherein the single crystal silicon layer is formed by an epitaxial growth performed at a first reaction chamber of which pressure is maintained less than approximately 10−6 Torr; and filling the contact hole with polysilicon, wherein the polysilicon layer is formed at a second reaction chamber.
摘要翻译：本发明提供一种形成具有低接触电阻的半导体器件的接触插塞的方法。本发明的方法包括以下步骤：在形成在硅衬底上的层间绝缘层中形成接触孔; 去除形成在接触孔中的自然氧化物层; 在所述接触孔中的所述硅衬底的表面上形成单晶硅层，其中所述单晶硅层通过外延生长形成，所述外延生长在第一反应室中进行，其中所述第一反应室的压力保持在小于约10 -6 Torr ; 以及用多晶硅填充所述接触孔，其中所述多晶硅层在第二反应室处形成。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式