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1. 发明申请

US20080160699A1 Method for Fabricating Semiconductor Device Having Bulb-Type Recessed Channel 审中-公开
标题翻译：制造具有灯泡型嵌入式通道的半导体器件的方法
公开(公告)号：US20080160699A1
公开(公告)日：2008-07-03
申请号：US11759930
申请日：2007-06-07
申请人： Min Yong Lee , Yong Seok Eun , Dong Su Park , Jun Soo Chang
发明人： Min Yong Lee , Yong Seok Eun , Dong Su Park , Jun Soo Chang
IPC分类号： H01L21/336
CPC分类号： H01L29/66537 , H01L21/26586 , H01L29/66621 , H01L29/78
摘要： A method for fabricating a semiconductor device having a bulb-type recessed channel including forming a mask layer on the semiconductor substrate to expose a region where a trench for a bulb-type recessed channel can be formed, forming the trench in the semiconductor substrate, implanting dopant ions in three-dimensional radial directions with a predetermined tilt angle in the exposed region of the semiconductor substrate, removing the mask layer, forming a gate stack in the region including the trench, and forming a source/drain in the semiconductor substrate.
摘要翻译：一种制造具有灯泡型凹槽的半导体器件的方法，包括在半导体衬底上形成掩模层，以暴露可形成用于灯泡型凹槽的沟槽的区域，在半导体衬底中形成沟槽，掺杂剂离子在半导体衬底的暴露区域中具有预定倾斜角的三维径向方向，去除掩模层，在包括沟槽的区域中形成栅叠层，并在半导体衬底中形成源/漏。

2. 发明授权

US07859041B2 Gate structure of semiconductor device 有权
标题翻译：半导体器件的栅极结构
公开(公告)号：US07859041B2
公开(公告)日：2010-12-28
申请号：US12485649
申请日：2009-06-16
申请人： Young Bog Kim , Jun Soo Chang , Min Yong Lee , Yong Seok Eun
发明人： Young Bog Kim , Jun Soo Chang , Min Yong Lee , Yong Seok Eun
IPC分类号： H01L29/76
CPC分类号： H01L27/10876 , H01L21/2815 , H01L29/66636
摘要： A gate structure of a semiconductor device comprising a silicon substrate having a field oxide film, a plurality of gates formed by sequentially stacking a first gate dielectric film, a first gate conductive film, and a gate silicide film on the silicon substrate. a thermal oxide film formed on a side of the first gate conductive film, a plurality of trenches formed between the gates, a second gate oxide film formed on an interior wall of each trench; and a second conductive film formed in a spacer shape on a predetermined region of the second gate oxide film, and on a side of the first gate conductive film, the gate silicide film and the thermal oxide film.
摘要翻译：一种半导体器件的栅极结构，包括具有场氧化物膜的硅衬底，通过在硅衬底上依次层叠第一栅极电介质膜，第一栅极导电膜和栅极硅化物膜而形成的多个栅极。形成在第一栅极导电膜的一侧的热氧化膜，形成在栅极之间的多个沟槽，形成在每个沟槽的内壁上的第二栅极氧化膜; 以及在所述第二栅极氧化膜的预定区域上形成间隔物形状的第二导电膜，以及在所述第一栅极导电膜，所述栅极硅化物膜和所述热氧化物膜的一侧。

3. 发明申请

US20090256209A1 Gate Structure of Semiconductor Device 有权
标题翻译：半导体器件的栅极结构
公开(公告)号：US20090256209A1
公开(公告)日：2009-10-15
申请号：US12485649
申请日：2009-06-16
申请人： Young Bog Kim , Jun Soo Chang , Min Yong Lee , Yong Seok Eun
发明人： Young Bog Kim , Jun Soo Chang , Min Yong Lee , Yong Seok Eun
IPC分类号： H01L27/088
CPC分类号： H01L27/10876 , H01L21/2815 , H01L29/66636
摘要： A gate structure of a semiconductor device comprising a silicon substrate having a field oxide film, a plurality of gates formed by sequentially stacking a first gate dielectric film, a first gate conductive film, and a gate silicide film on the silicon substrate. a thermal oxide film formed on a side of the first gate conductive film, a plurality of trenches formed between the gates, a second gate oxide film formed on an interior wall of each trench; and a second conductive film formed in a spacer shape on a predetermined region of the second gate oxide film, and on a side of the first gate conductive film, the gate silicide film and the thermal oxide film.
摘要翻译：一种半导体器件的栅极结构，包括具有场氧化物膜的硅衬底，通过在硅衬底上依次层叠第一栅极电介质膜，第一栅极导电膜和栅极硅化物膜而形成的多个栅极。形成在第一栅极导电膜的一侧的热氧化膜，形成在栅极之间的多个沟槽，形成在每个沟槽的内壁上的第二栅极氧化膜; 以及在所述第二栅极氧化膜的预定区域上形成间隔物形状的第二导电膜，以及在所述第一栅极导电膜，所述栅极硅化物膜和所述热氧化物膜的一侧。

4. 发明授权

US07563673B2 Method of forming gate structure of semiconductor device 失效
标题翻译：形成半导体器件栅极结构的方法
公开(公告)号：US07563673B2
公开(公告)日：2009-07-21
申请号：US11268846
申请日：2005-11-08
申请人： Young Bog Kim , Jun Soo Chang , Min Yong Lee , Yong Seok Eun
发明人： Young Bog Kim , Jun Soo Chang , Min Yong Lee , Yong Seok Eun
IPC分类号： H01L21/336
CPC分类号： H01L27/10876 , H01L21/2815 , H01L29/66636
摘要： Disclosed herein is a method for forming a gate structure of a semiconductor device. The method comprises forming a plurality of gates including a first gate dielectric film, a first gate conductive film, and a gate silicide film sequentially stacked on a silicon substrate having a field oxide film, forming a thermal oxide film on a side of the first gate conductive film, etching the silicon substrate exposed between the plurality of gates to a predetermined depth to form a plurality of trenches, forming a second gate oxide film on the interior wall of the trenches, and forming a second gate conductive film in a spacer shape on a predetermined region of the second gate oxide film, and on a side of the first gate conductive film, the gate silicide film, and the thermal oxide film.
摘要翻译：本文公开了一种用于形成半导体器件的栅极结构的方法。该方法包括形成多个栅极，其包括依次层叠在具有场氧化膜的硅基板上的第一栅极电介质膜，第一栅极导电膜和栅极硅化物膜，在第一栅极的一侧形成热氧化膜将暴露在所述多个栅极之间的硅衬底蚀刻到预定深度以形成多个沟槽，在所述沟槽的内壁上形成第二栅极氧化膜，并且形成间隔物形状的第二栅极导电膜第二栅极氧化膜的预定区域，以及第一栅极导电膜，栅极硅化物膜和热氧化物膜的一侧。

5. 发明申请

US20070264770A1 CAPACITOR FORMING METHOD 审中-公开
标题翻译：电容成型方法
公开(公告)号：US20070264770A1
公开(公告)日：2007-11-15
申请号：US11618796
申请日：2006-12-30
申请人： Keum Bum Lee , Hai Won Kim , Ho Jin Cho , Jun Soo Chang , Eun A. Lee , Dong Su Park
发明人： Keum Bum Lee , Hai Won Kim , Ho Jin Cho , Jun Soo Chang , Eun A. Lee , Dong Su Park
IPC分类号： H01L21/8242 , H01L29/92
CPC分类号： H01L21/3141 , H01L21/02178 , H01L21/02189 , H01L21/022 , H01L21/0228 , H01L21/0234 , H01L27/10852 , H01L28/91
摘要： A method for forming a capacitor includes forming a concave mold over a semiconductor substrate. A storage node is formed on the concave mold. A dielectric layer including a zirconium oxide (ZrO2) layer is deposited over the storage node at a first temperature. A radical pile-up treatment on the dielectric layer is performed in an atmosphere including radicals at a second temperature higher than the first temperature to induce crystallization of the dielectric layer. A plate node is formed over the dielectric layer.
摘要翻译：形成电容器的方法包括在半导体衬底上形成凹模。存储节点形成在凹模上。包含氧化锆（ZrO 2）层的电介质层在第一温度下沉积在存储节点上。在包括自由基的气氛中，在高于第一温度的第二温度下进行介电层上的自由基堆积处理，以诱导电介质层的结晶。在该电介质层上形成一个平板节点。

6. 发明申请

US20080242045A1 METHOD FOR FABRICATING TRENCH DIELECTRIC LAYER IN SEMICONDUCTOR DEVICE 审中-公开
标题翻译：用于在半导体器件中制造TRENCH介电层的方法
公开(公告)号：US20080242045A1
公开(公告)日：2008-10-02
申请号：US11951965
申请日：2007-12-06
申请人： Keum Bum LEE , Dong Su Park , Jun Soo Chang , Eun A Lee
发明人： Keum Bum LEE , Dong Su Park , Jun Soo Chang , Eun A Lee
IPC分类号： H01L21/62
CPC分类号： H01L21/76232
摘要： A method for fabricating a trench dielectric layer in a semiconductor device is provided. A trench is formed in a semiconductor substrate and a liner nitride layer is then formed on an inner wall of the trench. A liner oxide layer formed on the liner nitride layer is nitrified in order to protect the liner nitride layer from being exposed. Subsequently, the trench is filled with one or more dielectric layers.
摘要翻译：提供一种在半导体器件中制造沟槽电介质层的方法。在半导体衬底中形成沟槽，然后在沟槽的内壁上形成衬里氮化物层。形成在衬里氮化物层上的衬里氧化物层被硝化以保护衬里氮化物层免受暴露。随后，沟槽被一个或多个电介质层填充。

7. 发明授权

US07300852B2 Method for manufacturing capacitor of semiconductor element 失效
标题翻译：制造半导体元件电容器的方法
公开(公告)号：US07300852B2
公开(公告)日：2007-11-27
申请号：US11089122
申请日：2005-03-24
申请人： Ho Jin Cho , Jun Soo Chang , Eun A. Lee , Su Jin Chae , Young Dae Kim
发明人： Ho Jin Cho , Jun Soo Chang , Eun A. Lee , Su Jin Chae , Young Dae Kim
IPC分类号： H01L21/20
CPC分类号： H01L21/02312 , H01L21/02178 , H01L21/02181 , H01L21/022 , H01L21/3144 , H01L28/60
摘要： A method for manufacturing a capacitor of a semiconductor element including: forming a bottom electrode of the capacitor on a semiconductor substrate; performing rapid thermal nitrification (RTN) on the upper surface of the bottom electrode; performing a thermal process on the obtained structure having the bottom electrode in a furnace under a nitride atmosphere to eliminate stress generated by the RTN; forming Al2O3 and HfO2 dielectric films on the nitrified bottom electrode; and forming a plate electrode of the capacitor on the Al2O3 and HfO2 dielectric films. The thermal process is performed after the RTN performed on the surface of the bottom electrode, so that stress, generated from the RTN, is alleviated, thereby allowing the capacitor to obtain a high capacitance and lowering leakage current.
摘要翻译：一种制造半导体元件的电容器的方法，包括：在半导体衬底上形成电容器的底部电极; 在底电极的上表面进行快速热硝化（RTN）; 对所获得的在氮化物气氛下的炉中具有底部电极的结构进行热处理以消除由RTN产生的应力; 在硝化的底部电极上形成Al 2 O 3 N 3和HfO 2 N 2电介质膜; 以及在Al 2 O 3和HfO 2 N 2电介质膜上形成电容器的平板电极。在底电极表面进行RTN之后进行热处理，从而可以减轻由RTN产生的应力，从而使电容器获得高电容，降低漏电流。

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