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1. 发明授权

US06856169B2 Method and apparatus for signal reception using ground termination and/or non-ground termination 有权
标题翻译：使用接地端接和/或非接地端接信号接收的方法和装置
公开(公告)号：US06856169B2
公开(公告)日：2005-02-15
申请号：US10435292
申请日：2003-05-09
申请人： Yohan U. Frans , Nhat M. Nguyen , Yueyong Wang
发明人： Yohan U. Frans , Nhat M. Nguyen , Yueyong Wang
IPC分类号： H03K5/00 , H03K5/003 , H03K5/01 , H03K19/003 , H03K19/0175 , H04L25/02
CPC分类号： H04L25/0292 , H03K5/003 , H04L25/0272
摘要： Receiving units with inputs that may be ground-terminated and with inputs that are selectively ground-terminated or non-ground terminated are enabled with signal level shifting and a termination mode selection input. In a first exemplary implementation, a receiving unit is capable of having ground-terminated inputs. However, common mode voltage of the signal that is input to decoding data recovery circuitry is above ground because the input signal may be level shifted in between the ground-terminated inputs and the decoding data recovery circuitry. In a second exemplary implementation, a mode selection is accomplished by switching a voltage divider into operation and bypassing a level shifter for a non-ground terminated mode. For a ground terminated mode, the voltage divider is switched out of operation and the level shifter is switched into operation for its signal output to be decoded. Pre-amplification may also be employed to improve signal strength.
摘要翻译：具有可能被接地端接的输入和具有选择性地接地或非接地端接的输入的接收单元使能信号电平移位和终端模式选择输入。在第一示例性实施方式中，接收单元能够具有接地端接的输入。然而，输入到解码数据恢复电路的信号的共模电压高于地，因为输入信号可能在接地端接输入和解码数据恢复电路之间的电平移位。在第二示例性实施方案中，通过将分压器切换到操作中并且绕过非接地端接模式的电平移位器来实现模式选择。对于接地端接模式，分压器切换到运行状态，电平转换器切换到其信号输出进行操作，进行解码。也可以使用预扩增来提高信号强度。

2. 发明授权

US07102390B2 Method and apparatus for signal reception using ground termination and/or non-ground termination 有权
标题翻译：使用接地端接和/或非接地端接信号接收的方法和装置
公开(公告)号：US07102390B2
公开(公告)日：2006-09-05
申请号：US11058088
申请日：2005-02-15
申请人： Yohan U. Frans , Nhat M. Nguyen , Yueyong Wang
发明人： Yohan U. Frans , Nhat M. Nguyen , Yueyong Wang
IPC分类号： H03K19/0175
CPC分类号： H04L25/0292 , H03K5/003 , H04L25/0272
摘要： Receiving units with inputs that may be ground-terminated and with inputs that are selectively ground-terminated or non-ground terminated are enabled with signal level shifting and a termination mode selection input. In a first exemplary implementation, a receiving unit is capable of having ground-terminated inputs. However, common mode voltage of the signal that is input to decoding data recovery circuitry is above ground because the input signal may be level shifted in between the ground-terminated inputs and the decoding data recovery circuitry. In a second exemplary implementation, a mode selection is accomplished by switching a voltage divider into operation and bypassing a level shifter for a non-ground terminated mode. For a ground terminated mode, the voltage divider is switched out of operation and the level shifter is switched into operation for its signal output to be decoded. Pre-amplification may also be employed to improve signal strength.
摘要翻译：具有可能被接地端接的输入和具有选择性地接地或非接地端接的输入的接收单元使能信号电平移位和终端模式选择输入。在第一示例性实施方式中，接收单元能够具有接地端接的输入。然而，输入到解码数据恢复电路的信号的共模电压高于地，因为输入信号可能在接地端接输入和解码数据恢复电路之间的电平移位。在第二示例性实施方案中，通过将分压器切换到操作中并且绕过非接地端接模式的电平移位器来实现模式选择。对于接地端接模式，分压器切换到运行状态，电平转换器切换到其信号输出进行操作，进行解码。也可以使用预扩增来提高信号强度。

3. 发明授权

US07183805B2 Method and apparatus for multi-mode driver 有权
标题翻译：多模式驱动程序的方法和装置
公开(公告)号：US07183805B2
公开(公告)日：2007-02-27
申请号：US11385234
申请日：2006-03-20
申请人： Yueyong Wang , Barry W. Daly , Nhat M. Nguyen , Yohan U. Frans
发明人： Yueyong Wang , Barry W. Daly , Nhat M. Nguyen , Yohan U. Frans
IPC分类号： H03K19/094
CPC分类号： H04L25/0274 , H03K19/018585 , H04L25/0282 , H04L25/10
摘要： Multi-mode signal drivers with a single output circuit that may be controlled using a mode select input and that may include a common mode (CM) voltage compensation mechanism are described. In a first exemplary implementation, a multi-mode output driver is adapted to drive signals from a single output circuit according to at least two modes, such as a current mode logic (CML) signaling mode and a low voltage differential signaling (LVDS) mode. In a second exemplary implementation, a circuit comprises a quasi-LVDS output driver in which a differential amplifier circuit is connected in series with an adjustable resistive element and a programmable current source. In a third exemplary implementation, a CM voltage of an output driver circuit changes with changes to a programmable bias current. To compensate, a feedback mechanism provides a compensation signal to a variable resistive element of the output driver circuit to maintain a desired CM voltage.
摘要翻译：描述具有可以使用模式选择输入并且可以包括共模（CM）电压补偿机制的单个输出电路的多模式信号驱动器。在第一示例性实施例中，多模式输出驱动器适于根据至少两种模式来驱动来自单个输出电路的信号，例如电流模式逻辑（CML）信令模式和低电压差分信号（LVDS）模式。在第二示例性实现中，电路包括准LVDS输出驱动器，其中差分放大器电路与可调电阻元件和可编程电流源串联连接。在第三示例性实施方案中，输出驱动器电路的CM电压随着可编程偏置电流的改变而改变。为了补偿，反馈机构向输出驱动器电路的可变电阻元件提供补偿信号，以维持期望的CM电压。

4. 发明授权

US07061273B2 Method and apparatus for multi-mode driver 失效
公开(公告)号：US07061273B2
公开(公告)日：2006-06-13
申请号：US10456303
申请日：2003-06-06
申请人： Yueyong Wang , Barry W. Daly , Nhat M. Nguyen , Yohan U. Frans
发明人： Yueyong Wang , Barry W. Daly , Nhat M. Nguyen , Yohan U. Frans
IPC分类号： H03K19/094
CPC分类号： H04L25/0274 , H03K19/018585 , H04L25/0282 , H04L25/10
摘要： Multi-mode signal drivers with a single output circuit that may be controlled using a mode select input and that may include a common mode (CM) voltage compensation mechanism are described. In a first exemplary implementation, a multi-mode output driver is adapted to drive signals from a single output circuit according to at least two modes, such as a current mode logic (CML) signaling mode and a low voltage differential signaling (LVDS) mode. In a second exemplary implementation, a circuit comprises a quasi-LVDS output driver in which a differential amplifier circuit is connected in series with an adjustable resistive element and a programmable current source. In a third exemplary implementation, a CM voltage of an output driver circuit changes with changes to a programmable bias current. To compensate, a feedback mechanism provides a compensation signal to a variable resistive element of the output driver circuit to maintain a desired CM voltage.

5. 发明申请

US20130148709A1 Interface with Variable Data Rate 有权
公开(公告)号：US20130148709A1
公开(公告)日：2013-06-13
申请号：US13633076
申请日：2012-10-01
申请人： Yohan U. Frans , Hae-Chang Lee , Brian S. Leibowitz , Simon Li , Nhat M. Nguyen
发明人： Yohan U. Frans , Hae-Chang Lee , Brian S. Leibowitz , Simon Li , Nhat M. Nguyen
IPC分类号： H04L25/02
CPC分类号： G06F13/4286 , G06F13/385 , G06F13/4068 , H04L1/0002 , H04L1/0015 , H04L1/203 , H04L1/205 , H04L1/243 , H04L5/1446 , H04L25/0262 , H04L25/0292 , Y02D50/10
摘要： A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.

6. 发明授权

US08279948B2 Interface with variable data rate 有权
标题翻译：具有可变数据速率的接口
公开(公告)号：US08279948B2
公开(公告)日：2012-10-02
申请号：US12518781
申请日：2007-12-10
申请人： Yohan U. Frans , Hae-Chang Lee , Brian S. Leibowitz , Simon Li , Nhat M. Nguyen
发明人： Yohan U. Frans , Hae-Chang Lee , Brian S. Leibowitz , Simon Li , Nhat M. Nguyen
IPC分类号： H04B3/00
CPC分类号： G06F13/4286 , G06F13/385 , G06F13/4068 , H04L1/0002 , H04L1/0015 , H04L1/203 , H04L1/205 , H04L1/243 , H04L5/1446 , H04L25/0262 , H04L25/0292 , Y02D50/10
摘要： A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined errorrate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.
摘要翻译：一种设备包括耦合到节点的发射器，其中节点将耦合到有线链路。发射机具有多种操作模式，包括校准模式，其中根据有线链路以预定的错误率对应的电压余量来确定有线链路上的通信数据速率的范围。通信数据速率的范围包括最大数据速率，其可以是初始数据速率的非整数倍。

7. 发明申请

US20100103994A1 Interface With Variable Data Rate 有权
标题翻译：可变数据速率接口
公开(公告)号：US20100103994A1
公开(公告)日：2010-04-29
申请号：US12518781
申请日：2007-12-10
申请人： Yohan U. Frans , Hae-Chang Lee , Brian S. Leibowitz , Simon Li , Nhat M. Nguyen
发明人： Yohan U. Frans , Hae-Chang Lee , Brian S. Leibowitz , Simon Li , Nhat M. Nguyen
IPC分类号： H04B17/00 , H04B1/38
CPC分类号： G06F13/4286 , G06F13/385 , G06F13/4068 , H04L1/0002 , H04L1/0015 , H04L1/203 , H04L1/205 , H04L1/243 , H04L5/1446 , H04L25/0262 , H04L25/0292 , Y02D50/10
摘要： A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined errorrate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.
摘要翻译：一种设备包括耦合到节点的发射器，其中节点将耦合到有线链路。发射机具有多种操作模式，包括校准模式，其中根据有线链路以预定的错误率对应的电压余量来确定有线链路上的通信数据速率的范围。通信数据速率的范围包括最大数据速率，其可以是初始数据速率的非整数倍。

8. 发明授权

US06539072B1 Delay locked loop circuitry for clock delay adjustment 有权
标题翻译：延迟锁定环电路，用于时钟延迟调整
公开(公告)号：US06539072B1
公开(公告)日：2003-03-25
申请号：US09524402
申请日：2000-03-13
申请人： Kevin S. Donnelly , Pak Shing Chau , Mark A. Horowitz , Thomas H. Lee , Mark G. Johnson , Benedict C. Lau , Leung Yu , Bruno W. Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Vi Tran , Donald C. Stark , Nhat M. Nguyen
发明人： Kevin S. Donnelly , Pak Shing Chau , Mark A. Horowitz , Thomas H. Lee , Mark G. Johnson , Benedict C. Lau , Leung Yu , Bruno W. Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Vi Tran , Donald C. Stark , Nhat M. Nguyen
IPC分类号： H04L700
CPC分类号： H03K5/133 , G06F1/10 , G11C7/22 , G11C7/222 , H03K5/2481 , H03K2005/00026 , H03K2005/00032 , H03K2005/00052 , H03K2005/00208 , H03L7/07 , H03L7/0805 , H03L7/0812 , H03L7/0814 , H04L7/0008 , H04L7/0025 , H04L7/0037
摘要： Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used in the path of the delayed output clock or the output clock.
摘要翻译：延迟锁定环电路，用于在一对时钟之间产生预定的相位关系。第一延迟锁定环包括布置在链中的延迟元件，所述链接收输入时钟，并且从每个延迟元件产生一组相位矢量，每组相移向量从相邻矢量移位单位延迟。第一延迟锁定环路使用延迟调整信号来调整延迟链中的单元延迟，使得相位矢量跨越输入时钟的预定相移。第二延迟锁定环路从第一延迟锁定环路中选择一对相对于输入时钟相位的相位矢量。相位插值器接收所选择的一对矢量，并产生输出时钟和延迟输出时钟，延迟量由第一延迟锁定环电路的延迟调整信号控制。相位检测器将延迟的输出时钟与输入时钟进行比较，并根据相位比较调节相位内插器，使得延迟输出时钟的相位与输入时钟同相。结果，在输出时钟和输入时钟之间存在预定的相位关系，相位关系是输出时钟和延迟的输出时钟之间的延迟量。根据在延迟输出时钟或输出时钟的路径中使用的单位延迟数，输入和输出时钟之间的不同相位关系是可能的。

9. 发明授权

US5532655A Method and apparatus for AC/DC signal multiplexing 失效
标题翻译：用于AC / DC信号复用的方法和装置
公开(公告)号：US5532655A
公开(公告)日：1996-07-02
申请号：US393634
申请日：1995-02-24
申请人： Nhat M. Nguyen , Kevin J. Negus
发明人： Nhat M. Nguyen , Kevin J. Negus
IPC分类号： H01L25/00 , H01L21/822 , H01L27/04 , H03F1/02 , H03F3/189 , H03F3/195 , H03F3/347 , H03G3/10 , H03H1/02 , H03H7/46
CPC分类号： H03H7/46 , H03F1/0283 , H03F3/195 , H03F3/347
摘要： A method for using the same input/output pin on an integrated circuit ("IC") for both a high frequency AC signal and a DC signal simultaneously and a first circuit means to accomplish this multiplexing is disclosed. The circuit topology comprises a first and second capacitor, coupled between the AC signal input and the AC signal output. A first and second resistor are coupled to the same input/output pin as the capacitors but between the two capacitors and respectively to a DC signal input and DC signal output. The DC signal path thus lies between the two capacitors and sees them as open circuits, while the AC signal path sees the two resistors as open circuits and the capacitors as short circuits.
摘要翻译：公开了一种在用于高频交流信号和直流信号的集成电路（“IC”）上同时使用相同的输入/输出引脚的方法和实现该多路复用的第一电路装置。电路拓扑包括耦合在AC信号输入和AC信号输出之间的第一和第二电容器。第一和第二电阻器耦合到与电容器相同的输入/输出引脚，但是耦合到两个电容器之间，并分别耦合到DC信号输入和DC信号输出。因此，DC信号路径位于两个电容器之间，并将其视为开路，而AC信号路径将两个电阻看作开路，电容器作为短路。

10. 发明授权

US07084681B2 PLL lock detection circuit using edge detection and a state machine 失效
标题翻译： PLL锁定检测电路采用边缘检测和状态机
公开(公告)号：US07084681B2
公开(公告)日：2006-08-01
申请号：US11088152
申请日：2005-03-23
申请人： Michael Green , Nhat M. Nguyen , Yohan Frans , Dennis Kim , Todd Bystrom
发明人： Michael Green , Nhat M. Nguyen , Yohan Frans , Dennis Kim , Todd Bystrom
IPC分类号： H03L7/06
CPC分类号： H03D13/003
摘要： A lock detection circuit operatively associated with a phase-locked loop indicates when a feedback clock signal is locked to a reference clock signal. The lock detection circuit counts the number of rising and falling edges of the feedback clock signal that are detected between rising edges of the reference clock cycle. The lock detection circuit counts the number of consecutive valid cycles of the reference clock signal during which a single rising edge and a single falling edge of the feedback clock signal are detected. Lock detection circuit uses a state machine to assert a lock signal when the number of consecutive valid cycles counted exceeds a predetermined number. Where the lock detection circuit indicates locked signals and then detects a reference clock cycle that is not valid, the lock detection circuit continues to indicate lock if the next reference clock cycle is valid relative to a skewed feedback clock signal.
摘要翻译：与锁相环可操作地相关联的锁定检测电路指示何时将反馈时钟信号锁定到参考时钟信号。锁定检测电路对在参考时钟周期的上升沿之间检测到的反馈时钟信号的上升沿和下降沿的数量进行计数。锁定检测电路对在其中检测到反馈时钟信号的单个上升沿和单个下降沿的参考时钟信号的连续有效周期的数量进行计数。当连续的有效周期数超过预定数量时，锁定检测电路使用状态机来声明锁定信号。如果锁定检测电路指示锁定信号，然后检测到无效的参考时钟周期，则如果下一个参考时钟周期相对于偏斜反馈时钟信号有效，则锁定检测电路继续指示锁定。

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