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1. 发明授权

US07308065B2 Delay locked loop circuitry for clock delay adjustment 失效
标题翻译：延迟锁定环电路，用于时钟延迟调整
公开(公告)号：US07308065B2
公开(公告)日：2007-12-11
申请号：US11406557
申请日：2006-04-18
申请人： Kevin S. Donnelly , Pak Shing Chau , Mark A. Horowitz , Thomas H. Lee , Mark G. Johnson , Benedict C. Lau , Leung Yu , Bruno W. Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Vi Tran , Donald C. Stark , Nhat M. Nguyen
发明人： Kevin S. Donnelly , Pak Shing Chau , Mark A. Horowitz , Thomas H. Lee , Mark G. Johnson , Benedict C. Lau , Leung Yu , Bruno W. Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Vi Tran , Donald C. Stark , Nhat M. Nguyen
IPC分类号： H03D3/24 , H03L7/06
CPC分类号： H03K5/133 , G06F1/10 , G11C7/22 , G11C7/222 , H03K5/2481 , H03K2005/00026 , H03K2005/00032 , H03K2005/00052 , H03K2005/00208 , H03L7/07 , H03L7/0805 , H03L7/0812 , H03L7/0814 , H04L7/0008 , H04L7/0025 , H04L7/0037
摘要： A receiver adapted to be coupled to a data bus and configured to receive data in accordance with a receive clock includes first and second delay-locked loops. The first delay-locked loop is configured to generate a plurality of phase vectors from a first reference clock, and the second delay-locked loop is coupled to the first delay-locked loop and configured to generate the receive clock from at least one phase vector selected from the plurality of phase vectors and a second reference clock.
摘要翻译：适于耦合到数据总线并被配置为根据接收时钟接收数据的接收机包括第一和第二延迟锁定环路。第一延迟锁定环路被配置为从第一参考时钟产生多个相位矢量，并且第二延迟锁定环路耦合到第一延迟锁定环路并且被配置为从至少一个相位矢量生成接收时钟从所述多个相位矢量中选择并具有第二参考时钟。

2. 发明授权

US07102390B2 Method and apparatus for signal reception using ground termination and/or non-ground termination 有权
标题翻译：使用接地端接和/或非接地端接信号接收的方法和装置
公开(公告)号：US07102390B2
公开(公告)日：2006-09-05
申请号：US11058088
申请日：2005-02-15
申请人： Yohan U. Frans , Nhat M. Nguyen , Yueyong Wang
发明人： Yohan U. Frans , Nhat M. Nguyen , Yueyong Wang
IPC分类号： H03K19/0175
CPC分类号： H04L25/0292 , H03K5/003 , H04L25/0272
摘要： Receiving units with inputs that may be ground-terminated and with inputs that are selectively ground-terminated or non-ground terminated are enabled with signal level shifting and a termination mode selection input. In a first exemplary implementation, a receiving unit is capable of having ground-terminated inputs. However, common mode voltage of the signal that is input to decoding data recovery circuitry is above ground because the input signal may be level shifted in between the ground-terminated inputs and the decoding data recovery circuitry. In a second exemplary implementation, a mode selection is accomplished by switching a voltage divider into operation and bypassing a level shifter for a non-ground terminated mode. For a ground terminated mode, the voltage divider is switched out of operation and the level shifter is switched into operation for its signal output to be decoded. Pre-amplification may also be employed to improve signal strength.
摘要翻译：具有可能被接地端接的输入和具有选择性地接地或非接地端接的输入的接收单元使能信号电平移位和终端模式选择输入。在第一示例性实施方式中，接收单元能够具有接地端接的输入。然而，输入到解码数据恢复电路的信号的共模电压高于地，因为输入信号可能在接地端接输入和解码数据恢复电路之间的电平移位。在第二示例性实施方案中，通过将分压器切换到操作中并且绕过非接地端接模式的电平移位器来实现模式选择。对于接地端接模式，分压器切换到运行状态，电平转换器切换到其信号输出进行操作，进行解码。也可以使用预扩增来提高信号强度。

3. 发明授权

US06963232B2 Compensator for leakage through loop filter capacitors in phase-locked loops 失效
标题翻译：用于通过锁相环路环路滤波电容器进行泄漏的补偿器
公开(公告)号：US06963232B2
公开(公告)日：2005-11-08
申请号：US10638717
申请日：2003-08-11
申请人： Yohan Frans , Nhat M. Nguyen
发明人： Yohan Frans , Nhat M. Nguyen
IPC分类号： H03L7/081 , H03L7/089 , H03L7/093 , H03L7/06
CPC分类号： H03L7/0896 , H03L7/0812 , H03L7/093
摘要： A loop filter of a compensating phase-locked loop contains capacitors formed from transistors with thin gate oxide dielectric layers. Leakage current leaks through the capacitors. To avoid jitter in the output signal of the phase-locked loop that would otherwise be caused by the leakage current, a leakage compensation circuit is provided. The leakage compensation circuit of a first embodiment replicates the leakage current using a replication capacitor and a current mirror. The voltage across the replication capacitor is proportional to the control voltage of a voltage-controlled oscillator of the compensating phase-locked loop. A second embodiment generates the compensation current by controlling the voltage on the gate of a transistor. The gate voltage depends on charge added and subtracted by a charge pump in addition to the charge pumps in the loop filter. A third embodiment applies a leakage compensation circuit to a delay locked loop.
摘要翻译：补偿锁相环的环路滤波器包含由具有薄栅极氧化物介电层的晶体管形成的电容器。泄漏电流通过电容器泄漏。为了避免由漏电流引起的锁相环的输出信号中的抖动，提供了泄漏补偿电路。第一实施例的漏电补偿电路使用复制电容器和电流镜复制泄漏电流。复制电容器两端的电压与补偿锁相环的压控振荡器的控制电压成比例。第二实施例通过控制晶体管的栅极上的电压来产生补偿电流。除了环路滤波器中的电荷泵之外，栅极电压还取决于电荷泵的电荷和扣除电荷。第三实施例将泄漏补偿电路应用于延迟锁定环路。

4. 发明授权

US06879195B2 PLL lock detection circuit using edge detection 有权
标题翻译： PLL锁定检测电路采用边缘检测
公开(公告)号：US06879195B2
公开(公告)日：2005-04-12
申请号：US10622627
申请日：2003-07-17
申请人： Michael Green , Nhat M. Nguyen , Yohan Frans , Dennis Kim , Todd Bystrom
发明人： Michael Green , Nhat M. Nguyen , Yohan Frans , Dennis Kim , Todd Bystrom
IPC分类号： H03D13/00 , H03L7/06
CPC分类号： H03D13/003
摘要： A lock detection circuit operatively associated with a phase-locked loop indicates when a feedback clock signal is locked to a reference clock signal. The lock detection circuit counts the number of rising and falling edges of the feedback clock signal that are detected between rising edges of the reference clock cycle. The lock detection circuit counts the number of consecutive valid cycles of the reference clock signal during which a single rising edge and a single falling edge of the feedback clock signal are detected. Lock detection circuit asserts a lock signal when the number of consecutive valid cycles counted exceeds a predetermined number. Where the lock detection circuit indicates locked signals and then detects a reference clock cycle that is not valid, lock detection circuit continues to indicate lock if the next reference clock cycle is valid relative to a skewed feedback clock signal.
摘要翻译：与锁相环可操作地相关联的锁定检测电路指示何时将反馈时钟信号锁定到参考时钟信号。锁定检测电路对在参考时钟周期的上升沿之间检测到的反馈时钟信号的上升沿和下降沿的数量进行计数。锁定检测电路对在其中检测到反馈时钟信号的单个上升沿和单个下降沿的参考时钟信号的连续有效周期的数量进行计数。当连续的有效周期数超过预定数量时，锁定检测电路断言锁定信号。如果锁定检测电路指示锁定信号，然后检测到无效的参考时钟周期，则如果下一个参考时钟周期相对于偏斜反馈时钟信号有效，锁定检测电路将继续指示锁定。

5. 发明授权

US6014042A Phase detector using switched capacitors 失效
标题翻译：相位检测器采用开关电容器
公开(公告)号：US6014042A
公开(公告)日：2000-01-11
申请号：US25983
申请日：1998-02-19
申请人： Nhat M. Nguyen
发明人： Nhat M. Nguyen
IPC分类号： H03K5/26
CPC分类号： H03K5/26
摘要： A phase detector operating in a low voltage environment and providing a substantially constant integral voltage over variations in temperature, supply voltage and process parameters. The quadrature phase detector includes an equalizer, a switching unit, a sampler and comparator unit and a bias generator. The bias generator includes a switched capacitor structure which produces a bias current which tracks fluctuations in capacitance values due to temperature, supply voltage and process variations. The errors introduced due to fluctuations in bias current and capacitance are thus minimized.
摘要翻译：相位检测器在低电压环境中工作，并且在温度，电源电压和工艺参数的变化上提供基本恒定的积分电压。正交相位检测器包括均衡器，开关单元，采样器和比较器单元以及偏置发生器。偏置发生器包括开关电容器结构，其产生偏移电流，该偏置电流跟踪由于温度，电源电压和工艺变化引起的电容值的波动。由于偏置电流和电容的波动引起的误差因此被最小化。

6. 发明授权

US08279948B2 Interface with variable data rate 有权
标题翻译：具有可变数据速率的接口
公开(公告)号：US08279948B2
公开(公告)日：2012-10-02
申请号：US12518781
申请日：2007-12-10
申请人： Yohan U. Frans , Hae-Chang Lee , Brian S. Leibowitz , Simon Li , Nhat M. Nguyen
发明人： Yohan U. Frans , Hae-Chang Lee , Brian S. Leibowitz , Simon Li , Nhat M. Nguyen
IPC分类号： H04B3/00
CPC分类号： G06F13/4286 , G06F13/385 , G06F13/4068 , H04L1/0002 , H04L1/0015 , H04L1/203 , H04L1/205 , H04L1/243 , H04L5/1446 , H04L25/0262 , H04L25/0292 , Y02D50/10
摘要： A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined errorrate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.
摘要翻译：一种设备包括耦合到节点的发射器，其中节点将耦合到有线链路。发射机具有多种操作模式，包括校准模式，其中根据有线链路以预定的错误率对应的电压余量来确定有线链路上的通信数据速率的范围。通信数据速率的范围包括最大数据速率，其可以是初始数据速率的非整数倍。

7. 发明授权

US06856169B2 Method and apparatus for signal reception using ground termination and/or non-ground termination 有权
标题翻译：使用接地端接和/或非接地端接信号接收的方法和装置
公开(公告)号：US06856169B2
公开(公告)日：2005-02-15
申请号：US10435292
申请日：2003-05-09
申请人： Yohan U. Frans , Nhat M. Nguyen , Yueyong Wang
发明人： Yohan U. Frans , Nhat M. Nguyen , Yueyong Wang
IPC分类号： H03K5/00 , H03K5/003 , H03K5/01 , H03K19/003 , H03K19/0175 , H04L25/02
CPC分类号： H04L25/0292 , H03K5/003 , H04L25/0272
摘要： Receiving units with inputs that may be ground-terminated and with inputs that are selectively ground-terminated or non-ground terminated are enabled with signal level shifting and a termination mode selection input. In a first exemplary implementation, a receiving unit is capable of having ground-terminated inputs. However, common mode voltage of the signal that is input to decoding data recovery circuitry is above ground because the input signal may be level shifted in between the ground-terminated inputs and the decoding data recovery circuitry. In a second exemplary implementation, a mode selection is accomplished by switching a voltage divider into operation and bypassing a level shifter for a non-ground terminated mode. For a ground terminated mode, the voltage divider is switched out of operation and the level shifter is switched into operation for its signal output to be decoded. Pre-amplification may also be employed to improve signal strength.
摘要翻译：具有可能被接地端接的输入和具有选择性地接地或非接地端接的输入的接收单元使能信号电平移位和终端模式选择输入。在第一示例性实施方式中，接收单元能够具有接地端接的输入。然而，输入到解码数据恢复电路的信号的共模电压高于地，因为输入信号可能在接地端接输入和解码数据恢复电路之间的电平移位。在第二示例性实施方案中，通过将分压器切换到操作中并且绕过非接地端接模式的电平移位器来实现模式选择。对于接地端接模式，分压器切换到运行状态，电平转换器切换到其信号输出进行操作，进行解码。也可以使用预扩增来提高信号强度。

8. 发明授权

US06696829B1 Self-resetting phase locked loop 有权
标题翻译：自复位锁相环
公开(公告)号：US06696829B1
公开(公告)日：2004-02-24
申请号：US09993929
申请日：2001-11-16
申请人： Nhat M. Nguyen , Kun-Yung K. Chang
发明人： Nhat M. Nguyen , Kun-Yung K. Chang
IPC分类号： G01R2312
CPC分类号： H03L7/18 , H03K17/22 , H03L7/0802 , H03L7/10
摘要： An integrated circuit device having a self-resetting phase-locked loop (PLL) circuit. The PLL circuit generates an output clock signal having a first frequency in a first operating mode and a second frequency in a second operating mode, the second frequency being determined, at least in part, by a reference clock signal. A control circuit within the integrated circuit resets the PLL circuit by selecting the first operating mode for a predetermined time interval, then selecting the second operating mode.
摘要翻译：一种具有自复位锁相环（PLL）电路的集成电路器件。 PLL电路产生具有第一操作模式的第一频率和第二操作模式的第二频率的输出时钟信号，第二频率至少部分地由参考时钟信号确定。集成电路内的控制电路通过在预定的时间间隔内选择第一操作模式来重置PLL电路，然后选择第二操作模式。

9. 发明授权

US5379457A Low noise active mixer 失效
标题翻译：平衡混频器，具有rf输入晶体管对发射极之间的电感耦合
公开(公告)号：US5379457A
公开(公告)日：1995-01-03
申请号：US83449
申请日：1993-06-28
申请人： Nhat M. Nguyen
发明人： Nhat M. Nguyen
IPC分类号： H03D7/14 , H04B1/28 , G06G7/02
CPC分类号： H03F3/45197 , H03D7/1425 , H03D7/1433 , H03D7/1441 , H03D7/1458 , H03D2200/0019 , H03F2203/45148 , H03F2203/45151 , H03F2203/45458 , H03F2203/45464 , H03F2203/45496
摘要： In a conventional Gilbert-cell active mixer, two local oscillator matched pairs of transistors receive a local oscillator input signal and are coupled to a radio frequency matched pair of transistors which receive a radio frequency input signal. The circuit generates an intermodulated output signal at the collectors of the local oscillator matched pairs. Noise degradation is reduced over the conventional mixer by replacing the standard radio frequency emitter degeneration resistor with a reactive element, thereby reducing thermal noise. Narrow-band input matching is achieved by insertion of a series inductive element and optional parallel capacitive element in line with the radio frequency input. Thermal noise contributed to the circuit is thereby minimized while circuit linearity is preserved in the narrow frequency band of interest.
摘要翻译：在传统的吉尔伯特电池有源混频器中，两个本地振荡器匹配的晶体管对接收本地振荡器输入信号，并且耦合到接收射频输入信号的射频匹配对晶体管对。该电路在本地振荡器匹配对的收集器处产生互调输出信号。通过用无功元件替换标准射频发生器退化电阻器，通过常规混频器降低噪声，从而降低热噪声。窄带输入匹配通过插入串联电感元件和可选的并联电容元件与射频输入一致来实现。由此，在感兴趣的窄频带中保持电路线性度，从而最小化了导致电路的热噪声。

10. 发明申请

US20130148709A1 Interface with Variable Data Rate 有权
公开(公告)号：US20130148709A1
公开(公告)日：2013-06-13
申请号：US13633076
申请日：2012-10-01
申请人： Yohan U. Frans , Hae-Chang Lee , Brian S. Leibowitz , Simon Li , Nhat M. Nguyen
发明人： Yohan U. Frans , Hae-Chang Lee , Brian S. Leibowitz , Simon Li , Nhat M. Nguyen
IPC分类号： H04L25/02
CPC分类号： G06F13/4286 , G06F13/385 , G06F13/4068 , H04L1/0002 , H04L1/0015 , H04L1/203 , H04L1/205 , H04L1/243 , H04L5/1446 , H04L25/0262 , H04L25/0292 , Y02D50/10
摘要： A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.

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