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1. 发明授权

US07413941B2 Method of fabricating sectional field effect devices 有权
标题翻译：制造截面场效应装置的方法
公开(公告)号：US07413941B2
公开(公告)日：2008-08-19
申请号：US11433806
申请日：2006-05-13
申请人： Ying Zhang , Bruce B. Doris , Thomas Safron Kanarsky , Meikei Ieong , Jakub Tadeusz Kedzierski
发明人： Ying Zhang , Bruce B. Doris , Thomas Safron Kanarsky , Meikei Ieong , Jakub Tadeusz Kedzierski
IPC分类号： H01L21/84
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66795
摘要： A field effect device is disclosed which has a body formed of a crystalline semiconductor material and has at least one vertically oriented section and at least one horizontally oriented section. The device is produced in SOI technology by fabricating first a formation of the device in masking insulators, and then transferring this formation through several etching steps into the SOI layer. The segmented field effect device combines FinFET, or fully depleted silicon-on-insulator FETs, type devices with fully depleted planar devices. This combination allows device width control with FinFET type devices. The segmented field effect device gives high current drive for a given layout area. The segmented field effect devices allow for the fabrication of high performance processors.
摘要翻译：公开了一种场效应器件，其具有由晶体半导体材料形成的主体，并具有至少一个垂直取向部分和至少一个水平定向部分。该器件通过在掩模绝缘体中首先制造器件的形成，然后将该形成通过几个蚀刻步骤转移到SOI层中而以SOI技术制造。分段场效应器件结合FinFET或完全耗尽的绝缘体上硅FET，具有完全耗尽的平面器件的类型器件。该组合允许使用FinFET类型器件进行器件宽度控制。分段场效应器件为给定的布局区域提供高电流驱动。分段场效应器件允许制造高性能处理器。

2. 发明授权

US07659153B2 Sectional field effect devices and method of fabrication 有权
标题翻译：截面场效应器件及其制造方法
公开(公告)号：US07659153B2
公开(公告)日：2010-02-09
申请号：US12142849
申请日：2008-06-20
申请人： Ying Zhang , Bruce B. Doris , Thomas Safron Kanarsky , Meikei Ieong , Jakub Tadeusz Kedzierski
发明人： Ying Zhang , Bruce B. Doris , Thomas Safron Kanarsky , Meikei Ieong , Jakub Tadeusz Kedzierski
IPC分类号： H01L21/84
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66795
摘要： A field effect device is disclosed which has a body formed of a crystalline semiconductor material and has at least one vertically oriented section and at least one horizontally oriented section. The device is produced in SOI technology by fabricating first a formation of the device in masking insulators, and then transferring this formation through several etching steps into the SOI layer. The segmented field effect device combines FinFET, or fully depleted silicon-on-insulator FETs, type devices with fully depleted planar devices. This combination allows device width control with FinFET type devices. The segmented field effect device gives high current drive for a given layout area. The segmented field effect devices allow for the fabrication of high performance processors.
摘要翻译：公开了一种场效应器件，其具有由晶体半导体材料形成的主体，并具有至少一个垂直取向部分和至少一个水平定向部分。该器件通过在掩模绝缘体中首先制造器件的形成，然后将该形成通过几个蚀刻步骤转移到SOI层中而以SOI技术制造。分段场效应器件结合FinFET或完全耗尽的绝缘体上硅FET，具有完全耗尽的平面器件的类型器件。该组合允许使用FinFET类型器件进行器件宽度控制。分段场效应器件为给定的布局区域提供高电流驱动。分段场效应器件允许制造高性能处理器。

3. 发明授权

US07388258B2 Sectional field effect devices 有权
标题翻译：截面场效应装置
公开(公告)号：US07388258B2
公开(公告)日：2008-06-17
申请号：US10732322
申请日：2003-12-10
申请人： Ying Zhang , Bruce B. Doris , Thomas Safron Kanarsky , Meikei Ieong , Jakub Tadeusz Kedzierski
发明人： Ying Zhang , Bruce B. Doris , Thomas Safron Kanarsky , Meikei Ieong , Jakub Tadeusz Kedzierski
IPC分类号： H01L29/06
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66795
摘要： A field effect device is disclosed which has a body formed of a crystalline semiconductor material and has at least one vertically oriented section and at least one horizontally oriented section. The device is produced in SOI technology by fabricating first a formation of the device in masking insulators, and then transferring this formation through several etching steps into the SOI layer. The segmented field effect device combines FinFET, or fully depleted silicon-on-insulator FETs, type devices with fully depleted planar devices. This combination allows device width control with FinFET type devices. The segmented field effect device gives high current drive for a given layout area. The segmented field effect devices allow for the fabrication of high performance processors.
摘要翻译：公开了一种场效应器件，其具有由晶体半导体材料形成的主体，并具有至少一个垂直取向部分和至少一个水平定向部分。该器件通过在掩模绝缘体中首先制造器件的形成，然后将该形成通过几个蚀刻步骤转移到SOI层中而以SOI技术制造。分段场效应器件结合FinFET或完全耗尽的绝缘体上硅FET，具有完全耗尽的平面器件的类型器件。该组合允许使用FinFET类型器件进行器件宽度控制。分段场效应器件为给定的布局区域提供高电流驱动。分段场效应器件允许制造高性能处理器。

4. 发明申请

US20080254577A1 Sectional Field Effect Devices and Method of Fabrication 有权
标题翻译：截面场效应器件及其制作方法
公开(公告)号：US20080254577A1
公开(公告)日：2008-10-16
申请号：US12142849
申请日：2008-06-20
申请人： Ying Zhang , Bruce B. Doris , Thomas Safron Kanarsky , Meikei Ieong , Jakub Tadeusz Kedzierski
发明人： Ying Zhang , Bruce B. Doris , Thomas Safron Kanarsky , Meikei Ieong , Jakub Tadeusz Kedzierski
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66795
摘要： A field effect device is disclosed which has a body formed of a crystalline semiconductor material and has at least one vertically oriented section and at least one horizontally oriented section. The device is produced in SOI technology by fabricating first a formation of the device in masking insulators, and then transferring this formation through several etching steps into the SOI layer. The segmented field effect device combines FinFET, or fully depleted silicon-on-insulator FETs, type devices with fully depleted planar devices. This combination allows device width control with FinFET type devices. The segmented field effect device gives high current drive for a given layout area. The segmented field effect devices allow for the fabrication of high performance processors.
摘要翻译：公开了一种场效应器件，其具有由晶体半导体材料形成的主体，并具有至少一个垂直取向部分和至少一个水平定向部分。该器件通过在掩模绝缘体中首先制造器件的形成，然后将该形成通过几个蚀刻步骤转移到SOI层中而以SOI技术制造。分段场效应器件结合FinFET或完全耗尽的绝缘体上硅FET，具有完全耗尽的平面器件的类型器件。该组合允许使用FinFET类型器件进行器件宽度控制。分段场效应器件为给定的布局区域提供高电流驱动。分段场效应器件允许制造高性能处理器。

5. 发明授权

US06914303B2 Ultra thin channel MOSFET 有权
公开(公告)号：US06914303B2
公开(公告)日：2005-07-05
申请号：US10650229
申请日：2003-08-28
申请人： Bruce B. Doris , Thomas S. Kanarsky , Ying Zhang , Huilong Zhu , Meikei Ieong , Omer Dokumaci
发明人： Bruce B. Doris , Thomas S. Kanarsky , Ying Zhang , Huilong Zhu , Meikei Ieong , Omer Dokumaci
IPC分类号： H01L21/336 , H01L21/84 , H01L27/12 , H01L29/786 , H01L27/01
CPC分类号： H01L29/66772 , H01L21/84 , H01L27/1203 , H01L29/6656 , H01L29/78612 , H01L29/78621
摘要： Described is a method for making thin channel silicon-on-insulator structures. The inventive method comprises forming a set of thin spacer abutting a gate region in a first device and a second device region; forming a raised source/drain region on either side of the gate region in the first device region and the second device region, implanting dopants of a first conductivity type into the raised source drain region in the first device region to form a first dopant impurity region, where the second device region is protected by a second device region block mask; implanting dopants of a second conductivity type into the raised source/drain region in the second device region to form a second dopant impurity region, where the first device region is protected by a first device region block mask; and activating the first dopant impurity region and the second dopant impurity region to provide a thin channel MOSFET.

6. 发明授权

US07211490B2 Ultra thin channel MOSFET 失效
标题翻译：超薄通道MOSFET
公开(公告)号：US07211490B2
公开(公告)日：2007-05-01
申请号：US11083743
申请日：2005-03-18
申请人： Bruce B. Doris , Thomas S. Kanarsky , Ying Zhang , Huilong Zhu , Meikei Ieong , Omer Dokumaci
发明人： Bruce B. Doris , Thomas S. Kanarsky , Ying Zhang , Huilong Zhu , Meikei Ieong , Omer Dokumaci
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/66772 , H01L21/84 , H01L27/1203 , H01L29/6656 , H01L29/78612 , H01L29/78621
摘要： Described is a method for making thin channel silicon-on-insulator structures. The inventive method comprises forming a set of thin spacer abutting a gate region in a first device and a second device region; forming a raised source/drain region on either side of the gate region in the first device region and the second device region, implanting dopants of a first conductivity type into the raised source drain region in the first device region to form a first dopant impurity region, where the second device region is protected by a second device region block mask; implanting dopants of a second conductivity type into the raised source/drain region in the second device region to form a second dopant impurity region, where the first device region is protected by a first device region block mask; and activating the first dopant impurity region and the second dopant impurity region to provide a thin channel MOSFET.
摘要翻译：描述了制造薄沟道硅绝缘体上结构的方法。本发明的方法包括在第一装置和第二装置区域中形成邻接栅极区的一组薄间隔件; 在第一器件区域和第二器件区域中的栅极区域的任一侧上形成凸起的源极/漏极区域，将第一导电类型的掺杂剂注入到第一器件区域中的凸起的源极漏极区域中以形成第一掺杂剂杂质区域，其中所述第二设备区域被第二设备区域块掩码保护; 将第二导电类型的掺杂剂注入所述第二器件区域中的所述升高的源极/漏极区域中以形成第二掺杂剂杂质区域，其中所述第一器件区域被第一器件区域阻挡掩模保护; 以及激活第一掺杂杂质区和第二掺杂杂质区，以提供薄沟道MOSFET。

7. 发明授权

US07713807B2 High-performance CMOS SOI devices on hybrid crystal-oriented substrates 失效
标题翻译：高性能CMOS SOI器件在混合晶体取向衬底上
公开(公告)号：US07713807B2
公开(公告)日：2010-05-11
申请号：US11958877
申请日：2007-12-18
申请人： Bruce B. Doris , Kathryn W. Guarini , Meikei Ieong , Shreesh Narasimha , Kern Rim , Jeffrey W. Sleight , Min Yang
发明人： Bruce B. Doris , Kathryn W. Guarini , Meikei Ieong , Shreesh Narasimha , Kern Rim , Jeffrey W. Sleight , Min Yang
IPC分类号： H01L21/8238
CPC分类号： H01L21/76275 , H01L21/823807 , H01L21/84
摘要： An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is provided. The method of forming the integrated structure includes providing a bonded substrate including at least a first semiconductor layer of a first crystallographic orientation and a second semiconductor layer of a second different crystallographic orientation. A portion of the bonded substrate is protected to define a first device area, while another portion of the bonded substrate is unprotected. The unprotected portion of the bonded substrate is then etched to expose a surface of the second semiconductor layer and a semiconductor material is regrown on the exposed surface. Following planarization, a first semiconductor device is formed in the first device region and a second semiconductor device is formed on the regrown material.
摘要翻译：提供包含至少一个器件的集成半导体结构，所述器件形成在对于该器件最佳的第一晶体表面上，而另一器件形成在对于另一器件最佳的第二不同晶体表面上。形成集成结构的方法包括提供包括至少第一晶体取向的第一半导体层和第二不同晶体取向的第二半导体层的键合衬底。键合衬底的一部分被保护以限定第一器件区域，而键合衬底的另一部分是未受保护的。然后蚀刻键合衬底的未保护部分以暴露第二半导体层的表面，并将半导体材料重新生长在暴露表面上。在平坦化之后，在第一器件区域中形成第一半导体器件，并且在再生长材料上形成第二半导体器件。

8. 发明授权

US07605447B2 Highly manufacturable SRAM cells in substrates with hybrid crystal orientation 有权
标题翻译：具有混合晶体取向的基板中的高度可制造的SRAM单元
公开(公告)号：US07605447B2
公开(公告)日：2009-10-20
申请号：US11162780
申请日：2005-09-22
申请人： Bruce B. Doris , Gregory Costrini , Oleg Gluschenkov , Meikei Ieong , Nakgeuon Seong
发明人： Bruce B. Doris , Gregory Costrini , Oleg Gluschenkov , Meikei Ieong , Nakgeuon Seong
IPC分类号： H01L29/06 , H01L29/04 , H01L27/11
CPC分类号： H01L27/1104 , H01L27/11 , Y10S257/903 , Y10S438/973
摘要： The present invention relates to a semiconductor device structure that includes at least one SRAM cell formed in a substrate. Such SRAM cell comprises two pull-up transistors, two pull-down transistors, and two pass-gate transistors. The pull-down transistors and the pass-gate transistors are substantially similar in channel widths and have substantially similar source-drain doping concentrations, while the SRAM cell has a beta ratio of at least 1.5. The substrate preferably comprises a hybrid substrate with at two isolated sets of regions, while carrier mobility in these two sets of regions differentiates by a factor of at least about 1.5. More preferably, the pull-down transistors of the SRAM cell are formed in one set of regions, and the pass-gate transistors are formed in the other set of regions, so that current flow in the pull-down transistors is larger than that in the pass-gate transistors.
摘要翻译：本发明涉及一种半导体器件结构，其包括在衬底中形成的至少一个SRAM单元。这样的SRAM单元包括两个上拉晶体管，两个下拉晶体管和两个通过栅极晶体管。下拉晶体管和栅极晶体管在沟道宽度上基本相似，并且具有基本相似的源极 - 漏极掺杂浓度，而SRAM单元的β比率至少为1.5。衬底优选地包括具有两个分离的区域集合的混合衬底，而这两组区域中的载流子迁移率以至少约1.5的因子差分。更优选地，SRAM单元的下拉晶体管形成在一组区域中，并且栅极晶体管形成在另一组区域中，使得下拉晶体管中的电流大于传输栅晶体管。

9. 发明授权

US07494861B2 Method for metal gated ultra short MOSFET devices 失效
标题翻译：金属门极超短MOSFET器件的方法
公开(公告)号：US07494861B2
公开(公告)日：2009-02-24
申请号：US12013704
申请日：2008-01-14
申请人： Jack Oon Chu , Bruce B. Doris , Meikei Ieong , Jing Wang
发明人： Jack Oon Chu , Bruce B. Doris , Meikei Ieong , Jing Wang
IPC分类号： H01L21/8238
CPC分类号： H01L29/7838 , H01L21/28017 , H01L29/105
摘要： MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body layer is doped with impurities of opposite type than the ground plane. The gate has a metal with a mid-gap workfunction directly contacting a gate insulator layer. The gate is patterned to a length of less than about 40 nm, and possibly less than 20 nm. The source and the drain of the MOSFET are doped with the same type of dopant as the body layer. In CMOS embodiments of the invention the metal in the gate of the NMOS and the PMOS devices may be the same metal.
摘要翻译：适用于栅极长度小于约40nm的MOSFET器件及其制造方法。 MOSFET器件包括由单晶Si基材料形成的接地平面。 Si基体层外延地设置在接地平面上。体层掺杂了与地平面相反的杂质。栅极具有中间功能函数的金属，其直接接触栅极绝缘体层。栅极被图案化成小于约40nm，并且可能小于20nm的长度。 MOSFET的源极和漏极掺杂有与体层相同类型的掺杂剂。在本发明的CMOS实施例中，NMOS和PMOS器件的栅极中的金属可以是相同的金属。

10. 发明申请

US20080246090A1 SELF-ALIGNED PLANAR DOUBLE-GATE TRANSISTOR STRUCTURE 有权
标题翻译：自对准平面双栅晶体管结构
公开(公告)号：US20080246090A1
公开(公告)日：2008-10-09
申请号：US12119765
申请日：2008-05-13
申请人： Omer H. Dokumaci , Bruce B. Doris , Kathryn W. Guarini , Suryanarayan G. Hegde , MeiKei Ieong , Erin Catherine Jones
发明人： Omer H. Dokumaci , Bruce B. Doris , Kathryn W. Guarini , Suryanarayan G. Hegde , MeiKei Ieong , Erin Catherine Jones
IPC分类号： H01L27/12
CPC分类号： H01L29/78648 , H01L21/0338 , H01L21/2007 , H01L21/26506 , H01L21/26586 , H01L29/42384
摘要： A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer; a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.
摘要翻译：提供了具有横向排列的前（上）和后门的双栅极晶体管。双栅晶体管包括在器件层下面的背栅热氧化层; 位于背栅极氧化物层下面的背栅电极; 位于器件层上方的前门热氧化物; 前栅极热氧化物上方的前栅极电极层，并与背栅电极垂直对准; 以及设置在背栅极热氧化物层上方的与第一栅极对称的晶体管体。背栅电极具有形成在晶体管本体下方和在背栅电极的中心部分的任一侧上的氧化物层，从而将后栅极与前栅极自对准。晶体管还包括在所述晶体管体的相对侧上的源极和漏极。

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