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1. 发明授权

US07605447B2 Highly manufacturable SRAM cells in substrates with hybrid crystal orientation 有权
标题翻译：具有混合晶体取向的基板中的高度可制造的SRAM单元
公开(公告)号：US07605447B2
公开(公告)日：2009-10-20
申请号：US11162780
申请日：2005-09-22
申请人： Bruce B. Doris , Gregory Costrini , Oleg Gluschenkov , Meikei Ieong , Nakgeuon Seong
发明人： Bruce B. Doris , Gregory Costrini , Oleg Gluschenkov , Meikei Ieong , Nakgeuon Seong
IPC分类号： H01L29/06 , H01L29/04 , H01L27/11
CPC分类号： H01L27/1104 , H01L27/11 , Y10S257/903 , Y10S438/973
摘要： The present invention relates to a semiconductor device structure that includes at least one SRAM cell formed in a substrate. Such SRAM cell comprises two pull-up transistors, two pull-down transistors, and two pass-gate transistors. The pull-down transistors and the pass-gate transistors are substantially similar in channel widths and have substantially similar source-drain doping concentrations, while the SRAM cell has a beta ratio of at least 1.5. The substrate preferably comprises a hybrid substrate with at two isolated sets of regions, while carrier mobility in these two sets of regions differentiates by a factor of at least about 1.5. More preferably, the pull-down transistors of the SRAM cell are formed in one set of regions, and the pass-gate transistors are formed in the other set of regions, so that current flow in the pull-down transistors is larger than that in the pass-gate transistors.
摘要翻译：本发明涉及一种半导体器件结构，其包括在衬底中形成的至少一个SRAM单元。这样的SRAM单元包括两个上拉晶体管，两个下拉晶体管和两个通过栅极晶体管。下拉晶体管和栅极晶体管在沟道宽度上基本相似，并且具有基本相似的源极 - 漏极掺杂浓度，而SRAM单元的β比率至少为1.5。衬底优选地包括具有两个分离的区域集合的混合衬底，而这两组区域中的载流子迁移率以至少约1.5的因子差分。更优选地，SRAM单元的下拉晶体管形成在一组区域中，并且栅极晶体管形成在另一组区域中，使得下拉晶体管中的电流大于传输栅晶体管。

2. 发明申请

US20070063278A1 HIGHLY MANUFACTURABLE SRAM CELLS IN SUBSTRATES WITH HYBRID CRYSTAL ORIENTATION 有权
标题翻译：具有混合晶体取向的衬底中的高度可制造的SRAM电池
公开(公告)号：US20070063278A1
公开(公告)日：2007-03-22
申请号：US11162780
申请日：2005-09-22
申请人： Bruce Doris , Gregory Costrini , Oleg Gluschenkov , Meikei Ieong , Nakgeuon Seong
发明人： Bruce Doris , Gregory Costrini , Oleg Gluschenkov , Meikei Ieong , Nakgeuon Seong
IPC分类号： H01L27/12
CPC分类号： H01L27/1104 , H01L27/11 , Y10S257/903 , Y10S438/973
摘要： The present invention relates to a semiconductor device structure that includes at least one SRAM cell formed in a substrate. Such SRAM cell comprises two pull-up transistors, two pull-down transistors, and two pass-gate transistors. The pull-down transistors and the pass-gate transistors are substantially similar in channel widths and have substantially similar source-drain doping concentrations, while the SRAM cell has a beta ratio of at least 1.5. The substrate preferably comprises a hybrid substrate with at two isolated sets of regions, while carrier mobility in these two sets of regions differentiates by a factor of at least about 1.5. More preferably, the pull-down transistors of the SRAM cell are formed in one set of regions, and the pass-gate transistors are formed in the other set of regions, so that current flow in the pull-down transistors is larger than that in the pass-gate transistors.
摘要翻译：本发明涉及一种半导体器件结构，其包括在衬底中形成的至少一个SRAM单元。这样的SRAM单元包括两个上拉晶体管，两个下拉晶体管和两个通过栅极晶体管。下拉晶体管和栅极晶体管在沟道宽度上基本相似，并且具有基本相似的源极 - 漏极掺杂浓度，而SRAM单元的β比率至少为1.5。衬底优选地包括具有两个分离的区域集合的混合衬底，而这两组区域中的载流子迁移率以至少约1.5的因子差分。更优选地，SRAM单元的下拉晶体管形成在一组区域中，并且栅极晶体管形成在另一组区域中，使得下拉晶体管中的电流大于传输栅晶体管。

3. 发明申请

US20090189242A1 METHOD FOR NON-SELECTIVE SHALLOW TRENCH ISOLATION REACTIVE ION ETCH FOR PATTERNING HYBRID-ORIENTED DEVICES COMPATIBLE WITH HIGH-PERFORMANCE HIGHLY-INTEGRATED LOGIC DEVICES 失效
标题翻译：用于非选择性低温分离隔离反应离子蚀刻的方法，适用于兼容高性能高度集成逻辑器件的混合器件
公开(公告)号：US20090189242A1
公开(公告)日：2009-07-30
申请号：US12020887
申请日：2008-01-28
申请人： Gregory Costrini , David M. Dobuzinsky , Thomas S. Kanarsky , Munir D. Naeem , Christopher D. Sheraw , Richard Wise
发明人： Gregory Costrini , David M. Dobuzinsky , Thomas S. Kanarsky , Munir D. Naeem , Christopher D. Sheraw , Richard Wise
IPC分类号： H01L29/00 , H01L21/762
CPC分类号： H01L29/045 , H01L21/76224
摘要： Disclosed are embodiments of a hybrid-orientation technology (HOT) wafer and a method of forming the HOT wafer with improved shallow trench isolation (STI) structures for patterning devices in both silicon-on-insulator (SOI) regions, having a first crystallographic orientation, and bulk regions, having a second crystallographic orientation. The improved STI structures are formed using a non-selective etch process to ensure that all of the STI structures and, particularly, the STI structures at the SOI-bulk interfaces, each extend to the semiconductor substrate and have an essentially homogeneous (i.e., single material) and planar (i.e., divot-free) bottom surface that is approximately parallel to the top surface of the substrate. Optionally, an additional selective etch process can be used to extend the STI structures a predetermined depth into the substrate.
摘要翻译：公开了混合取向技术（HOT）晶片的实施例以及形成具有改进的浅沟槽隔离（STI）结构的HOT晶片的方法，用于在绝缘体上硅（SOI）区域中图案化器件，具有第一晶体取向和具有第二结晶取向的体区。使用非选择性蚀刻工艺形成改进的STI结构，以确保所有STI结构，特别是SOI-体界面处的STI结构各自延伸到半导体衬底并且具有基本均匀的（即，单个材料）和大致平行于衬底的顶表面的平面（即，无自由）底表面。可选地，可以使用附加的选择性蚀刻工艺来将STI结构延伸到衬底中的预定深度。

4. 发明申请

US20050277207A1 MASK SCHEMES FOR PATTERNING MAGNETIC TUNNEL JUNCTIONS 失效
标题翻译：用于绘制磁性隧道结的掩蔽方案
公开(公告)号：US20050277207A1
公开(公告)日：2005-12-15
申请号：US10868328
申请日：2004-06-15
申请人： Gregory Costrini , Frank Findeis , Gill Lee , Chanro Park
发明人： Gregory Costrini , Frank Findeis , Gill Lee , Chanro Park
IPC分类号： G11C11/15 , H01L21/8246 , H01L27/22 , H01L43/12
CPC分类号： H01L43/12 , B82Y10/00 , H01L27/228
摘要： Methods of patterning magnetic tunnel junctions (MTJ's) of magnetic memory devices that avoid shorting magnetic memory cells to upper levels of conductive lines during etching processes. One method involves using a hard mask having two material layers to pattern the lower magnetic material layers of an MTJ. The first material of the hard mask is thin and comprises an etch-resistant material. The second material of the hard mask deposited over the first material is thicker and is less etch-resistant than the first material. At least a portion of the second material is sacrificially removed during the etch process of the lower magnetic material layers. A conformal or non-conformal material may be used as the second material of the hard mask. The hard mask used to pattern lower magnetic materials of an MTJ may comprise a single layer of non-conformal material.
摘要翻译：磁记录装置的磁隧道结（MTJ）的图案化方法，可避免在刻蚀过程中将磁存储单元短路到上层的导线。一种方法包括使用具有两个材料层的硬掩模来图案化MTJ的下部磁性材料层。硬掩模的第一种材料是薄的并且包括耐蚀刻材料。沉积在第一材料上的硬掩模的第二材料比第一材料更厚并且耐蚀刻性更差。在下磁性材料层的蚀刻过程期间，至少部分第二材料被牺牲地去除。可以使用保形或非保形材料作为硬掩模的第二材料。用于图形MTJ的较低磁性材料的硬掩模可以包括单层非保形材料。

5. 发明申请

US20110092056A1 ELECTRICALLY CONDUCTIVE PATH FORMING BELOW BARRIER OXIDE LAYER AND INTEGRATED CIRCUIT 有权
标题翻译：氧化铝层和集成电路下面形成的导电路径
公开(公告)号：US20110092056A1
公开(公告)日：2011-04-21
申请号：US12977134
申请日：2010-12-23
申请人： Gregory Costrini , Ramachandra Divakaruni , Jeffrey P. Gambino , Randy W. Mann
发明人： Gregory Costrini , Ramachandra Divakaruni , Jeffrey P. Gambino , Randy W. Mann
IPC分类号： H01L21/762 , H01L21/3205
CPC分类号： H01L21/28518 , H01L21/743 , H01L27/105 , H01L27/11 , H01L27/1203
摘要： Methods of forming an electrically conductive path under a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate and an integrated circuit including the path are disclosed. In one embodiment, the method includes forming an electrically conductive path below a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate, the method comprising: forming a first barrier oxide layer on a semiconductor substrate; forming the electrically conductive path within the first barrier oxide layer; and forming a second barrier oxide layer on the first barrier oxide layer. The electrically conductive path allows reduction of SRAM area by forming a wiring path underneath the barrier oxide layer on the SOI substrate.
摘要翻译：公开了在绝缘体上半导体（SOI）基板的阻挡氧化物层和包括该路径的集成电路之下形成导电路径的方法。在一个实施例中，该方法包括在绝缘体上半导体（SOI）衬底的阻挡氧化物层下方形成导电路径，该方法包括：在半导体衬底上形成第一阻挡氧化物层; 在所述第一阻挡氧化物层内形成所述导电路径; 以及在所述第一阻挡氧化物层上形成第二阻挡氧化物层。导电路径允许通过在SOI衬底上的阻挡氧化物层下形成布线路径来减小SRAM面积。

6. 发明申请

US20070249133A1 CONDUCTIVE SPACERS FOR SEMICONDUCTOR DEVICES AND METHODS OF FORMING 审中-公开
标题翻译：用于半导体器件的导电间隔物
公开(公告)号：US20070249133A1
公开(公告)日：2007-10-25
申请号：US11308604
申请日：2006-04-11
申请人： Gary Bronner , David Fried , Jeffrey Gambino , Leland Chang , Ramachandra Divakaruni , Haizhou Yin , Gregory Costrini , Viraj Sardesai
发明人： Gary Bronner , David Fried , Jeffrey Gambino , Leland Chang , Ramachandra Divakaruni , Haizhou Yin , Gregory Costrini , Viraj Sardesai
IPC分类号： H01L21/336
CPC分类号： H01L21/26586 , H01L21/28518 , H01L21/76895 , H01L21/823468 , H01L21/84 , H01L27/11 , H01L27/1108 , H01L27/1203
摘要： A method of forming a conductive spacer on a semiconductor device. The method includes depositing a polysilicon layer on the semiconductor device, selectively implanting dopant ions in the polysilicon layer on a first side of a transistor region of the semiconductor device to define a conductive spacer area, and removing the polysilicon layer except for the conductive spacer area. Optionally, a silicidation process can be performed on the conductive spacer area so that the conductive spacer is made up of metal silicide.
摘要翻译：一种在半导体器件上形成导电间隔物的方法。该方法包括在半导体器件上沉积多晶硅层，在半导体器件的晶体管区域的第一侧上选择性地将多晶硅层中的掺杂剂离子注入以限定导电间隔区，以及除去导电间隔区之外的多晶硅层。任选地，可以在导电间隔物区域上进行硅化处理，使得导电间隔物由金属硅化物构成。

7. 发明申请

US20050280040A1 Methods of patterning a magnetic stack of a magnetic memory cell and structures thereof 有权
标题翻译：图案化磁性存储单元的磁性堆叠的方法及其结构
公开(公告)号：US20050280040A1
公开(公告)日：2005-12-22
申请号：US10870756
申请日：2004-06-17
申请人： Ihar Kasko , Sivanandha Kanakasabapathy , Gregory Costrini
发明人： Ihar Kasko , Sivanandha Kanakasabapathy , Gregory Costrini
IPC分类号： H01L21/335 , H01L27/22 , H01L29/76 , H01L43/12
CPC分类号： H01L43/12 , H01L27/228
摘要： Methods of patterning a magnetic stack of a magnetic memory cell and structures thereof. At least the top magnetic material layer of a magnetic stack is patterned using a hard mask, and a conformal insulating material is deposited over the patterned top magnetic material layer and hard mask. The conformal insulating material is anisotropically etched to remove the conformal insulating material from horizontal surfaces of the device, leaving portions of the conformal insulating material over vertical sidewalls of at least the patterned top magnetic material layer and the hard mask. The remaining conformal insulating material comprises a sidewall spacer hard mask that is used as a mask to pattern the remaining material layers of the magnetic stack. The sidewall spacer hard mask may be left remaining in the magnetic memory cell structure.
摘要翻译：图案化磁性存储单元的磁性堆叠的方法及其结构。至少使用硬掩模对磁性堆叠的顶部磁性材料层进行构图，并且在图案化的顶部磁性材料层和硬掩模上沉积保形绝缘材料。共形绝缘材料被各向异性地蚀刻以从装置的水平表面去除保形绝缘材料，从而将保形绝缘材料的一部分留在至少图案化的顶部磁性材料层和硬掩模的垂直侧壁上。剩余的共形绝缘材料包括侧壁间隔物硬掩模，其用作掩模以对磁性堆叠的剩余材料层进行图案化。侧壁间隔物硬掩模可以留在磁存储单元结构中。

8. 发明申请

US20050146927A1 Spacer integration scheme in MRAM technology 审中-公开
标题翻译： MRAM技术中的间隔整合方案
公开(公告)号：US20050146927A1
公开(公告)日：2005-07-07
申请号：US11055903
申请日：2005-02-11
申请人： Gregory Costrini
发明人： Gregory Costrini
IPC分类号： G11B5/127 , G11B5/33 , G11C11/00 , G11C11/15 , G11C11/34 , H01L21/00 , H01L21/331 , H01L21/335 , H01L21/8232 , H01L21/8246 , H01L27/105 , H01L27/146 , H01L27/22 , H01L31/0352 , H01L43/12
CPC分类号： H01L43/12
摘要： A magneto resistive memory device is fabricated by etching a blanket metal stack comprised of a buffer layer, pinned magnetic layer, a tunnel barrier layer and a free magnetic layer. The problem of junction shorting from resputtered metal during the etching process is eliminated by formation of a protective spacer covering the side of the freelayer and tunnel barrier interface. The spacer is formed following the first etch through the free layer which stops on the barrier layer. After spacer formation a second etch is made to isolate the device. The patterning of the device tunnel junction is made using a disposable mandrel method that enables a self-aligned contact to be made following the completion of the device patterning process.
摘要翻译：通过蚀刻由缓冲层，钉扎磁性层，隧道势垒层和自由磁性层组成的覆盖金属堆叠来制造磁阻存储器件。通过形成覆盖自由层和隧道屏障界面侧面的保护性间隔物，消除了在蚀刻过程期间与溅射金属接合短路的问题。在通过在阻挡层上停止的自由层的第一次蚀刻之后形成间隔物。在间隔物形成之后，进行第二次蚀刻以隔离该装置。器件隧道结的图案化使用一次性心轴方法制造，其能够在器件图案化工艺完成之后进行自对准接触。

9. 发明授权

US06686296B1 Nitrogen-based highly polymerizing plasma process for etching of organic materials in semiconductor manufacturing 失效
标题翻译：用于半导体制造中有机材料蚀刻的氮基高聚合等离子体工艺
公开(公告)号：US06686296B1
公开(公告)日：2004-02-03
申请号：US09723529
申请日：2000-11-28
申请人： Gregory Costrini , Peter D. Hoh , Richard S. Wise , Wendy Yan
发明人： Gregory Costrini , Peter D. Hoh , Richard S. Wise , Wendy Yan
IPC分类号： H01L213065
CPC分类号： H01L21/31138 , H01L21/0276
摘要： A method of etching an organic antireflective film layer underlying a patterned resist layer on a semiconductor substrate by contacting the exposed organic film with a fluorocarbon and nitrogen etchant in the presence of a plasma-generated energy and removing exposed areas of the organic film with the etchant. An oxide layer underlying the organic film layer is substantially undamaged after contact with the etchant. The plasma is a high density plasma and preferably contains argon, C4F8, and nitrogen.
摘要翻译：一种通过在等离子体产生的能量存在下使暴露的有机膜与碳氟化合物和氮气蚀刻剂接触来蚀刻半导体衬底下的图案化抗蚀剂层下面的有机抗反射膜层的方法，并用蚀刻剂去除有机膜的暴露区域。在与蚀刻剂接触之后，有机薄膜层下面的氧化物层基本上没有损坏。等离子体是高密度等离子体，优选含有氩，C 4 F 8和氮。

10. 发明授权

US06333559B1 Method/structure for creating aluminum wirebound pad on copper BEOL 有权
公开(公告)号：US06333559B1
公开(公告)日：2001-12-25
申请号：US09487013
申请日：2000-01-19
申请人： Gregory Costrini , Ronald Dean Goldblatt , John Edward Heidenreich, III , Thomas Leddy McDevitt
发明人： Gregory Costrini , Ronald Dean Goldblatt , John Edward Heidenreich, III , Thomas Leddy McDevitt
IPC分类号： H01L214763
CPC分类号： H01L24/05 , H01L23/3192 , H01L24/03 , H01L24/11 , H01L24/13 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/0231 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05567 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/1191 , H01L2224/13007 , H01L2224/13022 , H01L2224/13099 , H01L2224/131 , H01L2224/45144 , H01L2224/45147 , H01L2224/48463 , H01L2224/48624 , H01L2224/48647 , H01L2224/48799 , H01L2224/48824 , H01L2224/48847 , H01L2924/0001 , H01L2924/00013 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01031 , H01L2924/01032 , H01L2924/01043 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/10329 , H01L2924/14 , H01L2924/00014 , H01L2924/00 , H01L2224/29099 , H01L2224/05552 , H01L2924/00015
摘要： The present invention provides a method for fabricating an integrated circuit (IC) structure having an Al contact in electrical communication with Cu wiring embedded in the initial semiconductor wafer. In accordance with the method of the present invention, the Al contact is formed in areas of the IC structure which contain or do not contain an underlying region of Cu wiring. The present invention also provides a method of interconnecting the fabricated structure to a semiconducting packaging material through the use of a wirebond or Controlled Collapse Chip Connection (C4) solder.

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