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1. 发明授权

US06767791B1 Structure and method for suppressing oxide encroachment in a floating gate memory cell 有权
标题翻译：用于抑制浮动栅极存储单元中的氧化物侵蚀的结构和方法
公开(公告)号：US06767791B1
公开(公告)日：2004-07-27
申请号：US10364569
申请日：2003-02-10
申请人： Yider Wu , Harpreet K. Sachar , Jean Yee-Mei Yang
发明人： Yider Wu , Harpreet K. Sachar , Jean Yee-Mei Yang
IPC分类号： H01L21336
CPC分类号： H01L29/511 , H01L21/28273 , H01L29/42324
摘要： According to one exemplary embodiment, a structure comprises a substrate. The structure further comprises a tunnel oxide layer, where the tunnel oxide layer is situated on the substrate. The structure further comprises a floating gate situated on the tunnel oxide layer, where the floating gate comprises nitrogen. The floating gate may further comprise polysilicon and may be situated in a floating gate flash memory cell, for example. The nitrogen may suppress oxide growth at first and second end regions of the tunnel oxide layer, for example. The nitrogen may be implanted in the floating gate, for example, at a concentration of between approximately 1013 atoms per cm2 and approximately 1015 atoms per cm2. According to this exemplary embodiment, the structure further comprises an ONO stack situated over the floating gate. The structure may further comprise a control gate situated over the ONO stack.
摘要翻译：根据一个示例性实施例，一种结构包括基底。该结构还包括隧道氧化物层，其中隧道氧化物层位于衬底上。该结构还包括位于隧道氧化物层上的浮置栅极，其中浮栅包括氮。浮栅可以进一步包括多晶硅，并且例如可以位于浮动栅闪存单元中。例如，氮可以抑制隧道氧化物层的第一和第二端区域的氧化物生长。可以将氮气注入浮栅中，例如以约10 13个原子/ cm 2和约10 15个原子/ cm 2的浓度注入。根据该示例性实施例，该结构还包括位于浮动栅极上方的ONO堆叠。该结构还可以包括位于ONO堆叠上的控制门。

2. 发明授权

US06737701B1 Structure and method for reducing charge loss in a memory cell 有权
标题翻译：用于减少存储器单元中的电荷损失的结构和方法
公开(公告)号：US06737701B1
公开(公告)日：2004-05-18
申请号：US10313454
申请日：2002-12-05
申请人： Amy C. Tu , Jean Yee-Mei Yang , Yider Wu
发明人： Amy C. Tu , Jean Yee-Mei Yang , Yider Wu
IPC分类号： H01L31119
CPC分类号： H01L27/11568 , H01L27/115
摘要： According to one exemplary embodiment, a structure comprises a first bit line and a second bit line. The structure further comprises a first memory cell situated over the first bit line, where the first memory cell comprises a first ONO stack segment, and where the first ONO stack segment is situated between the first bit line and a word line. The structure further comprises a second memory cell situated over the second bit line, where the second memory cell comprises a second ONO stack segment, where the second ONO stack segment is situated between the second bit line and the word line, and where the first ONO stack segment is separated from the second ONO stack segment by a gap. The first memory cell and the second memory cell may each be capable, for example, of storing two independent data bits.
摘要翻译：根据一个示例性实施例，一种结构包括第一位线和第二位线。该结构还包括位于第一位线之上的第一存储器单元，其中第一存储器单元包括第一ONO堆栈段，并且其中第一ONO堆栈段位于第一位线和字线之间。该结构还包括位于第二位线之上的第二存储器单元，其中第二存储器单元包括第二ONO堆栈段，其中第二ONO堆栈段位于第二位线和字线之间，并且其中第一ONO 堆叠段与第二ONO堆栈段间隔开。第一存储器单元和第二存储单元可以各自能够例如存储两个独立的数据位。

3. 发明授权

US06707078B1 Dummy wordline for erase and bitline leakage 有权
标题翻译：用于擦除和位线泄漏的虚拟字线
公开(公告)号：US06707078B1
公开(公告)日：2004-03-16
申请号：US10230729
申请日：2002-08-29
申请人： Hidehiko Shiraiwa , Yider Wu , Jean Yee-Mei Yang , Mark T. Ramsbey , Darlene G. Hamilton
发明人： Hidehiko Shiraiwa , Yider Wu , Jean Yee-Mei Yang , Mark T. Ramsbey , Darlene G. Hamilton
IPC分类号： H01L2968
CPC分类号： H01L27/11568 , G11C16/0466 , H01L27/115
摘要： One aspect of the present invention relates to a SONOS type non-volatile semiconductor memory device having improved erase speed, the device containing bitlines extending in a first direction; wordlines extending in a second direction, the wordlines comprising functioning wordlines and at least one dummy wordline, wherein the dummy wordline is positioned near at least one of a bitline contact and an edge of the core region, and the dummy wordline is treated so as not to cycle between on and off states. Another aspect of the present invention relates to a method of making a SONOS type non-volatile semiconductor memory device having improved erase speed, involving forming a plurality of bitlines extending in a first direction in the core region; forming a plurality of functioning wordlines extending in a second direction in the core region; forming at least one dummy wordline between the functioning wordlines and the periphery region or between the functioning wordlines and a bitline contact and treating the device so that the dummy wordline does not cycle between on and off states.
摘要翻译：本发明的一个方面涉及一种具有改进的擦除速度的SONOS型非易失性半导体存储器件，该器件含有沿第一方向延伸的位线; 所述字线在第二方向上延伸，所述字线包括功能字线和至少一个伪字线，其中所述伪字线位于所述芯区域的位线接触和边缘中的至少一个附近，并且所述伪字线被处理为不在开关状态之间循环。本发明的另一方面涉及一种制造具有改进的擦除速度的SONOS型非易失性半导体存储器件的方法，包括形成在芯区域中沿第一方向延伸的多个位线; 形成在所述芯区域中沿第二方向延伸的多个功能字线; 在功能字线和外围区域之间或在功能字线和位线接触之间形成至少一个伪字线，并对器件进行处理，使得伪字线不会在导通和关断状态之间循环。

4. 发明授权

US06680509B1 Nitride barrier layer for protection of ONO structure from top oxide loss in fabrication of SONOS flash memory 有权
标题翻译：用于保护ONO结构的氮化物阻挡层免受SONOS闪存的制造中的顶部氧化物损失
公开(公告)号：US06680509B1
公开(公告)日：2004-01-20
申请号：US10158044
申请日：2002-05-30
申请人： Yider Wu , Jean Yee-Mei Yang , Mark Ramsbey , Emmanuel H. Lingunis , Yu Sun
发明人： Yider Wu , Jean Yee-Mei Yang , Mark Ramsbey , Emmanuel H. Lingunis , Yu Sun
IPC分类号： H01L29792
CPC分类号： H01L27/11568 , H01L27/115 , Y10S438/954
摘要： A method for fabricating a SONOS device having a buried bit-line including the steps of: providing a semiconductor substrate having an ONO structure overlying the semiconductor substrate; forming a nitride barrier layer on the ONO structure to form, a four-layer stack; forming a patterned photoresist layer on the nitride barrier layer; implanting As or P ions through the four-layer stack to form a bit-line buried under the ONO structure; stripping the photoresist layer and cleaning an upper surface of the four-layer stack; and consolidating the four-layer stack by applying an oxidation cycle. The invention further relates to a SONOS-type device including the nitride barrier layer.
摘要翻译：一种用于制造具有掩埋位线的SONOS器件的方法，包括以下步骤：提供具有覆盖在半导体衬底上的ONO结构的半导体衬底; 在ONO结构上形成氮化物阻挡层以形成四层堆叠; 在氮化物阻挡层上形成图案化的光致抗蚀剂层; 将As或P离子注入四层堆叠中以形成埋在ONO结构下的位线; 剥离光致抗蚀剂层并清洁四层堆叠的上表面; 并通过施加氧化循环来合并四层堆叠。本发明还涉及包括氮化物阻挡层的SONOS型器件。

5. 发明授权

US06869844B1 Method and structure for protecting NROM devices from induced charge damage during device fabrication 有权
标题翻译：在器件制造期间保护NROM器件免受诱发电荷损伤的方法和结构
公开(公告)号：US06869844B1
公开(公告)日：2005-03-22
申请号：US10701780
申请日：2003-11-05
申请人： Zhizheng Liu , Yider Wu , Jean Yee-Mei Yang
发明人： Zhizheng Liu , Yider Wu , Jean Yee-Mei Yang
IPC分类号： H01L21/336 , H01L21/8246 , H01L27/02 , H01L27/105 , H01L27/115
CPC分类号： H01L27/105 , H01L27/0248 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： A structure for protecting an NROM from induced charge damage during device fabrication is described. The structure provides a discharge path for charge accumulated on the polygate layer during fabrication while providing sufficient isolation to ensure normal circuit operation.
摘要翻译：描述了在器件制造期间保护NROM免受感应电荷损伤的结构。该结构提供了在制造期间积聚在多晶硅层上的电荷的放电路径，同时提供足够的隔离以确保正常的电路操作。

6. 发明授权

US07078749B1 Memory structure having tunable interlayer dielectric and method for fabricating same 有权
标题翻译：具有可调谐层间电介质的记忆结构及其制造方法
公开(公告)号：US07078749B1
公开(公告)日：2006-07-18
申请号：US10618156
申请日：2003-07-11
申请人： Jean Yee-Mei Yang , Yider Wu
发明人： Jean Yee-Mei Yang , Yider Wu
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , G02F1/1334 , H01L29/792
摘要： According to one embodiment, a memory structure comprises a substrate having a channel region situated between a source region and a drain region. The memory structure further comprises a gate layer formed over the channel region of the substrate, and a tunable interlayer dielectric formed over the gate layer and the substrate. The tunable interlayer dielectric has a transparent state and an opaque state, and comprises a matrix and electrically or magnetically tunable material situated within the matrix. During the transparent state, UV rays can pass through the tunable interlayer dielectric to the gate layer, e.g., to perform a UV erase operation. During the opaque state, UV rays are prevented from passing through the tunable interlayer dielectric to the gate layer, thereby protecting the gate layer against unwanted charge storage and extrinsic damage that may occur during various processes.
摘要翻译：根据一个实施例，存储器结构包括具有位于源极区域和漏极区域之间的沟道区域的衬底。存储器结构还包括形成在衬底的沟道区上的栅极层和形成在栅极层和衬底上的可调谐层间电介质。可调谐层间电介质具有透明状态和不透明状态，并且包括位于基体内的矩阵和电或磁性可调谐材料。在透明状态期间，紫外线可以通过可调谐层间电介质到达栅极层，例如进行UV擦除操作。在不透明状态期间，防止紫外线通过可调谐层间电介质到栅极层，从而保护栅极层免于不必要的电荷存储和在各种过程中可能发生的外在损伤。

7. 发明授权

US06897533B1 Multi-bit silicon nitride charge-trapping non-volatile memory cell 有权
标题翻译：多位氮化硅电荷捕获非易失性存储单元
公开(公告)号：US06897533B1
公开(公告)日：2005-05-24
申请号：US10247641
申请日：2002-09-18
申请人： Jean Yee-Mei Yang , Yider Wu
发明人： Jean Yee-Mei Yang , Yider Wu
IPC分类号： G11C16/04 , H01L21/28 , H01L29/423 , H01L29/788 , H01L29/792 , H01L29/02
CPC分类号： H01L29/7923 , G11C16/0475 , H01L21/28282 , H01L29/42332 , H01L29/7887
摘要： A non-volatile multi-bit memory cell is presented which comprises a source, a drain, a channel coupling the source and the drain, and a gate with a plurality of charge trapping regions located so that a trapped charge in each charge trapping region is enabled to affect the influence of the gate voltage on the flow of electrons in the channel. The charge trapping regions are in multiple layers of oxide/nitride/oxide and there can be multiple levels of charge trapping regions. Charges are stored in the nitride layers and isolated by the oxide layers.
摘要翻译：提出了一种非易失性多位存储单元，其包括源极，漏极，耦合源极和漏极的沟道以及具有多个电荷俘获区域的栅极，所述多个电荷俘获区域被定位成使得每个电荷俘获区域中的俘获电荷为能够影响栅极电压对通道中电子流的影响。电荷捕获区域处于多层氧化物/氮化物/氧化物中，并且可以有多个电荷俘获区域。电荷存储在氮化物层中并被氧化层隔离。

8. 发明授权

US06440797B1 Nitride barrier layer for protection of ONO structure from top oxide loss in a fabrication of SONOS flash memory 有权
标题翻译：用于在SONOS闪存的制造中保护ONO结构免受顶部氧化物损失的氮化物阻挡层
公开(公告)号：US06440797B1
公开(公告)日：2002-08-27
申请号：US09966702
申请日：2001-09-28
申请人： Yider Wu , Jean Yee-Mei Yang , Mark Ramsbey , Emmanuel H. Lingunis , Yu Sun
发明人： Yider Wu , Jean Yee-Mei Yang , Mark Ramsbey , Emmanuel H. Lingunis , Yu Sun
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L27/115 , Y10S438/954
摘要： A method for fabricating a SONOS device having a buried bit-line including the steps of: providing a semiconductor substrate having an ONO structure overlying the semiconductor substrate; forming a nitride barrier layer on the ONO structure to form a four-layer stack; forming a patterned photoresist layer on the nitride barrier layer; implanting As or P ions through the four-layer stack to form a bit-line buried under the ONO structure; stripping the photoresist layer and cleaning an upper surface of the four-layer stack; and consolidating the four-layer stack by applying an oxidation cycle. The invention further relates to a SONOS-type device including the nitride barrier layer.
摘要翻译：一种用于制造具有掩埋位线的SONOS器件的方法，包括以下步骤：提供具有覆盖在半导体衬底上的ONO结构的半导体衬底; 在ONO结构上形成氮化物阻挡层以形成四层堆叠; 在所述氮化物阻挡层上形成图案化的光致抗蚀剂层; 将As或P离子注入四层堆叠中以形成埋在ONO结构下的位线; 剥离光致抗蚀剂层并清洁四层堆叠的上表面; 并通过施加氧化循环来合并四层堆叠。本发明还涉及包括氮化物阻挡层的SONOS型器件。

9. 发明授权

US06797565B1 Methods for fabricating and planarizing dual poly scalable SONOS flash memory 有权
标题翻译：双重可扩展SONOS闪存的制造和平面化方法
公开(公告)号：US06797565B1
公开(公告)日：2004-09-28
申请号：US10244369
申请日：2002-09-16
申请人： Jean Yee-Mei Yang , Yider Wu , Zhizheng Liu
发明人： Jean Yee-Mei Yang , Yider Wu , Zhizheng Liu
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/115
摘要： Methods are disclosed for fabricating dual bit SONOS flash memory cells, comprising forming polysilicon gate structures over an ONO layer, and doping source/drain regions of the substrate using the gate structures as an implant mask. Methods are also disclosed in which dielectric material is formed over and between the gate structures, and the wafer is planarized using an STI CMP process to remove dielectric material over the polysilicon gate structures.
摘要翻译：公开了用于制造双位SONOS闪速存储器单元的方法，包括在ONO层上形成多晶硅栅极结构，以及使用栅极结构作为注入掩模来掺杂衬底的源极/漏极区域。还公开了在栅极结构之上和栅极结构之间形成电介质材料的方法，并且使用STI CMP工艺对晶片进行平面化以去除多晶硅栅极结构上的电介质材料。

10. 发明授权

US06436768B1 Source drain implant during ONO formation for improved isolation of SONOS devices 有权
标题翻译：在ONO形成期间的源极漏极注入，以改善SONOS器件的隔离
公开(公告)号：US06436768B1
公开(公告)日：2002-08-20
申请号：US09893279
申请日：2001-06-27
申请人： Jean Yee-Mei Yang , Mark T. Ramsbey , Emmanuil Manos Lingunis , Yider Wu , Tazrien Kamal , Yi He , Edward Hsia , Hidehiko Shiraiwa
发明人： Jean Yee-Mei Yang , Mark T. Ramsbey , Emmanuil Manos Lingunis , Yider Wu , Tazrien Kamal , Yi He , Edward Hsia , Hidehiko Shiraiwa
IPC分类号： H01L21336
CPC分类号： H01L21/2652 , H01L21/2658 , H01L27/11568 , H01L29/66833
摘要： One aspect of the present invention relates to a method of forming a SONOS type non-volatile semiconductor memory device, involving forming a first layer of a charge trapping dielectric on a semiconductor substrate; forming a second layer of the charge trapping dielectric over the first layer of the charge trapping dielectric on the semiconductor substrate; optionally at least partially forming a third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate; optionally removing the third layer of the charge trapping dielectric; forming a source/drain mask over the charge trapping dielectric; implanting a source/drain implant through the charge trapping dielectric into the semiconductor substrate; optionally removing the third layer of the charge trapping dielectric; and one of forming the third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate, reforming the third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate, or forming additional material over the third layer of the charge trapping dielectric.
摘要翻译：本发明的一个方面涉及一种形成SONOS型非易失性半导体存储器件的方法，包括在半导体衬底上形成电荷俘获电介质的第一层; 在所述半导体衬底上的所述电荷俘获电介质的所述第一层上形成所述电荷俘获电介质的第二层; 可选地至少部分地在所述半导体衬底上的所述电荷俘获电介质的所述第二层上形成所述电荷俘获电介质的第三层; 任选地去除电荷俘获电介质的第三层; 在电荷俘获电介质上形成源极/漏极掩模; 将源极/漏极注入物通过电荷俘获电介质注入到半导体衬底中; 任选地去除电荷俘获电介质的第三层; 以及在半导体衬底上的电荷俘获电介质的第二层上形成电荷俘获电介质的第三层之一，在半导体衬底上的电荷俘获电介质的第二层上重整第三层电荷俘获电介质，或在电荷俘获电介质的第三层上形成附加材料。

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