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1. 发明授权

US06797565B1 Methods for fabricating and planarizing dual poly scalable SONOS flash memory 有权
标题翻译：双重可扩展SONOS闪存的制造和平面化方法
公开(公告)号：US06797565B1
公开(公告)日：2004-09-28
申请号：US10244369
申请日：2002-09-16
申请人： Jean Yee-Mei Yang , Yider Wu , Zhizheng Liu
发明人： Jean Yee-Mei Yang , Yider Wu , Zhizheng Liu
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/115
摘要： Methods are disclosed for fabricating dual bit SONOS flash memory cells, comprising forming polysilicon gate structures over an ONO layer, and doping source/drain regions of the substrate using the gate structures as an implant mask. Methods are also disclosed in which dielectric material is formed over and between the gate structures, and the wafer is planarized using an STI CMP process to remove dielectric material over the polysilicon gate structures.
摘要翻译：公开了用于制造双位SONOS闪速存储器单元的方法，包括在ONO层上形成多晶硅栅极结构，以及使用栅极结构作为注入掩模来掺杂衬底的源极/漏极区域。还公开了在栅极结构之上和栅极结构之间形成电介质材料的方法，并且使用STI CMP工艺对晶片进行平面化以去除多晶硅栅极结构上的电介质材料。

2. 发明授权

US06869844B1 Method and structure for protecting NROM devices from induced charge damage during device fabrication 有权
标题翻译：在器件制造期间保护NROM器件免受诱发电荷损伤的方法和结构
公开(公告)号：US06869844B1
公开(公告)日：2005-03-22
申请号：US10701780
申请日：2003-11-05
申请人： Zhizheng Liu , Yider Wu , Jean Yee-Mei Yang
发明人： Zhizheng Liu , Yider Wu , Jean Yee-Mei Yang
IPC分类号： H01L21/336 , H01L21/8246 , H01L27/02 , H01L27/105 , H01L27/115
CPC分类号： H01L27/105 , H01L27/0248 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： A structure for protecting an NROM from induced charge damage during device fabrication is described. The structure provides a discharge path for charge accumulated on the polygate layer during fabrication while providing sufficient isolation to ensure normal circuit operation.
摘要翻译：描述了在器件制造期间保护NROM免受感应电荷损伤的结构。该结构提供了在制造期间积聚在多晶硅层上的电荷的放电路径，同时提供足够的隔离以确保正常的电路操作。

3. 发明授权

US07553727B2 Using implanted poly-1 to improve charging protection in dual-poly process 有权
标题翻译：使用植入poly-1改善双重聚合过程中的充电保护
公开(公告)号：US07553727B2
公开(公告)日：2009-06-30
申请号：US11724726
申请日：2007-03-16
申请人： Ming-Sang Kwan , Bradley Marc Davis , Jean Yee-Mei Yang , Zhizheng Liu , Yi He
发明人： Ming-Sang Kwan , Bradley Marc Davis , Jean Yee-Mei Yang , Zhizheng Liu , Yi He
IPC分类号： H01L21/8247
CPC分类号： H01L29/7923 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： The present invention pertains to implementing a dual poly process in forming a transistor based memory device. The process allows a first polysilicon layer to be selectively doped subsequent to deposition of the second polysilicon layer. The doping increases the conductivity of the first polysilicon layer which can achieve a more robust charging protection for multi-bit core array and a more uniform distribution of charge.
摘要翻译：本发明涉及在形成基于晶体管的存储器件中实现双重聚合工艺。该过程允许在沉积第二多晶硅层之后选择性地掺杂第一多晶硅层。该掺杂增加了第一多晶硅层的导电性，其可以实现针对多位磁芯阵列的更强鲁棒的充电保护和更均匀的电荷分布。

4. 发明申请

US20080153269A1 Thin oxide dummy tiling as charge protection 有权
标题翻译：薄氧化虚拟平铺作为电荷保护
公开(公告)号：US20080153269A1
公开(公告)日：2008-06-26
申请号：US11645475
申请日：2006-12-26
申请人： Cinti Chen , Yi He , Wenmei Li , Zhizheng Liu , Ming-Sang Kwan , Yu Sun , Jean Yee-Mei Yang
发明人： Cinti Chen , Yi He , Wenmei Li , Zhizheng Liu , Ming-Sang Kwan , Yu Sun , Jean Yee-Mei Yang
IPC分类号： H01L21/20
CPC分类号： H01L27/115 , H01L27/0207 , H01L27/11568
摘要： The present invention pertains to a system and method for implementing dummy tiles in forming a memory device. The system and method involves forming at least a portion of a memory core array upon a semiconductor substrate comprising, forming STI structures in the substrate, depositing an oxide layer over the substrate, forming a first polysilicon layer over the oxide layer, doping the first polysilicon layer, forming a second polysilicon layer over the first polysilicon layer, patterning at least one memory core, patterning at least one dummy tile and performing back end processing.
摘要翻译：本发明涉及在形成存储器件时实现虚拟瓦片的系统和方法。该系统和方法包括在半导体衬底上形成存储芯阵列的至少一部分，包括：在衬底中形成STI结构，在衬底上沉积氧化层，在氧化物层上形成第一多晶硅层，掺杂第一多晶硅层，在第一多晶硅层上形成第二多晶硅层，图案化至少一个存储器芯，图案化至少一个虚拟贴片并执行后端处理。

5. 发明授权

US07977218B2 Thin oxide dummy tiling as charge protection 有权
标题翻译：薄氧化虚拟平铺作为电荷保护
公开(公告)号：US07977218B2
公开(公告)日：2011-07-12
申请号：US11645475
申请日：2006-12-26
申请人： Cinti Chen , Yi He , Wenmei Li , Zhizheng Liu , Ming-Sang Kwan , Yu Sun , Jean Yee-Mei Yang
发明人： Cinti Chen , Yi He , Wenmei Li , Zhizheng Liu , Ming-Sang Kwan , Yu Sun , Jean Yee-Mei Yang
IPC分类号： H01L21/00
CPC分类号： H01L27/115 , H01L27/0207 , H01L27/11568
摘要： Novel fabrication methods implement the use of dummy tiles to avoid the effects of in-line charging, ESD events, and such charge effects in the formation of a memory device region region. One method involves forming at least a portion of a memory core array upon a semiconductor substrate that involves forming STI structures in the substrate substantially surrounding a memory device region region within the array. An oxide layer is formed over the substrate in the memory device region region and over the STI's, wherein an inner section of the oxide layer formed over the memory device region region is thicker than an outer section of the oxide layer formed over the STI's. A first polysilicon layer is then formed over the inner and outer sections comprising one or more dummy tiles formed over one or more outer sections and electrically connected to at least one inner section.
摘要翻译：新颖的制造方法实现使用虚拟瓦片以避免在形成存储器件区域区域中的在线充电，ESD事件和这种电荷效应的影响。一种方法包括在半导体衬底上形成至少一部分存储器芯阵列，该半导体衬底涉及在衬底中形成基本上围绕阵列内的存储器件区域区域的STI结构。在存储器件区域和STI之上的衬底上形成氧化物层，其中形成在存储器件区域上的氧化物层的内部部分比在STI上形成的氧化物层的外部部分更厚。然后在内部和外部部分上形成第一多晶硅层，包括形成在一个或多个外部部分上并且电连接到至少一个内部部分的一个或多个虚拟瓦片。

6. 发明申请

US20080150006A1 Using implanted poly-1 to improve charging protection in dual-poly process 有权
标题翻译：使用植入poly-1改善双重聚合过程中的充电保护
公开(公告)号：US20080150006A1
公开(公告)日：2008-06-26
申请号：US11724726
申请日：2007-03-16
申请人： Ming-Sang Kwan , Bradley Marc Davis , Jean Yee-Mei Yang , Zhizheng Liu , Yi He
发明人： Ming-Sang Kwan , Bradley Marc Davis , Jean Yee-Mei Yang , Zhizheng Liu , Yi He
IPC分类号： H01L21/336 , H01L29/792
CPC分类号： H01L29/7923 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： The present invention pertains to implementing a dual poly process in forming a transistor based memory device. The process allows a first polysilicon layer to be selectively doped subsequent to deposition of the second polysilicon layer. The doping increases the conductivity of the first polysilicon layer which can achieve a more robust charging protection for multi-bit core array and a more uniform distribution of charge.
摘要翻译：本发明涉及在形成基于晶体管的存储器件中实现双重聚合工艺。该过程允许在沉积第二多晶硅层之后选择性地掺杂第一多晶硅层。该掺杂增加了第一多晶硅层的导电性，其可以实现针对多位磁芯阵列的更强鲁棒的充电保护和更均匀的电荷分布。

7. 发明授权

US06628545B1 Memory circuit for suppressing bit line current leakage 有权
标题翻译：用于抑制位线电流泄漏的存储电路
公开(公告)号：US06628545B1
公开(公告)日：2003-09-30
申请号：US10306080
申请日：2002-11-26
申请人： Jiang Li , Yider Wu , Zhizheng Liu
发明人： Jiang Li , Yider Wu , Zhizheng Liu
IPC分类号： G11C1604
CPC分类号： G11C16/3404
摘要： A memory circuit employed in a memory device is disclosed. According to one embodiment, the memory circuit comprises a first memory cell and a second memory cell. The first memory cell has a drain terminal connected to a bit line, which is connected to a sensing circuit. The first memory cell also has a control gate connected to a word line. The second memory cell also has a drain terminal connected to the bit line. The second memory cell has its control gate coupled to ground. The memory circuit supplies a source voltage greater than a ground voltage to a source terminal of the first memory cell and to a source terminal of the second memory cell such that the gate-to-source voltage of the second memory cell is less than the threshold voltage of the second memory cell.
摘要翻译：公开了一种在存储器件中使用的存储器电路。根据一个实施例，存储器电路包括第一存储单元和第二存储单元。第一存储单元具有连接到位线的漏极端子，该位线连接到感测电路。第一存储单元还具有连接到字线的控制栅极。第二存储单元还具有连接到位线的漏极端子。第二存储单元的控制栅极接地。存储器电路将大于接地电压的源极电压提供给第一存储单元的源极端子和第二存储器单元的源极端子，使得第二存储器单元的栅极 - 源极电压小于阈值第二存储单元的电压。

8. 发明授权

US07573103B1 Back-to-back NPN/PNP protection diodes 有权
标题翻译：背对背NPN / PNP保护二极管
公开(公告)号：US07573103B1
公开(公告)日：2009-08-11
申请号：US11855704
申请日：2007-09-14
申请人： Yi He , Zhizheng Liu , Meng Ding , Wei Zheng
发明人： Yi He , Zhizheng Liu , Meng Ding , Wei Zheng
IPC分类号： H01L27/06
CPC分类号： H01L27/0266 , H01L27/0255
摘要： A device includes a memory device and an NPN or PNP diode coupled to a word-line of the memory device. The NPN diode includes a p-type substrate connected to ground, a well of n-type material formed in the p-type substrate in direct physical contact with the p-type substrate and electrically connected to the p-type substrate via a first metal line, a well of p-type material formed in the first well of n-type material, a first n-type region formed in the well of p-type material in direct physical contact with the well of p-type material and connected to the word line of the memory device, and a first p-type region formed in the well of n-type material in direct physical contact with the well of n-type material and electrically connected to the well of p-type material via a second metal line. The PNP diode includes a n-type substrate connected to ground, a well of p-type material formed in the n-type substrate in direct physical contact with the n-type substrate and electrically connected to the n-type substrate via a first metal line, a well of n-type material formed in the first well of p-type material, a first p-type region formed in the well of n-type material in direct physical contact with the well of n-type material and connected to the word line of the memory device, and a first n-type region formed in the well of p-type material in direct physical contact with the well of p-type material and electrically connected to the well of n-type material via a second metal line.
摘要翻译：一种设备包括存储器件和耦合到存储器件的字线的NPN或PNP二极管。 NPN二极管包括连接到地的p型衬底，在p型衬底中形成的与p型衬底直接物理接触的n型材料的阱，并通过第一金属电连接到p型衬底线，在n型材料的第一阱中形成的p型材料的阱，形成在p型材料的阱中的第一n型区，与p型材料的阱直接物理接触并连接到存储器件的字线和形成在n型材料的阱中的与n型材料的阱直接物理接触并且经由第二p型材料电连接到p型材料的阱的第一p型区域金属线。 PNP二极管包括连接到地的n型衬底，形成在n型衬底中的p型材料的阱与n型衬底直接物理接触并且经由第一金属电连接到n型衬底线，在p型材料的第一阱中形成的n型材料的阱，形成在n型材料的阱中的与n型材料的阱直接物理接触的第一p型区，并连接到存储器件的字线和形成在p型材料的阱中的第一n型区域，其与p型材料的阱直接物理接触并且经由第二类型的n型材料电连接到n型材料的阱金属线。

9. 发明授权

US07432688B2 Soft-transition controller of a synchronous converter 有权
标题翻译：同步转换器的软转换控制器
公开(公告)号：US07432688B2
公开(公告)日：2008-10-07
申请号：US11356701
申请日：2006-02-17
申请人： Zhizheng Liu , Lam D. Vu
发明人： Zhizheng Liu , Lam D. Vu
IPC分类号： G05F1/613
CPC分类号： H02M7/217 , H02M3/1588 , H02M2001/0045 , Y02B70/1466
摘要： The present invention provides a soft-transition controller for use with a synchronous converter having primary and secondary rectifiers. In one embodiment, the soft-transition controller includes a primary driver configured to provide a primary drive signal to the primary rectifier operating in a synchronous mode, while the secondary rectifier is operating in a diode mode, to provide an output voltage of the synchronous rectifier. Additionally, the soft-transition controller also includes a complementary driver coupled to the primary driver and configured to provide a soft-transition drive signal during a transition period, which transfers the secondary rectifier from the diode mode to a synchronous mode while maintaining the output voltage within a predetermined voltage range.
摘要翻译：本发明提供了一种用于具有初级和次级整流器的同步转换器的软转换控制器。在一个实施例中，软转换控制器包括主驱动器，该主驱动器被配置为向次级整流器以同步模式操作提供初级驱动信号，而次级整流器以二极管模式工作，以提供同步整流器的输出电压。此外，软转换控制器还包括耦合到主驱动器并且被配置为在过渡期间提供软转换驱动信号的互补驱动器，其将次级整流器从二极管模式传输到同步模式，同时保持输出电压在预定电压范围内。

10. 发明申请

US20080153274A1 Deep bitline implant to avoid program disturb 有权
标题翻译：深位线植入，以避免程序干扰
公开(公告)号：US20080153274A1
公开(公告)日：2008-06-26
申请号：US11646157
申请日：2006-12-26
申请人： Timothy Thurgate , Yi He , Ming-Sang Kwan , Zhizheng Liu , Xuguang Wang
发明人： Timothy Thurgate , Yi He , Ming-Sang Kwan , Zhizheng Liu , Xuguang Wang
IPC分类号： H01L21/425 , G11C11/34
CPC分类号： H01L27/11568 , G11C5/02 , G11C5/06 , H01L27/115
摘要： A method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising performing front end processing, performing a first bitline implant, or pocket implants, or both into the first bitline spacings to establish buried first bitlines within the substrate, depositing a layer of the spacer material over the charge trapping dielectric and the polysilicon layer features, forming a sidewall spacer adjacent to the charge trapping dielectric and the polysilicon layer features to define second bitline spacings between adjacent memory cells, performing a deep arsenic implant into the second bitline spacings to establish a second bitline within the structure that is deeper than the first bit line, removing the sidewall spacers and performing back end processing.
摘要翻译：一种在半导体衬底上形成双位存储器核心阵列的至少一部分的方法，所述方法包括执行前端处理，执行第一位线注入或袋式注入或二者进入第一位线间隔以建立掩埋的第一位线在衬底内，在电荷俘获电介质和多晶硅层特征之上沉积间隔物材料层，形成与电荷俘获电介质相邻的侧壁隔离层和多晶硅层特征以限定相邻存储器单元之间的第二位线间隔，执行深度砷注入到第二位线间隔中，以在结构内建立比第一位线更深的第二位线，去除侧壁间隔件并执行后端处理。

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