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1. 发明申请

US20050145970A1 Schottky diode with silver layer contacting the ZnO and MgxZn1-xO films 有权
标题翻译：具有银层的肖特基二极管与ZnO和MgxZn1-xO膜接触
公开(公告)号：US20050145970A1
公开(公告)日：2005-07-07
申请号：US11042533
申请日：2005-01-25
申请人： Yicheng Lu , Haifeng Sheng , Sriram Muthukumar , Nuri Emanetoglu , Jian Zhong , Shaohua Liang
发明人： Yicheng Lu , Haifeng Sheng , Sriram Muthukumar , Nuri Emanetoglu , Jian Zhong , Shaohua Liang
IPC分类号： H01L31/0224 , H01L31/0392 , H01L31/108 , H01L31/112 , H01L29/84
CPC分类号： H01L31/0392 , H01L31/022408 , H01L31/108 , H01L31/1123 , Y02E10/50
摘要： In the present invention, there is provided semiconductor devices such as a Schottky UV photodetector fabricated on n-type ZnO and MgxZn1-xO epitaxial films. The ZnO and MgxZn1-xO films are grown on R-plane sapphire substrates and the Schottky diodes are fabricated on the ZnO and MgxZn1-xO films using silver and aluminum as Schottky and ohmic contact metals, respectively. The Schottky diodes have circular patterns, where the inner circle is the Schottky contact, and the outside ring is the ohmic contact. Ag Schottky contact patterns are fabricated using standard liftoff techniques, while the Al ohmic contact patterns are formed using wet chemical etching. These detectors show low frequency photoresponsivity, high speed photoresponse, lower leakage current and low noise performance as compared to their photoconductive counterparts. This invention is also applicable to optical modulators, Metal Semiconductor Field Effect Transistors (MESFETs) and more.
摘要翻译：在本发明中，提供了半导体器件，例如在n型ZnO和Mg x 1 Zn 1-x O O外延膜上制造的肖特基UV光电探测器。 ZnO和Mg x Zn 1-x O薄膜生长在R平面蓝宝石衬底上，肖特基二极管制造在ZnO和Mg < 分别使用银和铝作为肖特基和欧姆接触金属的ZnO 1-x O O膜。肖特基二极管具有圆形图案，其中内圆是肖特基接触，外环是欧姆接触。 Ag肖特基接触图案使用标准剥离技术制造，而Al欧姆接触图案是使用湿化学蚀刻法形成的。与其感光对手相比，这些检测器显示低频光响应，高速光响应，较低的漏电流和低噪声性能。本发明还可应用于光学调制器，金属半导体场效应晶体管（MESFET）等。

2. 发明授权

US07400030B2 Schottky diode with silver layer contacting the ZnO and MgxZn1−xO films 有权
标题翻译：具有银层的肖特基二极管与ZnO和MgxZn1-xO膜接触
公开(公告)号：US07400030B2
公开(公告)日：2008-07-15
申请号：US11042533
申请日：2005-01-25
申请人： Yicheng Lu , Haifeng Sheng , Sriram Muthukumar , Nuri William Emanetoglu , Jian Zhong , Shaohua Liang
发明人： Yicheng Lu , Haifeng Sheng , Sriram Muthukumar , Nuri William Emanetoglu , Jian Zhong , Shaohua Liang
IPC分类号： H01L29/04
CPC分类号： H01L31/0392 , H01L31/022408 , H01L31/108 , H01L31/1123 , Y02E10/50
摘要： In the present invention, there is provided semiconductor devices such as a Schottky UV photodetector fabricated on n-type ZnO and MgxZn1-xO epitaxial films. The ZnO and MgxZn1-xO films are grown on R-plane sapphire substrates and the Schottky diodes are fabricated on the ZnO and MgxZn1-xO films using silver and aluminum as Schottky and ohmic contact metals, respectively. The Schottky diodes have circular patterns, where the inner circle is the Schottky contact, and the outside ring is the ohmic contact. Ag Schottky contact patterns are fabricated using standard liftoff techniques, while the Al ohmic contact patterns are formed using wet chemical etching. These detectors show low frequency photoresponsivity, high speed photoresponse, lower leakage current and low noise performance as compared to their photoconductive counterparts. This invention is also applicable to optical modulators, Metal Semiconductor Field Effect Transistors (MESFETs) and more.
摘要翻译：在本发明中，提供了半导体器件，例如在n型ZnO和Mg x 1 Zn 1-x O O外延膜上制造的肖特基UV光电探测器。 ZnO和Mg x Zn 1-x O薄膜生长在R平面蓝宝石衬底上，肖特基二极管制造在ZnO和Mg < 分别使用银和铝作为肖特基和欧姆接触金属的ZnO 1-x O O膜。肖特基二极管具有圆形图案，其中内圆是肖特基接触，外环是欧姆接触。 Ag肖特基接触图案使用标准剥离技术制造，而Al欧姆接触图案是使用湿化学蚀刻法形成的。与其感光对手相比，这些检测器显示低频光响应，高速光响应，较低的漏电流和低噪声性能。本发明还可应用于光学调制器，金属半导体场效应晶体管（MESFET）等。

3. 发明授权

US06846731B2 Schottky diode with silver layer contacting the ZnO and MgxZn1-xO films 失效
标题翻译：具有银层的肖特基二极管与ZnO和MgxZn1-xO膜接触
公开(公告)号：US06846731B2
公开(公告)日：2005-01-25
申请号：US10158540
申请日：2002-05-30
申请人： Yicheng Lu , Haifeng Sheng , Sriram Muthukumar , Nuri William Emanetoglu , Jian Zhong
发明人： Yicheng Lu , Haifeng Sheng , Sriram Muthukumar , Nuri William Emanetoglu , Jian Zhong
IPC分类号： H01L31/0224 , H01L31/0392 , H01L31/108 , H01L31/112 , H01L21/28
CPC分类号： H01L31/0392 , H01L31/022408 , H01L31/108 , H01L31/1123 , Y02E10/50
摘要： In the present invention, there is provided semiconductor devices such as a Schottky UV photodetector fabricated on n-type ZnO and MgxZn1-xO epitaxial films. The ZnO and MgxZn1-xO films are grown on R-plane sapphire substrates and the Schottky diodes are fabricated on the ZnO and MgxZn1-xO films using silver and aluminum as Schottky and ohmic contact metals, respectively. The Schottky diodes have circular patterns, where the inner circle is the Schottky contact, and the outside ring is the ohmic contact. Ag Schottky contact patterns are fabricated using standard liftoff techniques, while the Al ohmic contact patterns are formed using wet chemical etching. These detectors show low frequency photoresponsivity, high speed photoresponse, lower leakage current and low noise performance as compared to their photoconductive counterparts. This invention is also applicable to optical modulators, Metal Semiconductor Field Effect Transistors (MESFETs) and more.
摘要翻译：在本发明中，提供了在n型ZnO和Mg x Zn 1-x O外延膜上制造的肖特基UV光电探测器等半导体器件。 ZnO和MgxZn1-xO膜在R平面蓝宝石衬底上生长，肖特基二极管分别用银和铝作为肖特基和欧姆接触金属制作在ZnO和Mg x Zn 1-x O膜上。肖特基二极管具有圆形图案，其中内圆是肖特基接触，外环是欧姆接触。 Ag肖特基接触图案使用标准剥离技术制造，而Al欧姆接触图案是使用湿化学蚀刻法形成的。与其感光对手相比，这些检测器显示低频光响应，高速光响应，较低的漏电流和低噪声性能。本发明还可应用于光学调制器，金属半导体场效应晶体管（MESFET）等。

4. 发明申请

US20070151508A1 Zinc oxide nanotip and fabricating method thereof 审中-公开
标题翻译：氧化锌纳米尖端及其制造方法
公开(公告)号：US20070151508A1
公开(公告)日：2007-07-05
申请号：US11311092
申请日：2005-12-19
申请人： Yicheng Lu , Sriram Muthukumar , Nuri Emanetoglu
发明人： Yicheng Lu , Sriram Muthukumar , Nuri Emanetoglu
IPC分类号： C30B25/00 , C23C16/00 , C30B23/00 , C30B28/12
CPC分类号： B82Y30/00 , B82Y15/00 , C30B25/02 , C30B29/16 , C30B29/60 , H01J1/3044 , H01J9/025 , H01J2201/30446 , Y10S977/811 , Y10T428/24802 , Y10T428/24917
摘要： In the present invention, there are provided self-assembled ZnO nanotips grown on relatively low temperatures on various substrates by metalorganic chemical vapor deposition (MOCVD). The ZnO nanotips are made at relatively low temperatures, giving ZnO a unique advantage over other wide bandgap semiconductors such as GaN and SiC. The nanotips have controlled uniform size, distribution and orientation. These ZnO nanotips are of single crystal quality, show n-type conductivity and have good optical properties. Selective growth of ZnO nanotips also has been realized on patterned (100) silicon on r-sapphire (SOS), and amorphous SiO2 on r-sapphire substrates. Self-assembled ZnO nanotips can also be selectively grown on patterned layers or islands made of a semiconductor, an insulator or a metal deposited on R-plane (01 12) Al2O3 substrates as long as the ZnO grows in a columnar structure along the c-axis [0001] of ZnO on these materials. Such self-assembled ZnO nanotips and nanotip arrays are promising for applications in field emission displays and electron emission sources, photonic bandgap devices, near-field microscopy, UV optoelectronics, and bio-chemical sensors.
摘要翻译：在本发明中，提供了通过金属有机化学气相沉积（MOCVD）在各种基底上在较低温度下生长的自组装的ZnO纳米二极管。 ZnO纳米芯片在相对低的温度下制成，使ZnO比其他宽带隙半导体（如GaN和SiC）具有独特的优势。纳米片具有均匀的尺寸，分布和取向。这些ZnO纳米芯片具有单晶质量，显示n型导电性，并具有良好的光学性能。 ZnO纳米片的选择性生长也已经在r-蓝宝石（SOS）上的图案化（100）硅和r-蓝宝石衬底上的无定形SiO 2上实现。自组装ZnO纳米技术也可以选择性地生长在由半导体，绝缘体或沉积在R平面上的金属（01 12）Al 2 / 只要ZnO沿着这些材料上的ZnO的c轴[0001]以柱状结构生长，就可以进行。这种自组装的ZnO纳米片和纳米尖端阵列对于场发射显示器和电子发射源，光子带隙器件，近场显微镜，UV光电子学和生物化学传感器的应用是有希望的。

5. 发明授权

US06979489B2 Zinc oxide nanotip and fabricating method thereof 失效
标题翻译：氧化锌纳米尖端及其制造方法
公开(公告)号：US06979489B2
公开(公告)日：2005-12-27
申请号：US10243269
申请日：2002-09-13
申请人： Yicheng Lu , Sriram Muthukumar , Nuri William Emanetoglu
发明人： Yicheng Lu , Sriram Muthukumar , Nuri William Emanetoglu
IPC分类号： C30B25/02 , H01J1/304 , H01J9/02 , B32B15/00 , B32B9/04 , B32B3/00
CPC分类号： B82Y30/00 , B82Y15/00 , C30B25/02 , C30B29/16 , C30B29/60 , H01J1/3044 , H01J9/025 , H01J2201/30446 , Y10S977/811 , Y10T428/24802 , Y10T428/24917
摘要： In the present invention, there are provided self-assembled ZnO nanotips grown on relatively low temperatures on various substrates by metalorganic chemical vapor deposition (MOCVD). The ZnO nanotips are made at relatively low temperatures, giving ZnO a unique advantage over other wide bandgap semiconductors such as GaN and SiC. The nanotips have controlled uniform size, distribution and orientation. These ZnO nanotips are of single crystal quality, show n-type conductivity and have good optical properties. Selective growth of ZnO nanotips also has been realized on patterned (100) silicon on r-sapphire (SOS), and amorphous SiO2 on r-sapphire substrates. Self-assembled ZnO nanotips can also be selectively grown on patterned layers or islands made of a semiconductor, an insulator or a metal deposited on R-plane (01{overscore (1)}2) Al2O3 substrates as long as the ZnO grows in a columnar stucture along the c-axis [0001] of ZnO on these materials. Such self-assembled ZnO nanotips and nanotip arrays are promising for applications in field emission displays and electron emission sources, photonic bandgap devices, near-field microscopy, UV optoelectronics, and bio-chemical sensors.
摘要翻译：在本发明中，提供了通过金属有机化学气相沉积（MOCVD）在各种基底上在较低温度下生长的自组装ZnO纳米二极管。 ZnO纳米芯片在相对低的温度下制成，使ZnO比其他宽带隙半导体（如GaN和SiC）具有独特的优势。纳米片具有均匀的尺寸，分布和取向。这些ZnO纳米芯片具有单晶质量，显示n型导电性，并具有良好的光学性能。 ZnO纳米片的选择性生长也已经在r-蓝宝石（SOS）上的图案化（100）硅和r-蓝宝石衬底上的无定形SiO 2上实现。自组装ZnO纳米技术也可以选择性地生长在由R平面上沉积的半导体，绝缘体或金属制成的图案化的层或岛上（01（过滤（12）Al 2 O 2 只要ZnO沿着这些材料上的ZnO的c轴[0001]在柱状结构中生长，这些自组装的ZnO纳米尖端和纳米尖端阵列对于在场发射显示器和电子发射中的应用是有希望的光源带隙器件，近场显微镜，紫外光电子学和生物化学传感器。

6. 发明授权

US09349698B2 Integrated WLUF and SOD process 有权
标题翻译：集成WLUF和SOD过程
公开(公告)号：US09349698B2
公开(公告)日：2016-05-24
申请号：US13534565
申请日：2012-06-27
申请人： Rubayat Mahmud , Saikumar Jayaraman , Sriram Muthukumar
发明人： Rubayat Mahmud , Saikumar Jayaraman , Sriram Muthukumar
IPC分类号： H01L23/48 , H01L23/00 , H01L23/31
CPC分类号： H01L24/05 , H01L23/3157 , H01L24/03 , H01L24/11 , H01L24/13 , H01L24/14 , H01L2224/02126 , H01L2224/0384 , H01L2224/03845 , H01L2224/0391 , H01L2224/0401 , H01L2224/05025 , H01L2224/05147 , H01L2224/05567 , H01L2224/05571 , H01L2224/05647 , H01L2224/1132 , H01L2224/1147 , H01L2224/11474 , H01L2224/1148 , H01L2224/11849 , H01L2224/13007 , H01L2224/13026 , H01L2924/00014 , H01L2924/351 , H01L2924/00012 , H01L2224/05552
摘要： This disclosure relates generally to a wafer having a plurality of semiconductor chips having a major surface, a metal contact positioned on one of the plurality of semiconductor chips and having a side surface and contact surface, the contact surface substantially parallel to the major surface, wherein the contact surface defines a thickness of the metal contact relative to the major surface, an underfill layer abutting the one of the plurality of semiconductor chips and the side surface of the metal contact, the underfill layer having a top surface substantially parallel to the major surface, wherein the top surface of the underfill layer defines a thickness of the underfill layer relative to the major surface, the thickness of the underfill layer being not greater than the thickness of the metal contact, and a solder bump formed in electrical contact with the contact surface of the metal contact.
摘要翻译：本公开总体上涉及具有多个具有主表面的半导体芯片的晶片，位于多个半导体芯片之一上的金属触点，并且具有侧表面和接触表面，该接触表面基本上平行于主表面，其中所述接触表面限定所述金属接触件相对于所述主表面的厚度，底部填充层邻接所述多个半导体芯片中的一个和所述金属接触件的侧表面，所述底部填充层具有基本上平行于所述主表面的顶表面其中所述底部填充层的顶表面相对于所述主表面限定所述底部填充层的厚度，所述底部填充层的厚度不大于所述金属接触件的厚度，以及形成为与所述触点电接触的焊料凸块表面的金属接触。

7. 发明授权

US08502400B2 Methods and apparatuses to stiffen integrated circuit package 有权
标题翻译：强化集成电路封装的方法和装置
公开(公告)号：US08502400B2
公开(公告)日：2013-08-06
申请号：US13413616
申请日：2012-03-06
申请人： Prasanna Karpur , Sriram Muthukumar
发明人： Prasanna Karpur , Sriram Muthukumar
IPC分类号： H01L23/29 , H01L23/48
CPC分类号： H01L21/563 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/15311 , H01L2924/00
摘要： A dam stiffener for a package substrate is presented. In an embodiment, the dam stiffener comprises a thermally curable polymer, and is simultaneously cured with the underfill material to act as stiffener to the substrate. In another embodiment, a curable reservoir material can be dispensed to fill the space between the integrated circuit die and the dam stiffener, forming a thick reservoir layer, acting as an additional stiffener for the package substrate.
摘要翻译：提出了一种用于封装衬底的大坝加强件。在一个实施方案中，坝加强件包括可热固化的聚合物，并且与底部填充材料同时固化以作为基底的加强件。在另一个实施例中，可以分配可固化储存器材料以填充集成电路管芯和坝加强件之间的空间，形成用作封装衬底的附加加强件的厚的储存层。

8. 发明授权

US08387240B2 Methods for making multi-chip packaging using an interposer 有权
标题翻译：使用插入片进行多芯片封装的方法
公开(公告)号：US08387240B2
公开(公告)日：2013-03-05
申请号：US12955816
申请日：2010-11-29
申请人： Sriram Muthukumar , Raul Mancera , Yoshihiro Tomita , Chi-won Hwang
发明人： Sriram Muthukumar , Raul Mancera , Yoshihiro Tomita , Chi-won Hwang
IPC分类号： H01K3/10
CPC分类号： H01L23/49827 , H01L21/486 , H01L23/147 , H01L25/0655 , H01L2224/81203 , H01L2224/81815 , H01L2924/10253 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49144 , Y10T29/49163 , Y10T29/49165 , H01L2924/00
摘要： In one embodiment, a method includes forming a plurality of vias partially through a body, the vias including sidewalls defined by the body. An electrically insulating layer is formed on the sidewalls and on an upper surface of the body. An electrically conductive layer is formed on the insulating layer in the vias and on the upper surface, the electrically conductive layer defining first metal pads on the upper surface and second metal pads in contact with the first metal pads, the second metal pads having a denser pitch than the first metal pads. A dielectric layer is formed between adjacent first metal pads and between adjacent second metal pads. The body is thinned through a lower surface and the electrically insulating layer in the vias is exposed. After the thinning, a portion of the electrically insulating layer in the, vias is removed. The body is coupled to a substrate.
摘要翻译：在一个实施例中，一种方法包括通过主体部分地形成多个通孔，通孔包括由身体限定的侧壁。电绝缘层形成在主体的侧壁和上表面上。在通孔和上表面上的绝缘层上形成导电层，导电层限定上表面上的第一金属焊盘和与第一金属焊盘接触的第二金属焊盘，第二金属焊盘具有较密的间距比第一金属垫。在相邻的第一金属焊盘之间和相邻的第二金属焊盘之间形成介电层。身体通过下表面变薄，并且通孔中的电绝缘层被暴露。在变薄之后，去除通孔中的电绝缘层的一部分。主体耦合到基板。

9. 发明授权

US08030782B2 Metal-metal bonding of compliant interconnect 有权
标题翻译：金属 - 金属接合兼容互连
公开(公告)号：US08030782B2
公开(公告)日：2011-10-04
申请号：US12789886
申请日：2010-05-28
申请人： Shriram Ramanathan , Sriram Muthukumar
发明人： Shriram Ramanathan , Sriram Muthukumar
IPC分类号： H01L23/48
CPC分类号： H01L24/10 , H01L24/13 , H01L2224/05001 , H01L2224/05022 , H01L2224/05548 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05669 , H01L2224/05671 , H01L2224/05681 , H01L2224/13 , H01L2224/13099 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/01073 , H01L2924/01076 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/00 , H01L2224/05099
摘要： Embodiments of the invention provide a first component with a compliant interconnect bonded to a second component with a land pad by a metal to metal bond. In some embodiments, the first component may be a microprocessor die and the second component a package substrate.
摘要翻译：本发明的实施例提供一种第一部件，其具有通过金属与金属粘接的带有焊盘的第二部件与柔性互连件接合。在一些实施例中，第一部件可以是微处理器管芯，而第二部件可以是封装衬底。

10. 发明授权

US07800402B1 Look-up table overdrive circuits 有权
标题翻译：查找表超速电路
公开(公告)号：US07800402B1
公开(公告)日：2010-09-21
申请号：US11982865
申请日：2007-11-05
申请人： Irfan Rahim , Sriram Muthukumar , William Bradley Vest , Myron Wai Wong
发明人： Irfan Rahim , Sriram Muthukumar , William Bradley Vest , Myron Wai Wong
IPC分类号： H03K19/173 , G06F7/38
CPC分类号： H03K19/17736 , H03K19/17728 , H03K19/1778
摘要： A programmable logic device integrated circuit or other integrated circuit may have logic circuitry that produces data signals. The data signals may be routed to other logic circuits through interconnects. The interconnects may be programmable. A level recovery circuit may be used at the end of each interconnect line to strengthen the transmitted data signal. The level recovery circuit that is attached to a given interconnect line may produce true and complementary versions of the data signal that is on that interconnect line. Level shifting circuitry may be provided to boost the data signals on the interconnects. Each interconnect line may have a level shifter circuit that receives the true and complementary versions of a data signal and that produces corresponding boosted true and complementary versions of the data signal. The boosted signals may be provided to the control inputs of complementary-metal-oxide-semiconductor transistor pass gates in programmable look-up table circuitry.
摘要翻译：可编程逻辑器件集成电路或其他集成电路可以具有产生数据信号的逻辑电路。数据信号可以通过互连路由到其他逻辑电路。互连可以是可编程的。可以在每条互连线的末端使用电平恢复电路，以加强传输的数据信号。连接到给定互连线的电平恢复电路可以产生在该互连线上的数据信号的真实和互补版本。可以提供电平移位电路以升高互连上的数据信号。每个互连线可以具有电平移位器电路，其接收数据信号的真实和互补版本并且产生数据信号的相应增强的真实和互补版本。升压的信号可以提供给可编程查找表电路中的互补金属氧化物半导体晶体管栅极的控制输入。

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