专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07400030B2 Schottky diode with silver layer contacting the ZnO and MgxZn1−xO films 有权
标题翻译：具有银层的肖特基二极管与ZnO和MgxZn1-xO膜接触
公开(公告)号：US07400030B2
公开(公告)日：2008-07-15
申请号：US11042533
申请日：2005-01-25
申请人： Yicheng Lu , Haifeng Sheng , Sriram Muthukumar , Nuri William Emanetoglu , Jian Zhong , Shaohua Liang
发明人： Yicheng Lu , Haifeng Sheng , Sriram Muthukumar , Nuri William Emanetoglu , Jian Zhong , Shaohua Liang
IPC分类号： H01L29/04
CPC分类号： H01L31/0392 , H01L31/022408 , H01L31/108 , H01L31/1123 , Y02E10/50
摘要： In the present invention, there is provided semiconductor devices such as a Schottky UV photodetector fabricated on n-type ZnO and MgxZn1-xO epitaxial films. The ZnO and MgxZn1-xO films are grown on R-plane sapphire substrates and the Schottky diodes are fabricated on the ZnO and MgxZn1-xO films using silver and aluminum as Schottky and ohmic contact metals, respectively. The Schottky diodes have circular patterns, where the inner circle is the Schottky contact, and the outside ring is the ohmic contact. Ag Schottky contact patterns are fabricated using standard liftoff techniques, while the Al ohmic contact patterns are formed using wet chemical etching. These detectors show low frequency photoresponsivity, high speed photoresponse, lower leakage current and low noise performance as compared to their photoconductive counterparts. This invention is also applicable to optical modulators, Metal Semiconductor Field Effect Transistors (MESFETs) and more.
摘要翻译：在本发明中，提供了半导体器件，例如在n型ZnO和Mg x 1 Zn 1-x O O外延膜上制造的肖特基UV光电探测器。 ZnO和Mg x Zn 1-x O薄膜生长在R平面蓝宝石衬底上，肖特基二极管制造在ZnO和Mg < 分别使用银和铝作为肖特基和欧姆接触金属的ZnO 1-x O O膜。肖特基二极管具有圆形图案，其中内圆是肖特基接触，外环是欧姆接触。 Ag肖特基接触图案使用标准剥离技术制造，而Al欧姆接触图案是使用湿化学蚀刻法形成的。与其感光对手相比，这些检测器显示低频光响应，高速光响应，较低的漏电流和低噪声性能。本发明还可应用于光学调制器，金属半导体场效应晶体管（MESFET）等。

2. 发明授权

US06846731B2 Schottky diode with silver layer contacting the ZnO and MgxZn1-xO films 失效
标题翻译：具有银层的肖特基二极管与ZnO和MgxZn1-xO膜接触
公开(公告)号：US06846731B2
公开(公告)日：2005-01-25
申请号：US10158540
申请日：2002-05-30
申请人： Yicheng Lu , Haifeng Sheng , Sriram Muthukumar , Nuri William Emanetoglu , Jian Zhong
发明人： Yicheng Lu , Haifeng Sheng , Sriram Muthukumar , Nuri William Emanetoglu , Jian Zhong
IPC分类号： H01L31/0224 , H01L31/0392 , H01L31/108 , H01L31/112 , H01L21/28
CPC分类号： H01L31/0392 , H01L31/022408 , H01L31/108 , H01L31/1123 , Y02E10/50
摘要： In the present invention, there is provided semiconductor devices such as a Schottky UV photodetector fabricated on n-type ZnO and MgxZn1-xO epitaxial films. The ZnO and MgxZn1-xO films are grown on R-plane sapphire substrates and the Schottky diodes are fabricated on the ZnO and MgxZn1-xO films using silver and aluminum as Schottky and ohmic contact metals, respectively. The Schottky diodes have circular patterns, where the inner circle is the Schottky contact, and the outside ring is the ohmic contact. Ag Schottky contact patterns are fabricated using standard liftoff techniques, while the Al ohmic contact patterns are formed using wet chemical etching. These detectors show low frequency photoresponsivity, high speed photoresponse, lower leakage current and low noise performance as compared to their photoconductive counterparts. This invention is also applicable to optical modulators, Metal Semiconductor Field Effect Transistors (MESFETs) and more.
摘要翻译：在本发明中，提供了在n型ZnO和Mg x Zn 1-x O外延膜上制造的肖特基UV光电探测器等半导体器件。 ZnO和MgxZn1-xO膜在R平面蓝宝石衬底上生长，肖特基二极管分别用银和铝作为肖特基和欧姆接触金属制作在ZnO和Mg x Zn 1-x O膜上。肖特基二极管具有圆形图案，其中内圆是肖特基接触，外环是欧姆接触。 Ag肖特基接触图案使用标准剥离技术制造，而Al欧姆接触图案是使用湿化学蚀刻法形成的。与其感光对手相比，这些检测器显示低频光响应，高速光响应，较低的漏电流和低噪声性能。本发明还可应用于光学调制器，金属半导体场效应晶体管（MESFET）等。

3. 发明申请

US20050145970A1 Schottky diode with silver layer contacting the ZnO and MgxZn1-xO films 有权
标题翻译：具有银层的肖特基二极管与ZnO和MgxZn1-xO膜接触
公开(公告)号：US20050145970A1
公开(公告)日：2005-07-07
申请号：US11042533
申请日：2005-01-25
申请人： Yicheng Lu , Haifeng Sheng , Sriram Muthukumar , Nuri Emanetoglu , Jian Zhong , Shaohua Liang
发明人： Yicheng Lu , Haifeng Sheng , Sriram Muthukumar , Nuri Emanetoglu , Jian Zhong , Shaohua Liang
IPC分类号： H01L31/0224 , H01L31/0392 , H01L31/108 , H01L31/112 , H01L29/84
CPC分类号： H01L31/0392 , H01L31/022408 , H01L31/108 , H01L31/1123 , Y02E10/50
摘要： In the present invention, there is provided semiconductor devices such as a Schottky UV photodetector fabricated on n-type ZnO and MgxZn1-xO epitaxial films. The ZnO and MgxZn1-xO films are grown on R-plane sapphire substrates and the Schottky diodes are fabricated on the ZnO and MgxZn1-xO films using silver and aluminum as Schottky and ohmic contact metals, respectively. The Schottky diodes have circular patterns, where the inner circle is the Schottky contact, and the outside ring is the ohmic contact. Ag Schottky contact patterns are fabricated using standard liftoff techniques, while the Al ohmic contact patterns are formed using wet chemical etching. These detectors show low frequency photoresponsivity, high speed photoresponse, lower leakage current and low noise performance as compared to their photoconductive counterparts. This invention is also applicable to optical modulators, Metal Semiconductor Field Effect Transistors (MESFETs) and more.
摘要翻译：在本发明中，提供了半导体器件，例如在n型ZnO和Mg x 1 Zn 1-x O O外延膜上制造的肖特基UV光电探测器。 ZnO和Mg x Zn 1-x O薄膜生长在R平面蓝宝石衬底上，肖特基二极管制造在ZnO和Mg < 分别使用银和铝作为肖特基和欧姆接触金属的ZnO 1-x O O膜。肖特基二极管具有圆形图案，其中内圆是肖特基接触，外环是欧姆接触。 Ag肖特基接触图案使用标准剥离技术制造，而Al欧姆接触图案是使用湿化学蚀刻法形成的。与其感光对手相比，这些检测器显示低频光响应，高速光响应，较低的漏电流和低噪声性能。本发明还可应用于光学调制器，金属半导体场效应晶体管（MESFET）等。

4. 发明授权

US08183149B1 Method of fabricating a conductive interconnect arrangement for a semiconductor device 有权
标题翻译：制造用于半导体器件的导电互连装置的方法
公开(公告)号：US08183149B1
公开(公告)日：2012-05-22
申请号：US12973373
申请日：2010-12-20
申请人： David M. Permana , Ravi P. Srivastava , Haifeng Sheng , Dimitri R. Kioussis
发明人： David M. Permana , Ravi P. Srivastava , Haifeng Sheng , Dimitri R. Kioussis
IPC分类号： H01L21/4763
CPC分类号： H01L21/76832 , H01L21/31144 , H01L21/76804
摘要： A method of fabricating a semiconductor device is provided. The method begins by providing a semiconductor device structure having electronic devices formed on a semiconductor substrate, and having an upper metal layer associated with electrical contacts for the electronic devices. The method continues by forming a diffusion barrier layer overlying the upper metal layer. Next, the method deposits a first layer of graded ultra-low-k (ULK) material overlying the diffusion barrier layer, a layer of ULK material overlying the first layer of graded ULK material, and a second layer of graded ULK material overlying the layer of ULK material. The method continues by depositing a layer of low temperature oxide material overlying the second layer of graded ULK material, and forming a layer of metal hard mask material overlying the layer of low temperature oxide material.
摘要翻译：提供一种制造半导体器件的方法。该方法开始于提供具有形成在半导体衬底上的电子器件的半导体器件结构，并且具有与电子器件的电触点相关联的上部金属层。该方法通过形成覆盖上金属层的扩散阻挡层而继续。接下来，该方法沉积覆盖扩散阻挡层的第一层级别超低k（ULK）材料，覆盖第一层级ULK材料层的ULK材料层和覆盖层的第二层级别的ULK材料的ULK材料。该方法通过沉积覆盖在第二层级ULK材料层上的低温氧化物层，并且形成覆盖在低温氧化物材料层上的金属硬掩模材料层。

5. 发明申请

US20090315115A1 Implantation for shallow trench isolation (STI) formation and for stress for transistor performance enhancement 审中-公开
标题翻译：用于浅沟槽隔离（STI）形成和用于晶体管性能增强的应力的植入
公开(公告)号：US20090315115A1
公开(公告)日：2009-12-24
申请号：US12214854
申请日：2008-06-23
申请人： Beichao Zhang , Johnny Widodo , Juan Boon Tan , Yong Kong Siew , Fan Zhang , Haifeng Sheng , Wenhe Lin , Young Way Teh , Jinping Liu , Vincent Ho , Liang Choo Hsia
发明人： Beichao Zhang , Johnny Widodo , Juan Boon Tan , Yong Kong Siew , Fan Zhang , Haifeng Sheng , Wenhe Lin , Young Way Teh , Jinping Liu , Vincent Ho , Liang Choo Hsia
IPC分类号： H01L21/8234 , H01L27/088
CPC分类号： H01L21/823481 , H01L21/76224 , H01L29/7846
摘要： A method (and semiconductor device) of fabricating a semiconductor device provides a shallow trench isolation (STI) structure or region by implanting ions in the STI region. After implantation, the region (of substrate material and ions of a different element) is thermally annealed producing a dielectric material operable for isolating two adjacent field-effect transistors (FET). This eliminates the conventional steps of removing substrate material to form the trench and refilling the trench with dielectric material. Implantation of nitrogen ions into an STI region adjacent a p-type FET applies a compressive stress to the transistor channel region to enhance transistor performance. Implantation of oxygen ions into an STI region adjacent an n-type FET applies a tensile stress to the transistor channel region to enhance transistor performance.
摘要翻译：制造半导体器件的方法（和半导体器件）通过在STI区域中注入离子来提供浅沟槽隔离（STI）结构或区域。在植入之后，区域（衬底材料和不同元素的离子）进行热退火，产生用于隔离两个相邻的场效应晶体管（FET）的电介质材料。这消除了去除衬底材料以形成沟槽并用电介质材料重新填充沟槽的常规步骤。将氮离子注入到邻近p型FET的STI区域中，对晶体管沟道区域施加压缩应力以增强晶体管性能。将氧离子注入到与n型FET相邻的STI区域中，对晶体管沟道区域施加拉伸应力以增强晶体管性能。

6. 发明授权

US07993997B2 Poly profile engineering to modulate spacer induced stress for device enhancement 有权
标题翻译：聚轮廓工程用于调制间隔物诱发的应力用于器件增强
公开(公告)号：US07993997B2
公开(公告)日：2011-08-09
申请号：US11865563
申请日：2007-10-01
申请人： Vincent Ho , Wenhe Lin , Young Way Teh , Yong Kong Siew , Bei Chao Zhang , Fan Zhang , Haifeng Sheng , Juan Boon Tan
发明人： Vincent Ho , Wenhe Lin , Young Way Teh , Yong Kong Siew , Bei Chao Zhang , Fan Zhang , Haifeng Sheng , Juan Boon Tan
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/26506 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L29/6659 , H01L29/7833 , H01L29/7845
摘要： The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate.
摘要翻译：本发明提供了一种通过在源/漏退火处理之前将栅极区域施加离子注入来在半导体器件衬底中引起应力的方法。然后可以将栅极/漏极区域与栅极退火，由于所述离子注入将导致栅极在某些区域中膨胀。结果，由栅极的所述膨胀引起的应力被转移到半导体衬底中的沟道区域。

7. 发明申请

US20100001370A1 INTEGRATED CIRCUIT SYSTEM EMPLOYING ALTERNATING CONDUCTIVE LAYERS 有权
标题翻译：集成电路系统采用替代导电层
公开(公告)号：US20100001370A1
公开(公告)日：2010-01-07
申请号：US12168816
申请日：2008-07-07
申请人： Haifeng Sheng , Fan Zhang , Juan Boon Tan , Bei Chao Zhang , Dong Kyun Sohn
发明人： Haifeng Sheng , Fan Zhang , Juan Boon Tan , Bei Chao Zhang , Dong Kyun Sohn
IPC分类号： H01L21/768 , H01L21/02 , H01L27/06
CPC分类号： H01L23/5223 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit system that includes: providing a substrate including front-end-of-line circuitry; forming a first conductive level including a first conductive trace over the substrate; forming a second conductive level spaced apart from the first conductive level and including a second conductive trace; and connecting the first conductive level to a third conductive level with a viabar that passes through the second conductive level without contacting the second conductive trace.
摘要翻译：一种集成电路系统，包括：提供包括前端电路的基板; 形成包括在所述衬底上的第一导电迹线的第一导电电平; 形成与所述第一导电电平间隔开并包括第二导电迹线的第二导电电平; 以及将第一导电电平与通过第二导电电平而不接触第二导电迹线的viabar连接到第三导电电平。

8. 发明申请

US20090085122A1 POLY PROFILE ENGINEERING TO MODULATE SPACER INDUCED STRESS FOR DEVICE ENHANCEMENT 有权
标题翻译： POLY PROFILE工程来调节间隔器感应应变的设备增强
公开(公告)号：US20090085122A1
公开(公告)日：2009-04-02
申请号：US11865563
申请日：2007-10-01
申请人： Vincent Ho , Wenhe Lin , Young Way Teh , Yong Kong Siew , Bei Chao Zhang , Fan Zhang , Haifeng Sheng , Juan Boon Tan
发明人： Vincent Ho , Wenhe Lin , Young Way Teh , Yong Kong Siew , Bei Chao Zhang , Fan Zhang , Haifeng Sheng , Juan Boon Tan
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/26506 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L29/6659 , H01L29/7833 , H01L29/7845
摘要： The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate.
摘要翻译：本发明提供了一种通过在源/漏退火处理之前将栅极区域施加离子注入来在半导体器件衬底中引起应力的方法。然后可以将栅极/漏极区域与栅极退火，由于所述离子注入将导致栅极在某些区域中膨胀。结果，由栅极的所述膨胀引起的应力被转移到半导体衬底中的沟道区域。

9. 发明授权

US09147654B2 Integrated circuit system employing alternating conductive layers 有权
标题翻译：采用交替导电层的集成电路系统
公开(公告)号：US09147654B2
公开(公告)日：2015-09-29
申请号：US12168816
申请日：2008-07-07
申请人： Haifeng Sheng , Fan Zhang , Juan Boon Tan , Bei Chao Zhang , Dong Kyun Sohn
发明人： Haifeng Sheng , Fan Zhang , Juan Boon Tan , Bei Chao Zhang , Dong Kyun Sohn
IPC分类号： H01L23/48 , H01L21/4763 , H01L23/522
CPC分类号： H01L23/5223 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit system that includes: providing a substrate including front-end-of-line circuitry; forming a first conductive level including a first conductive trace over the substrate; forming a second conductive level spaced apart from the first conductive level and including a second conductive trace; and connecting the first conductive level to a third conductive level with a viabar that passes through the second conductive level without contacting the second conductive trace.
摘要翻译：一种集成电路系统，包括：提供包括前端电路的基板; 形成包括在所述衬底上的第一导电迹线的第一导电电平; 形成与所述第一导电电平间隔开并包括第二导电迹线的第二导电电平; 以及将第一导电电平与通过第二导电电平而不接触第二导电迹线的viabar连接到第三导电电平。

10. 发明授权

US08519445B2 Poly profile engineering to modulate spacer induced stress for device enhancement 有权
标题翻译：聚轮廓工程用于调制间隔物诱发的应力用于器件增强
公开(公告)号：US08519445B2
公开(公告)日：2013-08-27
申请号：US13182455
申请日：2011-07-14
申请人： Vincent Ho , Wenhe Lin , Young Way Teh , Yong Kong Siew , Bei Chao Zhang , Fan Zhang , Haifeng Sheng , Juan Boon Tan
发明人： Vincent Ho , Wenhe Lin , Young Way Teh , Yong Kong Siew , Bei Chao Zhang , Fan Zhang , Haifeng Sheng , Juan Boon Tan
IPC分类号： H01L27/10 , H01L21/8238
CPC分类号： H01L21/26506 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L29/6659 , H01L29/7833 , H01L29/7845
摘要： The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate.
摘要翻译：本发明提供了一种通过在源/漏退火处理之前将栅极区域施加离子注入来在半导体器件衬底中引起应力的方法。然后可以将栅极/漏极区域与栅极退火，由于所述离子注入将导致栅极在某些区域中膨胀。结果，由栅极的所述膨胀引起的应力被转移到半导体衬底中的沟道区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式