专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07800402B1 Look-up table overdrive circuits 有权
标题翻译：查找表超速电路
公开(公告)号：US07800402B1
公开(公告)日：2010-09-21
申请号：US11982865
申请日：2007-11-05
申请人： Irfan Rahim , Sriram Muthukumar , William Bradley Vest , Myron Wai Wong
发明人： Irfan Rahim , Sriram Muthukumar , William Bradley Vest , Myron Wai Wong
IPC分类号： H03K19/173 , G06F7/38
CPC分类号： H03K19/17736 , H03K19/17728 , H03K19/1778
摘要： A programmable logic device integrated circuit or other integrated circuit may have logic circuitry that produces data signals. The data signals may be routed to other logic circuits through interconnects. The interconnects may be programmable. A level recovery circuit may be used at the end of each interconnect line to strengthen the transmitted data signal. The level recovery circuit that is attached to a given interconnect line may produce true and complementary versions of the data signal that is on that interconnect line. Level shifting circuitry may be provided to boost the data signals on the interconnects. Each interconnect line may have a level shifter circuit that receives the true and complementary versions of a data signal and that produces corresponding boosted true and complementary versions of the data signal. The boosted signals may be provided to the control inputs of complementary-metal-oxide-semiconductor transistor pass gates in programmable look-up table circuitry.
摘要翻译：可编程逻辑器件集成电路或其他集成电路可以具有产生数据信号的逻辑电路。数据信号可以通过互连路由到其他逻辑电路。互连可以是可编程的。可以在每条互连线的末端使用电平恢复电路，以加强传输的数据信号。连接到给定互连线的电平恢复电路可以产生在该互连线上的数据信号的真实和互补版本。可以提供电平移位电路以升高互连上的数据信号。每个互连线可以具有电平移位器电路，其接收数据信号的真实和互补版本并且产生数据信号的相应增强的真实和互补版本。升压的信号可以提供给可编程查找表电路中的互补金属氧化物半导体晶体管栅极的控制输入。

2. 发明申请

US20100321984A1 CONFIGURATION RANDOM ACCESS MEMORY 有权
标题翻译：配置随机存取存储器
公开(公告)号：US20100321984A1
公开(公告)日：2010-12-23
申请号：US12868575
申请日：2010-08-25
申请人： Irfan Rahim , Andy L. Lee , Myron Wai Wong , William Bradley Vest , Jeffrey T. Watt
发明人： Irfan Rahim , Andy L. Lee , Myron Wai Wong , William Bradley Vest , Jeffrey T. Watt
IPC分类号： G11C11/24
CPC分类号： H03K19/1776 , G11C11/401 , G11C11/404 , G11C14/00 , H03K19/1778
摘要： Integrated circuits such as programmable logic device integrated circuits are provided that have configuration random-access memory elements. The configuration random-access memory elements are loaded with configuration data to customize programmable logic on the integrated circuits. Each memory element has a capacitor that stores data for that memory element. A pair of cross-coupled inverters are connected to the capacitor. The inverters ensure that the memory elements produce output control signals with voltages than range from one power supply rail to another. Each configuration random-access memory element may have a clear transistor. The capacitor may be formed in a dielectric layer that lies above the transistors of the inverters, the address transistor, and the clear transistor. The inverters may be powered with an elevated power supply voltage.
摘要翻译：提供了诸如可编程逻辑器件集成电路的集成电路，其具有配置随机存取存储器元件。配置随机存取存储器元件装载有配置数据以在集成电路上定制可编程逻辑。每个存储器元件具有存储该存储器元件的数据的电容器。一对交叉耦合的反相器连接到电容器。逆变器确保存储元件产生的输出控制信号的电压低于从一个电源轨到另一个电源的范围。每个配置随机存取存储器元件可以具有透明晶体管。电容器可以形成在位于反相器，地址晶体管和透明晶体管的晶体管之上的电介质层中。逆变器可以用升高的电源电压供电。

3. 发明授权

US08030962B2 Configuration random access memory 有权
标题翻译：配置随机存取存储器
公开(公告)号：US08030962B2
公开(公告)日：2011-10-04
申请号：US12868575
申请日：2010-08-25
申请人： Irfan Rahim , Andy L. Lee , Myron Wai Wong , William Bradley Vest , Jeffrey T. Watt
发明人： Irfan Rahim , Andy L. Lee , Myron Wai Wong , William Bradley Vest , Jeffrey T. Watt
IPC分类号： H03K19/173
CPC分类号： H03K19/1776 , G11C11/401 , G11C11/404 , G11C14/00 , H03K19/1778
摘要： Integrated circuits such as programmable logic device integrated circuits are provided that have configuration random-access memory elements. The configuration random-access memory elements are loaded with configuration data to customize programmable logic on the integrated circuits. Each memory element has a capacitor that stores data for that memory element. A pair of cross-coupled inverters are connected to the capacitor. The inverters ensure that the memory elements produce output control signals with voltages than range from one power supply rail to another. Each configuration random-access memory element may have a clear transistor. The capacitor may be formed in a dielectric layer that lies above the transistors of the inverters, the address transistor, and the clear transistor. The inverters may be powered with an elevated power supply voltage.
摘要翻译：提供了诸如可编程逻辑器件集成电路的集成电路，其具有配置随机存取存储器元件。配置随机存取存储器元件装载有配置数据以在集成电路上定制可编程逻辑。每个存储器元件具有存储该存储器元件的数据的电容器。一对交叉耦合的反相器连接到电容器。逆变器确保存储元件产生的输出控制信号的电压低于从一个电源轨到另一个电源的范围。每个配置随机存取存储器元件可以具有透明晶体管。电容器可以形成在位于反相器，地址晶体管和透明晶体管的晶体管之上的电介质层中。逆变器可以用升高的电源电压供电。

4. 发明申请

US20080169836A1 Configuration random access memory 有权
标题翻译：配置随机存取存储器
公开(公告)号：US20080169836A1
公开(公告)日：2008-07-17
申请号：US11653001
申请日：2007-01-12
申请人： Irfan Rahim , Andy L. Lee , Myron Wai Wong , William Bradley Vest , Jeffrey T. Watt
发明人： Irfan Rahim , Andy L. Lee , Myron Wai Wong , William Bradley Vest , Jeffrey T. Watt
IPC分类号： H03K19/094 , G11C5/02
CPC分类号： H03K19/1776 , G11C11/401 , G11C11/404 , G11C14/00 , H03K19/1778
摘要： Integrated circuits such as programmable logic device integrated circuits are provided that have configuration random-access memory elements. The configuration random-access memory elements are loaded with configuration data to customize programmable logic on the integrated circuits. Each memory element has a capacitor that stores data for that memory element. A pair of cross-coupled inverters are connected to the capacitor. The inverters ensure that the memory elements produce output control signals with voltages than range from one power supply rail to another. Each configuration random-access memory element may have a clear transistor. The capacitor may be formed in a dielectric layer that lies above the transistors of the inverters, the address transistor, and the clear transistor. The inverters may be powered with an elevated power supply voltage.
摘要翻译：提供了诸如可编程逻辑器件集成电路的集成电路，其具有配置随机存取存储器元件。配置随机存取存储器元件装载有配置数据以在集成电路上定制可编程逻辑。每个存储器元件具有存储该存储器元件的数据的电容器。一对交叉耦合的反相器连接到电容器。逆变器确保存储元件产生的输出控制信号的电压低于从一个电源轨到另一个电源的范围。每个配置随机存取存储器元件可以具有透明晶体管。电容器可以形成在位于反相器，地址晶体管和透明晶体管的晶体管之上的电介质层中。逆变器可以用升高的电源电压供电。

5. 发明申请

US20100148304A1 INTEGRATED CIRCUIT DECOUPLING CAPACITORS 有权
标题翻译：集成电路解耦电容器
公开(公告)号：US20100148304A1
公开(公告)日：2010-06-17
申请号：US12332928
申请日：2008-12-11
申请人： Irfan Rahim , William Bradley Vest , Myron Wai Wong
发明人： Irfan Rahim , William Bradley Vest , Myron Wai Wong
IPC分类号： H01L29/00
CPC分类号： H01L27/0805 , H01L23/5223 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： Power supply decoupling capacitors are provided for integrated circuits. The decoupling capacitors may be distributed in clusters amongst powered circuit components. Each cluster may contain a number of individual capacitor cells that are connected in parallel. Each capacitor cell may contain a capacitor and a resistor connected in series with the capacitor. The capacitors may be metal-insulator-metal (MIM) capacitors. The resistor in each cell may limit the current through an individual capacitor in the event of a short in the capacitor due to a dielectric defect.
摘要翻译：为集成电路提供电源去耦电容。去耦电容器可以在电源电路组件之间分布成簇。每个集群可以包含并联连接的多个单独的电容器单元。每个电容器单元可以包含与电容器串联的电容器和电阻器。电容器可以是金属 - 绝缘体 - 金属（MIM）电容器。由于电介质缺陷，每个电池中的电阻可能会限制在电容器短路的情况下单个电容器的电流。

6. 发明授权

US09425192B2 Integrated circuit decoupling capacitors 有权
标题翻译：集成电路去耦电容
公开(公告)号：US09425192B2
公开(公告)日：2016-08-23
申请号：US12332928
申请日：2008-12-11
申请人： Irfan Rahim , William Bradley Vest , Myron Wai Wong
发明人： Irfan Rahim , William Bradley Vest , Myron Wai Wong
IPC分类号： H01L29/00 , H01L27/08 , H01L23/522 , H01L23/528
CPC分类号： H01L27/0805 , H01L23/5223 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： Power supply decoupling capacitors are provided for integrated circuits. The decoupling capacitors may be distributed in clusters amongst powered circuit components. Each cluster may contain a number of individual capacitor cells that are connected in parallel. Each capacitor cell may contain a capacitor and a resistor connected in series with the capacitor. The capacitors may be metal-insulator-metal (MIM) capacitors. The resistor in each cell may limit the current through an individual capacitor in the event of a short in the capacitor due to a dielectric defect.
摘要翻译：为集成电路提供电源去耦电容。去耦电容器可以在电源电路组件之间分布成簇。每个集群可以包含并联连接的多个单独的电容器单元。每个电容器单元可以包含与电容器串联的电容器和电阻器。电容器可以是金属 - 绝缘体 - 金属（MIM）电容器。由于电介质缺陷，每个电池中的电阻可能会限制在电容器短路的情况下单个电容器的电流。

7. 发明授权

US08289755B1 Volatile memory elements with soft error upset immunity 有权
标题翻译：易失性记忆元件，具有柔软的错误不耐受性
公开(公告)号：US08289755B1
公开(公告)日：2012-10-16
申请号：US12571346
申请日：2009-09-30
申请人： Irfan Rahim , Jeffrey T. Watt , Andy L. Lee , Myron Wai Wong , William Bradley Vest
发明人： Irfan Rahim , Jeffrey T. Watt , Andy L. Lee , Myron Wai Wong , William Bradley Vest
IPC分类号： G11C11/00
CPC分类号： G11C11/4125
摘要： Memory elements are provided that exhibit immunity to soft error upsets. The memory elements may have cross-coupled inverters. The inverters may be implemented using programmable Schmitt triggers. The memory elements may be locked and unlocked by providing appropriate power supply voltages to the Schmitt trigger. The memory elements may each have four inverter-like transistor pairs that form a bistable element, at least one address transistor, and at least one write enable transistor. The write enable transistor may bridge two of the four nodes. The memory elements may be locked and unlocked by turning the write enable transistor on and off. When a memory element is unlocked, the memory element is less resistant to changes in state, thereby facilitating write operations. When the memory element is locked, the memory element may exhibit enhanced immunity to soft error upsets.
摘要翻译：提供了显示对软错误扰乱的抗扰度的内存元素。存储器元件可以具有交叉耦合的反相器。可以使用可编程施密特触发器来实现逆变器。存储器元件可以通过向施密特触发器提供适当的电源电压来锁定和解锁。存储元件可以各自具有形成双稳态元件，至少一个地址晶体管和至少一个写使能晶体管的四个逆变器状晶体管对。写使能晶体管可以桥接四个节点中的两个。存储元件可以通过打开和关闭写使能晶体管来锁定和解锁。当存储器元件被解锁时，存储元件对状态变化的抵抗力较小，从而便于写操作。当存储器元件被锁定时，存储元件可以表现出对软错误扰动的增强的抗扰性。

8. 发明授权

US07800400B2 Configuration random access memory 有权
标题翻译：配置随机存取存储器
公开(公告)号：US07800400B2
公开(公告)日：2010-09-21
申请号：US11653001
申请日：2007-01-12
申请人： Irfan Rahim , Andy L. Lee , Myron Wai Wong , William Bradley Vest , Jeffrey T. Watt
发明人： Irfan Rahim , Andy L. Lee , Myron Wai Wong , William Bradley Vest , Jeffrey T. Watt
IPC分类号： H03K19/173
CPC分类号： H03K19/1776 , G11C11/401 , G11C11/404 , G11C14/00 , H03K19/1778
摘要： Integrated circuits such as programmable logic device integrated circuits are provided that have configuration random-access memory elements. The configuration random-access memory elements are loaded with configuration data to customize programmable logic on the integrated circuits. Each memory element has a capacitor that stores data for that memory element. A pair of cross-coupled inverters are connected to the capacitor. The inverters ensure that the memory elements produce output control signals with voltages than range from one power supply rail to another. Each configuration random-access memory element may have a clear transistor. The capacitor may be formed in a dielectric layer that lies above the transistors of the inverters, the address transistor, and the clear transistor. The inverters may be powered with an elevated power supply voltage.
摘要翻译：提供了诸如可编程逻辑器件集成电路的集成电路，其具有配置随机存取存储器元件。配置随机存取存储器元件装载有配置数据以在集成电路上定制可编程逻辑。每个存储器元件具有存储该存储器元件的数据的电容器。一对交叉耦合的反相器连接到电容器。逆变器确保存储元件产生的输出控制信号的电压低于从一个电源轨到另一个电源的范围。每个配置随机存取存储器元件可以具有透明晶体管。电容器可以形成在位于反相器，地址晶体管和透明晶体管的晶体管之上的电介质层中。逆变器可以用升高的电源电压供电。

9. 发明授权

US08797790B1 Memory elements with soft error upset immunity 有权
标题翻译：内存元件具有软错误的不安定性
公开(公告)号：US08797790B1
公开(公告)日：2014-08-05
申请号：US12568638
申请日：2009-09-28
申请人： Irfan Rahim , Andy L. Lee , Jeffrey T. Watt , William Bradley Vest
发明人： Irfan Rahim , Andy L. Lee , Jeffrey T. Watt , William Bradley Vest
IPC分类号： G11C11/00 , G11C11/412 , G11C8/16
CPC分类号： G11C11/412 , G11C5/005 , G11C5/06 , G11C8/16 , G11C11/4125
摘要： Memory elements are provided that exhibit immunity to soft error upset events when subjected to radiation strikes such as high-energy atomic particle strikes. Each memory element may each have four inverter-like transistor pairs that form a bistable element, a pair of address transistors, and a pair of relatively weak transistors connected between two of the inverters that create a common output node which is resistant to rapid changes to its state. The transistors may be connected in a pattern that forms a bistable memory element that is resistant to soft error upset events due to radiation strikes. Data may be loaded into and read out of the memory element using the address transistor pair.
摘要翻译：提供了存储器元件，当受到诸如高能量原子粒子撞击的辐射攻击时，其表现出对软错误失调事件的抗扰性。每个存储元件可以各自具有形成双稳态元件，一对地址晶体管和连接在两个逆变器之间的一对相对较弱的晶体管的四个逆变器状晶体管对，其形成公共输出节点，其抵抗快速变化它的状态。晶体管可以以形成双稳态存储器元件的图案连接，该双稳态存储器元件由于辐射打击而抵抗软错误不正常事件。可以使用地址晶体管对将数据加载到存储器元件中并从存储器元件读出。

10. 发明授权

US08081502B1 Memory elements with body bias control 有权
标题翻译：记忆元素与身体偏差控制
公开(公告)号：US08081502B1
公开(公告)日：2011-12-20
申请号：US12345560
申请日：2008-12-29
申请人： Irfan Rahim , Jun Liu , Andy L. Lee , William Bradley Vest , Lu Zhou , Qi Xiang , Yanzhong Yu , Jeffrey Xiaoqi Tung , Albert Ratnakumar
发明人： Irfan Rahim , Jun Liu , Andy L. Lee , William Bradley Vest , Lu Zhou , Qi Xiang , Yanzhong Yu , Jeffrey Xiaoqi Tung , Albert Ratnakumar
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： An integrated circuit with memory elements is provided. The memory elements may have memory element transistors with body terminals. Body bias control circuitry may supply body bias voltages that strengthen or weaken memory element transistors to improve read and write margins. The body bias control circuitry may dynamically control body bias voltages so that time-varying body bias voltages are supplied to memory element transistors. Address transistors and latch transistors in the memory elements may be selectively strengthened and weakened. Process variations may be compensated by weakening fast transistors and strengthening slow transistors with body bias adjustments.
摘要翻译：提供了一种具有存储元件的集成电路。存储器元件可以具有带有主体端子的存储器元件晶体管。体偏置控制电路可以提供加强或削弱存储元件晶体管的体偏置电压，以改善读和写余量。体偏置控制电路可以动态地控制体偏置电压，从而将时变体偏置电压提供给存储元件晶体管。存储元件中的地址晶体管和锁存晶体管可以被选择性地加强和削弱。过程变化可以通过削弱快速晶体管和加强具有体偏置调整的慢晶体管来补偿。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式