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1. 发明授权

US5410171A Vertical type semiconductor with main current section and emulation current section 失效
标题翻译：具有主电流部分和仿真电流部分的垂直型半导体
公开(公告)号：US5410171A
公开(公告)日：1995-04-25
申请号：US038951
申请日：1993-03-29
申请人： Yasuaki Tsuzuki , Akira Kuroyanagi , Toshiaki Nishizawa
发明人： Yasuaki Tsuzuki , Akira Kuroyanagi , Toshiaki Nishizawa
IPC分类号： H01L21/336 , H01L21/76 , H01L27/02 , H01L27/04 , H01L29/06 , H01L29/10 , H01L29/78
CPC分类号： H01L29/7815 , H01L27/0248 , H01L29/0619 , H01L29/0696 , H01L29/1095
摘要： A power DMOS semiconductor device providing improved current detection accuracy can be produced using standard pocessess. The device includes main wells, subwells and a line well which is independent of the main wells and subwells. These wells are formed by doping the surface of a semiconductor substrate with well-forming impurities. The line well surrounds the subwells at a predetermined distance away from the subwells to relax an electric field on the surface of the substrate. Gate electrodes are patterned to form a line opening which surrounds the subwells. The line opening serves as a mask when forming the line well by doping the surface of the substrate with the well-forming impurities. Accordingly, the width of a region between the line well and an adjacent subwell will not fluctuate.
摘要翻译：提供提高电流检测精度的功率DMOS半导体器件可以使用标准的方式产生。该装置包括主井，下井和一条独立于主井和下井的线井。这些阱通过掺杂具有良好形成杂质的半导体衬底的表面而形成。线路井在距离底孔预定距离处围绕底孔，以松弛基底表面上的电场。图案化栅电极以形成围绕底孔的线路开口。线形开口用于通过用形成阱的杂质掺杂衬底的表面来形成线状物时用作掩模。因此，线槽与相邻的底座之间的区域的宽度不会波动。

2. 发明授权

US5534454A Method of producing a semiconductor device having accurate current detection 失效
标题翻译：制造具有精确电流检测的半导体器件的方法
公开(公告)号：US5534454A
公开(公告)日：1996-07-09
申请号：US385553
申请日：1995-02-08
申请人： Yasuaki Tsuzuki , Akira Kuroyanagi , Toshiaki Nishizawa
发明人： Yasuaki Tsuzuki , Akira Kuroyanagi , Toshiaki Nishizawa
IPC分类号： H01L21/336 , H01L21/76 , H01L27/02 , H01L27/04 , H01L29/06 , H01L29/10 , H01L29/78 , H01L21/265 , H01L21/70 , H01L27/00
CPC分类号： H01L29/7815 , H01L27/0248 , H01L29/0619 , H01L29/0696 , H01L29/1095
摘要： A power DMOS semiconductor device is producible with standard processes and provides improved current detecting accuracy. The device involves main wells (41), subwells (42), and a line well (43), which is independent of the main wells and subwells. These wells are formed by doping the surface of a semiconductor substrate (1) with well forming impurities. The line well surrounds the subwells with a predetermined distance away from the subwells, to relax an electric field on the surface of the substrate. Gate electrodes (71, 72) are patterned to form a line opening (10), which surrounds the subwells. The line opening serves as a mask when forming the line well by doping the surface of the substrate with the well forming impurities. Accordingly, the width of a region between the line well and an adjacent subwell will not fluctuate.
摘要翻译：功率DMOS半导体器件可通过标准工艺生产，并提供改进的电流检测精度。该装置包括主井（41），底孔（42）和一条管井（43），其独立于主井和下井。这些阱通过掺杂具有良好形成杂质的半导体衬底（1）的表面而形成。线条井围绕底孔以预定的距离离开底孔，以松弛基底表面上的电场。栅电极（71,72）被图案化以形成围绕底孔的线路开口（10）。当通过用形成孔的杂质掺杂衬底的表面来形成线时，线路开口用作掩模。因此，线槽与相邻的底座之间的区域的宽度不会波动。

3. 发明授权

US5798550A Vertical type semiconductor device and gate structure 失效
标题翻译：垂直型半导体器件和栅极结构
公开(公告)号：US5798550A
公开(公告)日：1998-08-25
申请号：US469622
申请日：1995-06-06
申请人： Akira Kuroyanagi , Masami Yamaoka , Yoshifumi Okabe , Yasuaki Tsuzuki , Yutaka Tomatsu
发明人： Akira Kuroyanagi , Masami Yamaoka , Yoshifumi Okabe , Yasuaki Tsuzuki , Yutaka Tomatsu
IPC分类号： H01L21/336 , H01L29/423 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L29/66719 , H01L29/402 , H01L29/42368 , H01L29/66712 , H01L29/7811 , H01L29/0615 , H01L29/0638 , H01L29/1095
摘要： The present invention involves a vertical type semiconductor device whereby miniaturization and lowered ON resistance of a cell within the device can be achieved without impairing the functioning of the device. The line width of the gate electrode is made smaller to meeting the demand for miniaturization of the cell while the distance between the channel regions which are diffused into the portions below the gate during double diffusion remains virtually equal to that in the device of larger cell size having a low J.sub.FET resistance component. While the width of the gate electrode is set to be smaller, the mask members used during double diffusion are attached to the side walls of the gate electrode, where their width allows the source region to diffuse to the portion under the gate. Accordingly, miniaturization and lowered ON resistance of the cell can be achieved without impairing the functioning of the device.
摘要翻译：本发明涉及垂直型半导体器件，由此可以实现器件内的电池的小型化和降低的导通电阻，而不会损害器件的功能。使栅电极的线宽变小以满足电池小型化的需要，而在双扩散期间扩散到栅极下方的沟道区域之间的距离实际上等于在较大单元尺寸的器件中的沟道区域之间的距离具有低JFET电阻分量。虽然栅电极的宽度设定得较小，但是在双扩散期间使用的掩模构件附接到栅电极的侧壁，其宽度允许源极区域扩散到栅极下方的部分。因此，可以实现电池的小型化和降低的导通电阻，而不会损害器件的功能。

4. 发明授权

US5550067A Method for producing semiconductor device having DMOS and NMOS elements formed in the same substrate 失效
标题翻译：用于制造具有形成在同一衬底中的DMOS和NMOS元件的半导体器件的方法
公开(公告)号：US5550067A
公开(公告)日：1996-08-27
申请号：US38953
申请日：1993-03-29
申请人： Akira Kuroyanagi , Yutaka Tomatsu , Yasuaki Tsuzuki
发明人： Akira Kuroyanagi , Yutaka Tomatsu , Yasuaki Tsuzuki
IPC分类号： H01L27/088 , H01L21/8234 , H01L21/8236 , H01L29/06 , H01L29/78 , H01L21/265
CPC分类号： H01L29/66712 , H01L21/823456 , H01L29/7803 , H01L29/7811 , H01L29/1095 , H01L29/402
摘要： An intelligent power element has integrated DMOS transistors and control elements such as NMOS transistors. Impurity concentration inside a channel well (4) of each DMOS transistor is denser than that at the surface thereof. This results in reducing the reach-through withstand voltage of the DMOS transistor to less than that of the NMOS transistor. As a result, a reach-through phenomenon occurs on the DMOS transistor having a higher allowable (withstand) current before it occurs on the NMOS transistor having a lower allowable current. To provide the same effect, the reach-through withstand voltage of the DMOS transistor may be decreased by forming an internal high concentration well (201) at an upper part of a deep main well (31) of the DMOS transistor. The well (201) is shallower than the main well (31) and does not extend under a gate electrode (71).
摘要翻译：智能功率元件集成了DMOS晶体管和诸如NMOS晶体管的控制元件。每个DMOS晶体管的通道阱（4）内的杂质浓度比其表面处的浓度更致密。这导致将DMOS晶体管的可达耐受电压降低到小于NMOS晶体管的耐受电压。结果，在具有较低可允许电流的NMOS晶体管上发生之前，在具有较高允许（耐受）电流的DMOS晶体管上会发生到达现象现象。为了提供相同的效果，可以通过在DMOS晶体管的深主阱（31）的上部形成内部高浓度阱（201）来降低DMOS晶体管的到达耐受电压。井（201）比主井（31）浅，并且不在栅电极（71）下延伸。

5. 发明授权

US5453390A Method of producing semiconductor device with current detecting function 失效
标题翻译：具有电流检测功能的半导体器件的制造方法
公开(公告)号：US5453390A
公开(公告)日：1995-09-26
申请号：US38958
申请日：1993-03-29
申请人： Toshiaki Nishizawa , Akira Kuroyanagi , Tsuyoshi Yamamoto , Norihito Tokura
发明人： Toshiaki Nishizawa , Akira Kuroyanagi , Tsuyoshi Yamamoto , Norihito Tokura
IPC分类号： H01L29/78 , H01L21/336 , H01L27/02 , H01L27/04 , H01L21/266
CPC分类号： H01L29/66712 , H01L27/0248 , H01L29/7811 , H01L29/7815 , Y10S148/126
摘要： A power semiconductor device having current detecting function comprising a detection pert that includes the elements of a better reach-through withstand voltage capability than those of a principal current part. The power semiconductor device comprises such elements as DMOS, IGBT or BPT cells. One area of the device acts as the detection part and another as the principal current part. The detection part and the principal current part share as their common electrode a high density substrate having a low density layer of a first conductivity type. The surface of the low density layer carries a principal and a subordinate well region of a second conductivity type each. The surface of the principal well region bears a surface electrode region of the first conductivity type acting as the other electrode of the principal current part; the surface of the subordinate well region carries a surface electrode region of the first conductivity type acting as the other electrode of the detection part. The subordinate well region is made shallower than the principal well region illustratively by use of a mask having narrower apertures through which to form the former region. This causes a reach-through to occur in the principal current part with its well region having a shorter distance to the high density substrate, and not in the detection part with its well region having a longer distance to the substrate.
摘要翻译：一种具有电流检测功能的功率半导体器件，包括具有比主要电流部分更好的达到耐受电压能力的元件的检测灵敏度。功率半导体器件包括诸如DMOS，IGBT或BPT单元的元件。设备的一个区域作为检测部分，另一个作为主要的当前部分。检测部分和主要电流部分共同作为其公共电极具有第一导电类型的低密度层的高密度基板。低密度层的表面分别载有第二导电类型的主要和次要的阱区。主阱区域的表面具有作为主电流部分的另一个电极的第一导电类型的表面电极区域; 下位阱区域的表面带有用作检测部分的另一电极的第一导电类型的表面电极区域。通过使用具有较窄孔径的掩模来形成下一个井区域使其比主井区域浅，以形成前区域。这导致在主电流部分中出现通孔，其阱区具有与高密度衬底相距较短的距离，而不在其阱区具有与衬底相距较远的检测部分中。

6. 发明授权

US5654560A Semiconductor device with current detecting function and method of producing the same 失效
标题翻译：具有电流检测功能的半导体器件及其制造方法
公开(公告)号：US5654560A
公开(公告)日：1997-08-05
申请号：US475096
申请日：1995-06-07
申请人： Toshiaki Nishizawa , Akira Kuroyanagi , Tsuyoshi Yamamoto , Norihito Tokura
发明人： Toshiaki Nishizawa , Akira Kuroyanagi , Tsuyoshi Yamamoto , Norihito Tokura
IPC分类号： H01L29/78 , H01L21/336 , H01L27/02 , H01L27/04 , H01L29/74
CPC分类号： H01L29/66712 , H01L27/0248 , H01L29/7811 , H01L29/7815 , Y10S148/126
摘要： A power semiconductor device having a current detecting function comprising a detection part that includes the elements of a better reach-through withstand voltage capability than those of a principal current part. The power semiconductor device comprises such elements as DMOS, IGBT or BPT cells. One area of the device acts as the detection part and another as the principal current part. The detection part and the principal current part share as their common electrode a high density substrate having a low density layer of a first conductivity type. The surface of the low density layer carries a principal and a subordinate well region of a second conductivity type each. The surface of the principal well region bears a surface electrode region of the first conductivity type acting as the other electrode of the principal current part; the surface of the subordinate well region carries a surface electrode region of the first conductivity type acting as the other electrode of the detection part. The subordinate well region is made shallower than the principal well region illustratively by use of a mask having narrower apertures through which to form the former region. This causes a reach-through to occur in the principal current part with its well region having a shorter distance to the high density substrate, and not in the detection part with its well region having a longer distance to the substrate.
摘要翻译：一种具有电流检测功能的功率半导体器件，包括检测部件，该检测部件包括比主电流部件更好的达到耐受电压能力的元件。功率半导体器件包括诸如DMOS，IGBT或BPT单元的元件。设备的一个区域作为检测部分，另一个作为主要的当前部分。检测部分和主要电流部分共同作为其公共电极具有第一导电类型的低密度层的高密度基板。低密度层的表面分别载有第二导电类型的主要和次要的阱区。主阱区域的表面具有作为主电流部分的另一个电极的第一导电类型的表面电极区域; 下位阱区域的表面带有用作检测部分的另一电极的第一导电类型的表面电极区域。通过使用具有较窄孔径的掩模来形成下一个井区域使其比主井区域浅，以形成前区域。这导致在主电流部分中出现通孔，其阱区具有与高密度衬底相距较短的距离，而不在其阱区具有与衬底相距较远的检测部分中。

7. 发明授权

US07586151B2 Insulated gate semiconductor device 有权
标题翻译：绝缘栅半导体器件
公开(公告)号：US07586151B2
公开(公告)日：2009-09-08
申请号：US11578949
申请日：2005-05-11
申请人： Hidefumi Takaya , Yasushi Okura , Akira Kuroyanagi , Norihito Tokura
发明人： Hidefumi Takaya , Yasushi Okura , Akira Kuroyanagi , Norihito Tokura
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0623 , H01L29/0653 , H01L29/42368 , H01L29/4238 , H01L29/7811
摘要： The present invention provides an insulated gate semiconductor device which has floating regions around the bottoms of trenches and which is capable of reliably achieving a high withstand voltage. An insulated gate semiconductor device 100 includes a cell area through which current flows and an terminal area which surrounds the cell area. The semiconductor device 100 also has a plurality of gate trenches 21 in the cell area and a plurality of terminal trenches 62 in the terminal area. The gate trenches 21 are formed in a striped shape, and the terminal trenches 62 are formed concentrically. In the semiconductor device 100, the gate trenches 21 and the terminal trenches 62 are positioned in a manner that spacings between the ends of the gate trenches 21 and the side of the terminal trench 62 are uniform. That is, the length of the gate trenches 21 is adjusted according to the curvature of the corners of the terminal trench 62.
摘要翻译：本发明提供了一种绝缘栅半导体器件，其在沟槽底部附近具有浮动区域，并且能够可靠地实现高耐压。绝缘栅半导体器件100包括电流流过的单元区域和围绕单元区域的端子区域。半导体器件100还在单元区域中具有多个栅极沟槽21以及端子区域中的多个端子沟槽62。栅极沟槽21形成为条状，并且端子沟槽62同心地形成。在半导体器件100中，栅极沟槽21和端子沟槽62以栅极沟槽21的端部和端子沟槽62的侧面之间的间隔均匀的方式定位。也就是说，栅极沟槽21的长度根据端子沟槽62的拐角的曲率来调节。

8. 发明申请

US20050202117A1 Method of manufacturing resin molding and change-over device for changing over between heating medium and resin material in process of secondary forming 失效
标题翻译：在二次成型过程中制造树脂成型方法和切换装置，用于在加热介质和树脂材料之间切换
公开(公告)号：US20050202117A1
公开(公告)日：2005-09-15
申请号：US11079260
申请日：2005-03-14
申请人： Hidehisa Nasu , Akira Kuroyanagi , Masato Ichikawa , Akira Sahashi
发明人： Hidehisa Nasu , Akira Kuroyanagi , Masato Ichikawa , Akira Sahashi
IPC分类号： B29C45/26 , B29C45/00 , B29C45/14 , B29C45/72 , B29C65/70 , B29L23/00
CPC分类号： B29C45/0062 , B29C45/7207 , B29C65/103 , B29C65/42 , B29C65/542 , B29C66/0242 , B29C66/1312 , B29C66/547 , B29C2045/14877
摘要： The device includes: a runner block arranged at a position close to the injection port for resin material for secondary forming; and a slide core moved relatively with the runner block. In the runner block, a guide passage is formed which is communicated with a passage formed when pipe-shaped passages of the primary moldings are butted against each other. A heating medium passage or a resin material passage formed in the slide core are moved so that either the heating medium passage or the resin material passage can be selectively communicated with the guide passage formed in the runner block.
摘要翻译：该装置包括：设置在靠近用于二次成型的树脂材料的注入口的位置处的流道块; 并且滑块与滑块相对移动。在流道块中，形成一个引导通道，该引导通道与一次模制品的管状通道彼此对接时形成的通道连通。移动形成在滑动芯体中的加热介质通道或树脂材料通道，使得加热介质通道或树脂材料通道可以与形成在流道块中的引导通道选择性地连通。

9. 发明授权

US06864532B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06864532B2
公开(公告)日：2005-03-08
申请号：US10175294
申请日：2002-06-20
申请人： Takaaki Aoki , Akira Kuroyanagi , Mikimasa Suzuki , Takafumi Arakawa , Yukio Tsuzuki
发明人： Takaaki Aoki , Akira Kuroyanagi , Mikimasa Suzuki , Takafumi Arakawa , Yukio Tsuzuki
IPC分类号： H01L21/28 , H01L21/331 , H01L21/336 , H01L29/423 , H01L29/51 , H01L29/739 , H01L29/78 , H01L29/788
CPC分类号： H01L29/7813 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L29/42368 , H01L29/511 , H01L29/513 , H01L29/518 , H01L29/66348 , H01L29/7397
摘要： A trench-gate type transistor has a gate insulating film formed on an inner wall of a trench. The gate insulating film includes a first portion located on a wall of the trench and a second portion located on upper and bottom portions of the trench. The first portion includes a first oxide film, a nitride film, and a second oxide film. The second portion includes only an oxide film and is thicker than the first portion. Accordingly, electric field concentration on upper and lower corner portions of the trench can be reduced to improve the withstand voltage. In addition, and end of the trench may have an insulation layer that is thicker than the first portion.
摘要翻译：沟槽栅型晶体管具有形成在沟槽的内壁上的栅极绝缘膜。栅极绝缘膜包括位于沟槽的壁上的第一部分和位于沟槽的上部和底部的第二部分。第一部分包括第一氧化膜，氮化物膜和第二氧化物膜。第二部分仅包括氧化膜并且比第一部分厚。因此，可以减小沟槽的上下角部的电场集中以提高耐压。此外，沟槽的端部可以具有比第一部分更厚的绝缘层。

10. 发明授权

US06373093B1 Semiconductor memory device and method of manufacturing the same 有权
公开(公告)号：US06373093B1
公开(公告)日：2002-04-16
申请号：US09776769
申请日：2001-02-06
申请人： Tetsuo Fujii , Minekazu Sakai , Akira Kuroyanagi
发明人： Tetsuo Fujii , Minekazu Sakai , Akira Kuroyanagi
IPC分类号： H01L2976
摘要： A gate oxide film is formed on a surface of a semiconductor substrate. A tunnel insulating film having a thickness smaller than that of the gate insulating film is formed in a portion thereof corresponding to a tunnel region. A first silicon film having a low impurity concentration is formed on the gate insulating film. A second silicon film having an impurity concentration higher than that of the first silicon film is formed on the first silicon film so as to be connected thereto. A third silicon film is formed on the second silicon film through an insulating film. The second and third silicon films are formed into floating and control gates, respectively, thereby forming a semiconductor memory device.

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