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1. 发明授权

US06864532B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06864532B2
公开(公告)日：2005-03-08
申请号：US10175294
申请日：2002-06-20
申请人： Takaaki Aoki , Akira Kuroyanagi , Mikimasa Suzuki , Takafumi Arakawa , Yukio Tsuzuki
发明人： Takaaki Aoki , Akira Kuroyanagi , Mikimasa Suzuki , Takafumi Arakawa , Yukio Tsuzuki
IPC分类号： H01L21/28 , H01L21/331 , H01L21/336 , H01L29/423 , H01L29/51 , H01L29/739 , H01L29/78 , H01L29/788
CPC分类号： H01L29/7813 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L29/42368 , H01L29/511 , H01L29/513 , H01L29/518 , H01L29/66348 , H01L29/7397
摘要： A trench-gate type transistor has a gate insulating film formed on an inner wall of a trench. The gate insulating film includes a first portion located on a wall of the trench and a second portion located on upper and bottom portions of the trench. The first portion includes a first oxide film, a nitride film, and a second oxide film. The second portion includes only an oxide film and is thicker than the first portion. Accordingly, electric field concentration on upper and lower corner portions of the trench can be reduced to improve the withstand voltage. In addition, and end of the trench may have an insulation layer that is thicker than the first portion.
摘要翻译：沟槽栅型晶体管具有形成在沟槽的内壁上的栅极绝缘膜。栅极绝缘膜包括位于沟槽的壁上的第一部分和位于沟槽的上部和底部的第二部分。第一部分包括第一氧化膜，氮化物膜和第二氧化物膜。第二部分仅包括氧化膜并且比第一部分厚。因此，可以减小沟槽的上下角部的电场集中以提高耐压。此外，沟槽的端部可以具有比第一部分更厚的绝缘层。

2. 发明申请

US20050090060A1 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20050090060A1
公开(公告)日：2005-04-28
申请号：US10974838
申请日：2004-10-28
申请人： Takaaki Aoki , Yutaka Tomatsu , Akira Kuroyanagi , Mikimasa Suzuki , Hajime Soga , Takafumi Arakawa , Yukio Tsuzuki
发明人： Takaaki Aoki , Yutaka Tomatsu , Akira Kuroyanagi , Mikimasa Suzuki , Hajime Soga , Takafumi Arakawa , Yukio Tsuzuki
IPC分类号： H01L21/28 , H01L21/331 , H01L21/336 , H01L29/423 , H01L29/51 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7813 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L29/42368 , H01L29/511 , H01L29/513 , H01L29/518 , H01L29/66348 , H01L29/7397
摘要： A trench-gate type transistor has a gate insulating film formed on an inner wall of a trench. The gate insulating film includes a first portion located on a wall of the trench and a second portion located on upper and bottom portions of the trench. The first portion includes a first oxide film, a nitride film, and a second oxide film. The second portion includes only an oxide film and is thicker than the first portion. Accordingly, electric field concentration on upper and lower corner portions of the trench can be reduced to improve the withstand voltage. In addition, and end of the trench may have an insulation layer that is thicker than the first portion.
摘要翻译：沟槽栅型晶体管具有形成在沟槽的内壁上的栅极绝缘膜。栅极绝缘膜包括位于沟槽的壁上的第一部分和位于沟槽的上部和底部的第二部分。第一部分包括第一氧化膜，氮化物膜和第二氧化物膜。第二部分仅包括氧化膜并且比第一部分厚。因此，可以减小沟槽的上下角部的电场集中以提高耐压。此外，沟槽的端部可以具有比第一部分更厚的绝缘层。

3. 发明授权

US07622768B2 Semiconductor device and method of manufacturing thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07622768B2
公开(公告)日：2009-11-24
申请号：US11110826
申请日：2005-04-21
申请人： Takaaki Aoki , Mikimasa Suzuki , Yukio Tsuzuki , Tomofusa Shiga
发明人： Takaaki Aoki , Mikimasa Suzuki , Yukio Tsuzuki , Tomofusa Shiga
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/42368 , H01L29/511 , H01L29/66348 , H01L29/7397
摘要： On the surface of a silicon nitride film, there is formed a thermal oxide film, over which a CVD oxide film is then formed to provide a silicon oxide film of two-layered structure films. Moreover, the total thickness of the two-layered structure films is set to a value from 5 nm to 30 nm. Thus, the silicon oxide film is made into the two-layered structure films of the thermal oxide film and the CVD oxide film to thereby achieve the thickness of the silicon oxide film. As a result, it is possible to prevent a Vth from being lowered by a charge trap phenomenon and to prevent the Vth from fluctuating due to the enlargement of the bird's beak length by the silicon oxide film.
摘要翻译：在氮化硅膜的表面上形成热氧化膜，然后在其上形成CVD氧化膜，以提供两层结构膜的氧化硅膜。此外，将两层结构膜的总厚度设定为5nm〜30nm的值。因此，将氧化硅膜制成热氧化膜和CVD氧化物膜的两层结构膜，从而实现氧化硅膜的厚度。结果，可以通过电荷陷阱现象防止Vth降低，并且防止由于氧化硅膜的鸟喙长度的增大而导致的Vth波动。

4. 发明申请

US20050236664A1 Semiconductor device and method of manufacturing thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050236664A1
公开(公告)日：2005-10-27
申请号：US11110826
申请日：2005-04-21
申请人： Takaaki Aoki , Mikimasa Suzuki , Yukio Tsuzuki , Tomofusa Shiga
发明人： Takaaki Aoki , Mikimasa Suzuki , Yukio Tsuzuki , Tomofusa Shiga
IPC分类号： H01L29/78 , H01L21/331 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/51 , H01L29/739
CPC分类号： H01L29/7813 , H01L29/42368 , H01L29/511 , H01L29/66348 , H01L29/7397
摘要： On the surface of a silicon nitride film, there is formed a thermal oxide film, over which a CVD oxide film is then formed to provide a silicon oxide film of two-layered structure films. Moreover, the total thickness of the two-layered structure films is set to a value from 5 nm to 30 nm. Thus, the silicon oxide film is made into the two-layered structure films of the thermal oxide film and the CVD oxide film to thereby achieve the thickness of the silicon oxide film. As a result, it is possible to prevent a Vth from being lowered by a charge trap phenomenon and to prevent the Vth from fluctuating due to the enlargement of the bird's beak length by the silicon oxide film.
摘要翻译：在氮化硅膜的表面上形成热氧化膜，然后在其上形成CVD氧化膜，以提供两层结构膜的氧化硅膜。此外，将两层结构膜的总厚度设定为5nm〜30nm的值。因此，将氧化硅膜制成热氧化膜和CVD氧化物膜的两层结构膜，从而实现氧化硅膜的厚度。结果，可以通过电荷陷阱现象防止Vth降低，并且防止由于氧化硅膜的鸟喙长度的增大而导致的Vth波动。

5. 发明授权

US07126187B2 Semiconductor device and a method of producing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07126187B2
公开(公告)日：2006-10-24
申请号：US10635490
申请日：2003-08-07
申请人： Takaaki Aoki , Yukio Tsuzuki
发明人： Takaaki Aoki , Yukio Tsuzuki
IPC分类号： H01L29/76
CPC分类号： H01L29/7811 , H01L21/28194 , H01L21/28202 , H01L29/045 , H01L29/0696 , H01L29/1095 , H01L29/4238 , H01L29/513 , H01L29/518 , H01L29/7397 , H01L29/7813
摘要： A semiconductor device includes a semiconductor substrate, a cell region in a surface portion of the substrate for operating as a transistor, a gate lead wiring region having a gate lead pattern on the substrate, a trench in the surface portion of the substrate extending from the cell region to the gate lead wiring region, an oxide film on an inner surface of the trench, and a gate electrode in the trench insulated with at least the oxide film from the substrate. A speed of formation of a main portion of the sidewalls of the trench at the gate lead wiring region is greater than that of a main portion of the sidewalls of the trench at the cell region, so that a thickness of the oxide film at the gate lead wiring region is greater than that at the cell region.
摘要翻译：半导体器件包括半导体衬底，用于作为晶体管操作的衬底的表面部分中的单元区域，在衬底上具有栅极引线图案的栅极引线布线区域，从衬底的表面部分延伸的沟槽沟槽的内表面上的氧化膜，以及沟槽中的栅电极，至少与衬底的氧化膜绝缘。在栅极引线布线区域处沟槽的侧壁的主要部分的形成速度大于在单元区域处的沟槽的侧壁的主要部分的速度，使得栅极处的氧化物膜的厚度引线布线区域大于单元区域。

6. 发明申请

US20060128100A1 Semiconductor device and a method of producing the same 有权
公开(公告)号：US20060128100A1
公开(公告)日：2006-06-15
申请号：US11345310
申请日：2006-02-02
申请人： Takaaki Aoki , Yukio Tsuzuki
发明人： Takaaki Aoki , Yukio Tsuzuki
IPC分类号： H01L21/336
CPC分类号： H01L29/7811 , H01L21/28194 , H01L21/28202 , H01L29/045 , H01L29/0696 , H01L29/1095 , H01L29/4238 , H01L29/513 , H01L29/518 , H01L29/7397 , H01L29/7813
摘要： A semiconductor device includes a semiconductor substrate, a cell region in a surface portion of the substrate for operating as a transistor, a gate lead wiring region having a gate lead pattern on the substrate, a trench in the surface portion of the substrate extending from the cell region to the gate lead wiring region, an oxide film on an inner surface of the trench, and a gate electrode in the trench insulated with at least the oxide film from the substrate. A speed of formation of a main portion of the sidewalls of the trench at the gate lead wiring region is greater than that of a main portion of the sidewalls of the trench at the cell region, so that a thickness of the oxide film at the gate lead wiring region is greater than that at the cell region.

7. 发明申请

US20050161735A1 Method of producing a semiconductor device 有权
标题翻译：半导体装置的制造方法
公开(公告)号：US20050161735A1
公开(公告)日：2005-07-28
申请号：US11087758
申请日：2005-03-24
申请人： Takaaki Aoki , Yukio Tsuzuki
发明人： Takaaki Aoki , Yukio Tsuzuki
IPC分类号： H01L29/78 , H01L21/28 , H01L29/06 , H01L29/12 , H01L29/51 , H01L29/739 , H01L29/76 , H01L21/336
CPC分类号： H01L29/7811 , H01L21/28194 , H01L21/28202 , H01L29/045 , H01L29/0696 , H01L29/1095 , H01L29/4238 , H01L29/513 , H01L29/518 , H01L29/7397 , H01L29/7813
摘要： A semiconductor device includes a semiconductor substrate, a cell region in a surface portion of the substrate for operating as a transistor, a gate lead wiring region having a gate lead pattern on the substrate, a trench in the surface portion of the substrate extending from the cell region to the gate lead wiring region, an oxide film on an inner surface of the trench, and a gate electrode in the trench insulated with at least the oxide film from the substrate. A speed of formation of a main portion of the sidewalls of the trench at the gate lead wiring region is greater than that of a main portion of the sidewalls of the trench at the cell region, so that a thickness of the oxide film at the gate lead wiring region is greater than that at the cell region.
摘要翻译：半导体器件包括半导体衬底，用于作为晶体管操作的衬底的表面部分中的单元区域，在衬底上具有栅极引线图案的栅极引线布线区域，从衬底的表面部分延伸的沟槽沟槽的内表面上的氧化膜，以及沟槽中的栅电极，至少与衬底的氧化膜绝缘。在栅极引线布线区域处沟槽的侧壁的主要部分的形成速度大于在单元区域处的沟槽的侧壁的主要部分的速度，使得栅极处的氧化物膜的厚度引线布线区域大于单元区域。

8. 发明授权

US07348244B2 Method of producing a semiconductor device 有权
标题翻译：半导体装置的制造方法
公开(公告)号：US07348244B2
公开(公告)日：2008-03-25
申请号：US11345310
申请日：2006-02-02
申请人： Takaaki Aoki , Yukio Tsuzuki
发明人： Takaaki Aoki , Yukio Tsuzuki
IPC分类号： H01L21/336
CPC分类号： H01L29/7811 , H01L21/28194 , H01L21/28202 , H01L29/045 , H01L29/0696 , H01L29/1095 , H01L29/4238 , H01L29/513 , H01L29/518 , H01L29/7397 , H01L29/7813
摘要： A semiconductor device includes a semiconductor substrate, a cell region in a surface portion of the substrate for operating as a transistor, a gate lead wiring region having a gate lead pattern on the substrate, a trench in the surface portion of the substrate extending from the cell region to the gate lead wiring region, an oxide film on an inner surface of the trench, and a gate electrode in the trench insulated with at least the oxide film from the substrate. A speed of formation of a main portion of the sidewalls of the trench at the gate lead wiring region is greater than that of a main portion of the sidewalls of the trench at the cell region, so that a thickness of the oxide film at the gate lead wiring region is greater than that at the cell region.
摘要翻译：半导体器件包括半导体衬底，用于作为晶体管操作的衬底的表面部分中的单元区域，在衬底上具有栅极引线图案的栅极引线布线区域，从衬底的表面部分延伸的沟槽沟槽的内表面上的氧化膜，以及沟槽中的栅电极，至少与衬底的氧化膜绝缘。在栅极引线布线区域处沟槽的侧壁的主要部分的形成速度大于在单元区域处的沟槽的侧壁的主要部分的速度，使得栅极处的氧化物膜的厚度引线布线区域大于单元区域。

9. 发明授权

US07026215B2 Method of producing a semiconductor device 有权
标题翻译：半导体装置的制造方法
公开(公告)号：US07026215B2
公开(公告)日：2006-04-11
申请号：US11087758
申请日：2005-03-24
申请人： Takaaki Aoki , Yukio Tsuzuki
发明人： Takaaki Aoki , Yukio Tsuzuki
IPC分类号： H01L21/336
CPC分类号： H01L29/7811 , H01L21/28194 , H01L21/28202 , H01L29/045 , H01L29/0696 , H01L29/1095 , H01L29/4238 , H01L29/513 , H01L29/518 , H01L29/7397 , H01L29/7813
摘要： A semiconductor device includes a semiconductor substrate, a cell region in a surface portion of the substrate for operating as a transistor, a gate lead wiring region having a gate lead pattern on the substrate, a trench in the surface portion of the substrate extending from the cell region to the gate lead wiring region, an oxide film on an inner surface of the trench, and a gate electrode in the trench insulated with at least the oxide film from the substrate. A speed of formation of a main portion of the sidewalls of the trench at the gate lead wiring region is greater than that of a main portion of the sidewalls of the trench at the cell region, so that a thickness of the oxide film at the gate lead wiring region is greater than that at the cell region.
摘要翻译：半导体器件包括半导体衬底，用于作为晶体管操作的衬底的表面部分中的单元区域，在衬底上具有栅极引线图案的栅极引线布线区域，从衬底的表面部分延伸的沟槽沟槽的内表面上的氧化膜，以及沟槽中的栅电极，至少与衬底的氧化膜绝缘。在栅极引线布线区域处沟槽的侧壁的主要部分的形成速度大于在单元区域处的沟槽的侧壁的主要部分的速度，使得栅极处的氧化物膜的厚度引线布线区域大于单元区域。

10. 发明授权

US08102025B2 Semiconductor device having IGBT and diode 有权
标题翻译：具有IGBT和二极管的半导体器件
公开(公告)号：US08102025B2
公开(公告)日：2012-01-24
申请号：US11709272
申请日：2007-02-22
申请人： Yoshihiko Ozeki , Norihito Tokura , Yukio Tsuzuki
发明人： Yoshihiko Ozeki , Norihito Tokura , Yukio Tsuzuki
IPC分类号： H01L29/66
CPC分类号： H01L27/0611 , H01L29/7395 , H01L29/8611
摘要： A semiconductor device includes: a semiconductor substrate; a IGBT region including a first region on a first surface of the substrate and providing a channel-forming region and a second region on a second surface of the substrate and providing a collector; a diode region including a third region on the first surface and providing an anode or a cathode and a fourth region on the second surface and providing the anode or the cathode; a periphery region including a fifth region on the first surface and a sixth region on the second surface. The first, third and fifth regions are commonly and electrically coupled, and the second, fourth and sixth regions are commonly and electrically coupled with one another.
摘要翻译：半导体器件包括：半导体衬底; IGBT区域，包括在所述基板的第一表面上的第一区域，并且在所述基板的第二表面上提供沟道形成区域和第二区域，并提供集电体; 二极管区域，包括在第一表面上的第三区域，并在第二表面上提供阳极或阴极和第四区域，并提供阳极或阴极; 外围区域，包括在第一表面上的第五区域和第二表面上的第六区域。第一，第三和第五区域通常和电耦合，并且第二，第四和第六区域彼此通常电耦合。

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