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    • 3. 发明授权
    • Multiple gate transistor employing monocrystalline silicon walls
    • 采用单晶硅壁的多栅极晶体管
    • US06753216B2
    • 2004-06-22
    • US10285059
    • 2002-10-31
    • Leo MathewBich-Yen NguyenDaniel Thanh-Khac PhamAnne Vandooren
    • Leo MathewBich-Yen NguyenDaniel Thanh-Khac PhamAnne Vandooren
    • H01L218238
    • H01L29/785H01L29/42384H01L29/66795H01L29/78603H01L29/78621
    • A semiconductor fabrication process and structure in which a dielectric structure (106) is formed upon a substrate (102). Silicon is then deposited and processed to form a crystalline silicon wall (118) that envelopes the dielectric structure (106) and is physically and electrically isolated from the substrate (102). A gate dielectric film (130) is formed over at least two surfaces of the silicon wall (118) and a gate electrode film (132) is formed over the gate dielectric (130). The gate electrode film (132) is then patterned followed by conventional source/drain implant processing. Portions of the silicon wall (118) disposed on either side of the gate electrode (140) may then be contacted to form source/drain structures (150). In this manner, the portion of the silicon wall (118) covered by the gate electrode (140) comprises a transistor channel region having multiple surfaces controlled by gate electrode (140).
    • 一种在衬底(102)上形成电介质结构(106)的半导体制造工艺和结构。 然后沉积和处理硅以形成包封电介质结构(106)并与衬底(102)物理和电气隔离的晶体硅壁(118)。 在硅壁(118)的至少两个表面上形成栅极电介质膜(130),并且在栅极电介质(130)上形成栅电极膜(132)。 然后对栅极电极膜(132)进行构图,然后进行常规的源极/漏极注入处理。 设置在栅电极(140)的任一侧的硅壁(118)的部分然后可以接触以形成源极/漏极结构(150)。 以这种方式,由栅电极(140)覆盖的硅壁(118)的部分包括具有由栅电极(140)控制的多个表面的晶体管沟道区。
    • 5. 发明授权
    • Pseudo-inverter circuit on SeOI
    • SeOI上的伪逆变电路
    • US08654602B2
    • 2014-02-18
    • US13495632
    • 2012-06-13
    • Carlos MazureRichard FerrantBich-Yen Nguyen
    • Carlos MazureRichard FerrantBich-Yen Nguyen
    • G11C8/00
    • G11C8/08G11C11/4085G11C2211/4016
    • A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage.
    • 在绝缘体上半导体衬底上制成的电路。 该电路包括具有第一通道的第一晶体管,具有第二通道的第二晶体管,晶体管以第一和第二端子串联连接的方式提供,以施加电源电位,每个晶体管包括漏极区域和源极区域 在薄层中,在源极区域和漏极区域之间延伸的沟道以及位于沟道上方的前部控制栅极。 每个晶体管具有形成在晶体管的沟道下方的基底衬底中的背控制栅极,并且能够被偏置以便调制晶体管的阈值电压。 晶体管中的至少一个被配置为在充分调制其阈值电压的背栅信号的作用下以耗尽模式工作。
    • 6. 发明申请
    • PSEUDO-INVERTER CIRCUIT ON SeO1
    • PSO1上的PSEUDO-INVERTER电路
    • US20110242926A1
    • 2011-10-06
    • US12793553
    • 2010-06-03
    • Carlos MazureRichard FerrantBich-Yen Nguyen
    • Carlos MazureRichard FerrantBich-Yen Nguyen
    • G11C8/08G05F1/10
    • G11C8/08G11C11/4085G11C2211/4016
    • A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage.
    • 在绝缘体上半导体衬底上制成的电路。 该电路包括具有第一通道的第一晶体管,具有第二通道的第二晶体管,晶体管以第一和第二端子串联连接的方式提供,以施加电源电位,每个晶体管包括漏极区域和源极区域 在薄层中,在源极区域和漏极区域之间延伸的沟道以及位于沟道上方的前部控制栅极。 每个晶体管具有形成在晶体管的沟道下方的基底衬底中的背控制栅极,并且能够被偏置以便调制晶体管的阈值电压。 晶体管中的至少一个被配置为在充分调制其阈值电压的背栅信号的作用下以耗尽模式工作。
    • 7. 发明授权
    • Power MOSFET with a gate structure of different material
    • 功率MOSFET具有栅极结构不同的材料
    • US07943988B2
    • 2011-05-17
    • US12205438
    • 2008-09-05
    • Daniel PhamBich-Yen Nguyen
    • Daniel PhamBich-Yen Nguyen
    • H01L29/78
    • H01L29/7833H01L21/28105H01L29/42372
    • A semiconductor device includes a semiconductor layer of a first conductivity type and a first doping concentration. A first semiconductor region, used as drain, of the first conductivity type has a lower doping concentration than the semiconductor layer and is over the semiconductor layer. A gate dielectric is over the first semiconductor region. A gate electrode over the gate dielectric has a metal-containing center portion and first and second silicon portions on opposite sides of the center portion. A second semiconductor region, used as a channel, of the second conductivity type has a first portion under the first silicon portion and the gate dielectric. A third semiconductor region, used as a source, of the first conductivity type is laterally adjacent to the first portion of the second semiconductor region. The metal-containing center portion, replacing silicon, increases the source to drain breakdown voltage.
    • 半导体器件包括第一导电类型和第一掺杂浓度的半导体层。 用作第一导电类型的漏极的第一半导体区域具有比半导体层更低的掺杂浓度,并且在半导体层之上。 栅极电介质在第一半导体区域之上。 栅极电介质上的栅极电极在中心部分的相对侧上具有含金属的中心部分和第一和第二硅部分。 用作第二导电类型的沟道的第二半导体区域具有在第一硅部分下面的第一部分和栅极电介质。 用作第一导电类型的源的第三半导体区域与第二半导体区域的第一部分横向相邻。 置换硅的含金属中心部分将源极增加到漏极击穿电压。
    • 9. 发明授权
    • Electronic device including a semiconductor fin
    • 包括半导体鳍片的电子设备
    • US07800141B2
    • 2010-09-21
    • US12174357
    • 2008-07-16
    • Da ZhangBich-Yen Nguyen
    • Da ZhangBich-Yen Nguyen
    • H01L29/06
    • H01L29/785H01L29/4908H01L29/66507H01L29/66795H01L29/78684
    • An electronic device can include a semiconductor fin overlying an insulating layer. The electronic device can also include a semiconductor layer overlying the semiconductor fin. The semiconductor layer can have a first portion and a second portion that are spaced-apart from each other. In one aspect, the electronic device can include a conductive member that lies between and spaced-apart from the first and second portions of the semiconductor layer. The electronic device can also include a metal-semiconductor layer overlying the semiconductor layer. In another aspect, the semiconductor layer can abut the semiconductor fin and include a dopant. In a further aspect, a process of forming the electronic device can include reacting a metal-containing layer and a semiconductor layer to form a metal-semiconductor layer. In another aspect, a process can include forming a semiconductor layer, including a dopant, abutting a wall surface of a semiconductor fin.
    • 电子器件可以包括覆盖绝缘层的半导体鳍片。 电子器件还可以包括覆盖半导体鳍片的半导体层。 半导体层可以具有彼此间隔开的第一部分和第二部分。 在一个方面,电子设备可以包括位于半导体层的第一和第二部分之间并与之隔开的导电构件。 电子器件还可以包括覆盖半导体层的金属 - 半导体层。 在另一方面,半导体层可以邻接半导体鳍并包括掺杂剂。 在另一方面,形成电子器件的方法可以包括使含金属层和半导体层反应以形成金属 - 半导体层。 在另一方面,一种方法可以包括形成邻接半导体鳍片的壁表面的包括掺杂剂的半导体层。