专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06949455B2 Method for forming a semiconductor device structure a semiconductor layer 失效
标题翻译：半导体器件形成半导体层结构的方法
公开(公告)号：US06949455B2
公开(公告)日：2005-09-27
申请号：US10677070
申请日：2003-10-01
申请人： Daniel Thanh-Khac Pham , Bich-Yen Nguyen , James K. Schaeffer , Melissa O. Zavala , Sherry G. Straub , Kimberly G. Reid , Marc Rossow , James P. Geren
发明人： Daniel Thanh-Khac Pham , Bich-Yen Nguyen , James K. Schaeffer , Melissa O. Zavala , Sherry G. Straub , Kimberly G. Reid , Marc Rossow , James P. Geren
IPC分类号： H01L21/28 , H01L21/8238 , H01L29/49 , H01L29/51 , H01L21/3205
CPC分类号： H01L29/517 , H01L21/28061 , H01L21/823835 , H01L21/823842 , H01L21/823857 , H01L29/4933 , H01L29/51
摘要： A method for providing gates of transistors with at least two different work functions utilizes a silicidation of two different metals at different times, silicidation for one gate and polysilicon for the other, or silicidation using a single metal with two differently doped silicon structures. Thus the problem associated with performing silicidation of two different metals at the same time is avoided. If the two metals have significantly different silicidation temperatures, the one with the lower temperature silicidation will likely have significantly degraded performance as a result of having to also experience the higher temperature required to achieve silicidation with the other metal.
摘要翻译：用于提供具有至少两种不同功函数的晶体管栅极的方法利用两种不同金属在不同时间的硅化，一个栅极的硅化，另一个的硅化，或使用具有两个不同掺杂硅结构的单一金属的硅化。因此，避免了与同时进行两种不同金属的硅化相关的问题。如果两种金属具有明显不同的硅化物温度，则由于必须也经历用其它金属进行硅化所需的较高温度，具有较低温度硅化的温度可能会显着降低性能。

2. 发明授权

US06689676B1 Method for forming a semiconductor device structure in a semiconductor layer 有权
标题翻译：在半导体层中形成半导体器件结构的方法
公开(公告)号：US06689676B1
公开(公告)日：2004-02-10
申请号：US10206475
申请日：2002-07-26
申请人： Daniel Thanh-Khac Pham , Al T. Koh , Yeong-Jyh T. Lii , Robert F. Steimle , Anne Vandooren , Ricardo Garcia , Kimberly G. Reid , Marc Rossow , James P. Geren
发明人： Daniel Thanh-Khac Pham , Al T. Koh , Yeong-Jyh T. Lii , Robert F. Steimle , Anne Vandooren , Ricardo Garcia , Kimberly G. Reid , Marc Rossow , James P. Geren
IPC分类号： H01L213205
CPC分类号： H01L29/517 , H01L21/28061 , H01L21/823835 , H01L21/823842 , H01L21/823857 , H01L29/4933 , H01L29/51
摘要： A method for providing gates of transistors with at least two different work functions utilizes a silicidation of two different metals at different times, silicidation for one gate and polysilicon for the other, or silicidation using a single metal with two differently doped silicon structures. Thus the problem associated with performing silicidation of two different metals at the same time is avoided. If the two metals have significantly different silicidation temperatures, the one with the lower temperature silicidation will likely have significantly degraded performance as a result of having to also experience the higher temperature required to achieve silicidation with the other metal.
摘要翻译：用于提供具有至少两种不同功函数的晶体管栅极的方法利用两种不同金属在不同时间的硅化，一个栅极的硅化，另一个的硅化，或使用具有两个不同掺杂硅结构的单一金属的硅化。因此，避免了与同时进行两种不同金属的硅化相关的问题。如果两种金属具有明显不同的硅化物温度，则由于必须也经历用其它金属进行硅化所需的较高温度，具有较低温度硅化的温度可能会显着降低性能。

3. 发明授权

US06509609B1 Grooved channel schottky MOSFET 失效
标题翻译：沟槽肖特基MOSFET
公开(公告)号：US06509609B1
公开(公告)日：2003-01-21
申请号：US09884345
申请日：2001-06-18
申请人： Yaohui Zhang , Bich-Yen Nguyen , Kuntal Joardar , Daniel Thanh-Khac Pham
发明人： Yaohui Zhang , Bich-Yen Nguyen , Kuntal Joardar , Daniel Thanh-Khac Pham
IPC分类号： H01L2978
CPC分类号： H01L29/66643 , H01L21/823437 , H01L21/823828 , H01L29/6656 , H01L29/66621 , H01L29/7834 , H01L29/7839
摘要： A grooved channel Schottky contacted MOSFET has asymmetric source and drain regions. The MOSFET includes an undoped silicon substrate with a background doping concentration of less than about 1017 cm−3. A grooved channel is formed in a first surface of the substrate. A first metal silicide material is formed in a first side of the grooved channel, forming a source region, and a second metal silicide material is formed on a second side of the grooved channel, forming a drain region. A metal gate is formed in the grooved channel. The grooved structure allows the off-state current to be reduced to less than 50 pA/&mgr;m. Further, the feature size can be scaled down to 10 nm without strong short-channel effects (DIBL
摘要翻译：沟槽沟道肖特基接触MOSFET具有不对称的源极和漏极区域。 MOSFET包括背景掺杂浓度小于约1017cm-3的未掺杂硅衬底。在基板的第一表面中形成开槽通道。第一金属硅化物材料形成在带槽沟道的第一侧，形成源极区，并且第二金属硅化物材料形成在带槽沟道的第二侧上，形成漏区。在沟槽通道中形成金属门。带槽结构允许关断状态电流降低到小于50pA / mum。此外，特征尺寸可以缩小到10nm，而没有强的短信道效应（DIBL <0.063），并且门延迟（CV / I）降低到2.4ps。

4. 发明授权

US06753216B2 Multiple gate transistor employing monocrystalline silicon walls 有权
标题翻译：采用单晶硅壁的多栅极晶体管
公开(公告)号：US06753216B2
公开(公告)日：2004-06-22
申请号：US10285059
申请日：2002-10-31
申请人： Leo Mathew , Bich-Yen Nguyen , Daniel Thanh-Khac Pham , Anne Vandooren
发明人： Leo Mathew , Bich-Yen Nguyen , Daniel Thanh-Khac Pham , Anne Vandooren
IPC分类号： H01L218238
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66795 , H01L29/78603 , H01L29/78621
摘要： A semiconductor fabrication process and structure in which a dielectric structure (106) is formed upon a substrate (102). Silicon is then deposited and processed to form a crystalline silicon wall (118) that envelopes the dielectric structure (106) and is physically and electrically isolated from the substrate (102). A gate dielectric film (130) is formed over at least two surfaces of the silicon wall (118) and a gate electrode film (132) is formed over the gate dielectric (130). The gate electrode film (132) is then patterned followed by conventional source/drain implant processing. Portions of the silicon wall (118) disposed on either side of the gate electrode (140) may then be contacted to form source/drain structures (150). In this manner, the portion of the silicon wall (118) covered by the gate electrode (140) comprises a transistor channel region having multiple surfaces controlled by gate electrode (140).
摘要翻译：一种在衬底（102）上形成电介质结构（106）的半导体制造工艺和结构。然后沉积和处理硅以形成包封电介质结构（106）并与衬底（102）物理和电气隔离的晶体硅壁（118）。在硅壁（118）的至少两个表面上形成栅极电介质膜（130），并且在栅极电介质（130）上形成栅电极膜（132）。然后对栅极电极膜（132）进行构图，然后进行常规的源极/漏极注入处理。设置在栅电极（140）的任一侧的硅壁（118）的部分然后可以接触以形成源极/漏极结构（150）。以这种方式，由栅电极（140）覆盖的硅壁（118）的部分包括具有由栅电极（140）控制的多个表面的晶体管沟道区。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式