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1. 发明授权

US08809178B2 Methods of forming bulk FinFET devices with replacement gates so as to reduce punch through leakage currents 有权
标题翻译：用替换栅极形成大量FinFET器件的方法，以减少冲击穿过漏电流
公开(公告)号：US08809178B2
公开(公告)日：2014-08-19
申请号：US13408139
申请日：2012-02-29
申请人： Yanxiang Liu , Michael Hargrove , Xiaodong Yang , Hans van Meer , Laegu Kang , Christian Gruensfelder , Srikanth Samavedam
发明人： Yanxiang Liu , Michael Hargrove , Xiaodong Yang , Hans van Meer , Laegu Kang , Christian Gruensfelder , Srikanth Samavedam
IPC分类号： H01L21/4763
CPC分类号： H01L29/66545 , H01L29/66795
摘要： One illustrative method disclosed herein includes forming a plurality of spaced-apart trenches in a semiconducting substrate to thereby define a fin structure for the device, forming a local isolation region within each of the trenches, forming a sacrificial gate structure on the fin structure, wherein the sacrificial gate structure comprises at least a sacrificial gate electrode, and forming a layer of insulating material above the fin structure and within the trench above the local isolation region. In this example, the method further includes performing at least one etching process to remove the sacrificial gate structure to thereby define a gate cavity, after removing the sacrificial gate structure, performing at least one etching process to form a recess in the local isolation region, and forming a replacement gate structure that is positioned in the recess in the local isolation region and in the gate cavity.
摘要翻译：本文公开的一种说明性方法包括在半导体衬底中形成多个间隔开的沟槽，从而限定用于器件的鳍结构，在每个沟槽内形成局部隔离区，在翅片结构上形成牺牲栅极结构，其中所述牺牲栅极结构至少包括牺牲栅电极，以及在所述鳍结构之上和所述局部隔离区之上的沟槽内形成绝缘材料层。在该示例中，该方法还包括执行至少一个蚀刻工艺以去除牺牲栅极结构，从而在去除牺牲栅极结构之后，确定栅极腔，执行至少一个蚀刻工艺以在局部隔离区域中形成凹陷，以及形成位于局部隔离区域和门腔中的凹部中的替换栅极结构。

2. 发明申请

US20130224945A1 METHODS OF FORMING BULK FINFET DEVICES WITH REPLACEMENT GATES SO AS TO REDUCE PUNCH THROUGH LEAKAGE CURRENTS 有权
标题翻译：形成具有更换盖的块状FINFET器件的方法，以减少通过泄漏电流的冲击
公开(公告)号：US20130224945A1
公开(公告)日：2013-08-29
申请号：US13408139
申请日：2012-02-29
申请人： Yanxiang Liu , Michael Hargrove , Xiaodong Yang , Hans Van Meer , Laegu Kang , Christian Gruensfelder , Srikanth Samavedam
发明人： Yanxiang Liu , Michael Hargrove , Xiaodong Yang , Hans Van Meer , Laegu Kang , Christian Gruensfelder , Srikanth Samavedam
IPC分类号： H01L21/28
CPC分类号： H01L29/66545 , H01L29/66795
摘要： One illustrative method disclosed herein includes forming a plurality of spaced-apart trenches in a semiconducting substrate to thereby define a fin structure for the device, forming a local isolation region within each of the trenches, forming a sacrificial gate structure on the fin structure, wherein the sacrificial gate structure comprises at least a sacrificial gate electrode, and forming a layer of insulating material above the fin structure and within the trench above the local isolation region. In this example, the method further includes performing at least one etching process to remove the sacrificial gate structure to thereby define a gate cavity, after removing the sacrificial gate structure, performing at least one etching process to form a recess in the local isolation region, and forming a replacement gate structure that is positioned in the recess in the local isolation region and in the gate cavity.
摘要翻译：本文公开的一种说明性方法包括在半导体衬底中形成多个间隔开的沟槽，从而限定用于器件的鳍结构，在每个沟槽内形成局部隔离区，在翅片结构上形成牺牲栅极结构，其中所述牺牲栅极结构至少包括牺牲栅电极，以及在所述鳍结构之上和所述局部隔离区之上的沟槽内形成绝缘材料层。在该示例中，该方法还包括执行至少一个蚀刻工艺以去除牺牲栅极结构，从而在去除牺牲栅极结构之后，确定栅极腔，执行至少一个蚀刻工艺以在局部隔离区域中形成凹陷，以及形成位于局部隔离区域和门腔中的凹部中的替换栅极结构。

3. 发明授权

US09099525B2 Blanket EPI super steep retrograde well formation without Si recess 有权
标题翻译：毯子EPI超陡逆行井形成无Si凹陷
公开(公告)号：US09099525B2
公开(公告)日：2015-08-04
申请号：US13729207
申请日：2012-12-28
申请人： Laegu Kang , Vara Govindeswara Reddy Vakada , Michael P. Ganz , Yi Qi , Puneet Khanna , Sri Charan Vemula , Srikanth Samavedam
发明人： Laegu Kang , Vara Govindeswara Reddy Vakada , Michael P. Ganz , Yi Qi , Puneet Khanna , Sri Charan Vemula , Srikanth Samavedam
IPC分类号： H01L21/762 , H01L29/66 , H01L29/10 , H01L21/8238 , H01L29/165
CPC分类号： H01L29/0692 , H01L21/76224 , H01L21/823807 , H01L21/823878 , H01L21/823892 , H01L29/0649 , H01L29/1054 , H01L29/1095 , H01L29/165 , H01L29/167 , H01L29/66651
摘要： A method of forming SSRW FETs with controlled step height between a field oxide and epitaxially grown silicon and the resulting devices are provided. Embodiments include providing a SiN layer on a substrate, forming first, second, and third spaced STI regions of field oxide through the SiN layer and into the substrate, removing a top portion of the field oxide for each STI region by a controlled deglaze, removing the SiN layer, forming an n-type region in the substrate between the first and second STI regions and a p-type region in the substrate between the second and third STI regions, and epitaxially growing a Si based layer on the substrate over the n-type and p-type regions.
摘要翻译：提供了在场氧化物和外延生长的硅之间形成具有受控步长的SSRW FET的方法以及所得到的器件。实施例包括在衬底上提供SiN层，通过SiN层形成第一，第二和第三间隔的场区氧化物的STI区域并进入衬底，通过受控的消光去除每个STI区域的场氧化物的顶部部分，去除 SiN层，在第一和第二STI区域之间的衬底中形成n型区域和在第二和第三STI区域之间的衬底中的p型区域，并且在衬底上在n上外延生长Si基层型和p型区。

4. 发明申请

US20140183551A1 BLANKET EPI SUPER STEEP RETROGRADE WELL FORMATION WITHOUT Si RECESS 有权
公开(公告)号：US20140183551A1
公开(公告)日：2014-07-03
申请号：US13729207
申请日：2012-12-28
申请人： Laegu Kang , Vara Govindeswara Reddy Vakada , Michael P. Ganz , Yi Qi , Puneet Khanna , Sri Charan Vemula , Srikanth Samavedam
发明人： Laegu Kang , Vara Govindeswara Reddy Vakada , Michael P. Ganz , Yi Qi , Puneet Khanna , Sri Charan Vemula , Srikanth Samavedam
IPC分类号： H01L21/762 , H01L29/16
CPC分类号： H01L29/0692 , H01L21/76224 , H01L21/823807 , H01L21/823878 , H01L21/823892 , H01L29/0649 , H01L29/1054 , H01L29/1095 , H01L29/165 , H01L29/167 , H01L29/66651
摘要： A method of forming SSRW FETs with controlled step height between a field oxide and epitaxially grown silicon and the resulting devices are provided. Embodiments include providing a SiN layer on a substrate, forming first, second, and third spaced STI regions of field oxide through the SiN layer and into the substrate, removing a top portion of the field oxide for each STI region by a controlled deglaze, removing the SiN layer, forming an n-type region in the substrate between the first and second STI regions and a p-type region in the substrate between the second and third STI regions, and epitaxially growing a Si based layer on the substrate over the n-type and p-type regions.
摘要翻译：提供了在场氧化物和外延生长的硅之间形成具有受控步长的SSRW FET的方法以及所得到的器件。实施例包括在衬底上提供SiN层，通过SiN层形成第一，第二和第三间隔的场区氧化物的STI区域并进入衬底，通过受控的消光去除每个STI区域的场氧化物的顶部部分，去除 SiN层，在第一和第二STI区域之间的衬底中形成n型区域和在第二和第三STI区域之间的衬底中的p型区域，并且在衬底上在n上外延生长Si基层型和p型区。

5. 发明申请

US20140070358A1 METHOD OF TAILORING SILICON TRENCH PROFILE FOR SUPER STEEP RETROGRADE WELL FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：用于超级退火井场效应晶体管的硅介质轮廓的方法
公开(公告)号：US20140070358A1
公开(公告)日：2014-03-13
申请号：US13612032
申请日：2012-09-12
申请人： Yi Qi , Puneet Khanna , Srikanth Samavedam , Vara G. Vakada , Michael P. Ganz , Sri Charan Vemula , Laegu Kang , Bharat V. Krishnan
发明人： Yi Qi , Puneet Khanna , Srikanth Samavedam , Vara G. Vakada , Michael P. Ganz , Sri Charan Vemula , Laegu Kang , Bharat V. Krishnan
IPC分类号： H01L29/06 , H01L21/76
CPC分类号： H01L21/76224 , H01L21/02381 , H01L21/02529 , H01L21/02658
摘要： A methodology is disclosed enabling the formation of silicon trench profiles for devices, such as SSRW FETs, having a resultant profile that enables desirable epitaxial growth of semiconductor materials. Embodiments include forming a trench in a silicon wafer between STI regions, thermally treating the silicon surfaces of the trench, and forming Si:C in the trench. The process eliminates a need for an isotropic silicon etch to achieve a desirable flat surface. Further, the flat bottom surface provides a desirable surface for epitaxial growth of semiconductor materials, such as Si:C.
摘要翻译：公开了一种能够形成用于诸如SSRW FET的器件的硅沟槽轮廓的方法，其具有能够实现半导体材料的期望的外延生长的合成轮廓。实施例包括在STI区域之间的硅晶片中形成沟槽，热处理沟槽的硅表面，并在沟槽中形成Si：C。该方法消除了对各向同性硅蚀刻的需要以实现期望的平坦表面。此外，平坦的底表面为诸如Si：C的半导体材料的外延生长提供期望的表面。

6. 发明申请

US20120273894A1 HIGH PRESSURE DEUTERIUM TREATMENT FOR SEMICONDUCTOR/HIGH-K INSULATOR INTERFACE 有权
标题翻译：用于半导体/高K绝缘体接口的高压电解铜处理
公开(公告)号：US20120273894A1
公开(公告)日：2012-11-01
申请号：US13094873
申请日：2011-04-27
申请人： Xiangdong Chen , Laegu Kang , Weipeng Li , Dae-Gyu Park , Melanie J. Sherony
发明人： Xiangdong Chen , Laegu Kang , Weipeng Li , Dae-Gyu Park , Melanie J. Sherony
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/28176 , H01L21/3003 , H01L21/8258 , H01L29/1054 , H01L29/665 , H01L29/7843
摘要： An integrated circuit structure comprises at least one pair of complementary transistors on a substrate. The pair of complementary transistors includes a first transistor and a second transistor. In addition, only one stress-producing layer is on the first transistor and the second transistor and applies tensile strain force on the first transistor and the second transistor. The first transistor has a first channel region, a gate insulator on the first channel region, and a deuterium region between the first channel region and the gate insulator. The second transistor has a germanium doped channel region, as well as the same gate insulator on the germanium doped channel region, and the same deuterium region between the germanium doped channel region and the gate insulator.
摘要翻译：集成电路结构在衬底上包括至少一对互补晶体管。一对互补晶体管包括第一晶体管和第二晶体管。此外，在第一晶体管和第二晶体管上只有一个应力产生层，并且在第一晶体管和第二晶体管上施加拉伸应变力。第一晶体管具有第一沟道区，第一沟道区上的栅极绝缘体，以及第一沟道区和栅绝缘体之间的氘区。第二晶体管具有锗掺杂沟道区以及锗掺杂沟道区上的相同栅极绝缘体以及锗掺杂沟道区和栅绝缘体之间的相同氘区。

7. 发明授权

US08106462B2 Balancing NFET and PFET performance using straining layers 失效
标题翻译：使用应变层平衡NFET和PFET性能
公开(公告)号：US08106462B2
公开(公告)日：2012-01-31
申请号：US12687374
申请日：2010-01-14
申请人： Xiangdong Chen , Weipeng Li , Anda C. Mocuta , Dae-Gyu Park , Melanie J. Sherony , Kenneth J. Stein , Haizhou Yin , Franck Arnaud , Jin-Ping Han , Laegu Kang , Yong Meng Lee , Young Way Teh , Voon-Yew Thean , Da Zhang
发明人： Xiangdong Chen , Weipeng Li , Anda C. Mocuta , Dae-Gyu Park , Melanie J. Sherony , Kenneth J. Stein , Haizhou Yin , Franck Arnaud , Jin-Ping Han , Laegu Kang , Yong Meng Lee , Young Way Teh , Voon-Yew Thean , Da Zhang
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L29/7843
摘要： An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.
摘要翻译：集成电路结构包括衬底和衬底上或衬底中的至少一对互补晶体管。该对互补晶体管包括第一晶体管和第二晶体管。该结构还包括第一晶体管和第二晶体管上的第一应力产生层，以及在第一晶体管和第二晶体管上的第一应力产生层上的第二应力产生层。第一应力产生层在第一晶体管和第二晶体管上施加拉伸应变力。第二应力产生层对第一应力产生层，第一晶体管和第二晶体管施加压缩应变力。

8. 发明授权

US07795089B2 Forming a semiconductor device having epitaxially grown source and drain regions 有权
标题翻译：形成具有外延生长的源区和漏区的半导体器件
公开(公告)号：US07795089B2
公开(公告)日：2010-09-14
申请号：US11680219
申请日：2007-02-28
申请人： Laegu Kang , Vishal P. Trivedi , Da Zhang
发明人： Laegu Kang , Vishal P. Trivedi , Da Zhang
IPC分类号： H01L21/8238
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/84 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/66772
摘要： A semiconductor device structure is made on a semiconductor substrate having a semiconductor layer having isolation regions. A first gate structure is formed over a first region of the semiconductor layer, and a second gate structure is over a second region of the semiconductor layer. A first insulating layer is formed over the first and second regions. The first insulating layer can function as a mask during an etch of the semiconductor layer and can be removed selective to the isolation regions and the sidewall spacers. The first insulating layer is removed from over the first region to leave a remaining portion of the first insulating layer over the second region. The semiconductor layer is recessed in the first region adjacent to the first gate to form recesses. A semiconductor material is epitaxially grown in the recesses. The remaining portion of the first insulating layer is removed.
摘要翻译：在具有具有隔离区域的半导体层的半导体衬底上制造半导体器件结构。第一栅极结构形成在半导体层的第一区域上，第二栅极结构在半导体层的第二区域之上。在第一和第二区域上形成第一绝缘层。第一绝缘层可以在半导体层的蚀刻期间用作掩模，并且可以选择性地去除隔离区域和侧壁间隔物。从第一区域上去除第一绝缘层，以在第二区域上留下第一绝缘层的剩余部分。半导体层凹入与第一栅极相邻的第一区域中以形成凹陷。在凹部中外延生长半导体材料。去除第一绝缘层的剩余部分。

9. 发明授权

US07517742B2 Area diode formation in SOI application 有权
标题翻译： SOI应用中的二极管形成区域
公开(公告)号：US07517742B2
公开(公告)日：2009-04-14
申请号：US11158021
申请日：2005-06-21
申请人： Byoung W. Min , Laegu Kang , Michael Khazhinsky
发明人： Byoung W. Min , Laegu Kang , Michael Khazhinsky
IPC分类号： H01L21/20
CPC分类号： H01L21/84 , H01L27/0255 , H01L27/1203
摘要： A method for making a semiconductor device is provided herein. In accordance with the method, a semiconductor stack is provided which includes a semiconductor substrate, a first semiconductor layer, and a first dielectric layer disposed between the substrate and the first semiconductor layer. A first trench is formed in the first dielectric layer which exposes a portion of the substrate, and a first implant region is formed in the first trench. Cathode and anode regions are formed in the first implant region.
摘要翻译：本发明提供制造半导体器件的方法。根据该方法，提供一种半导体堆叠，其包括半导体衬底，第一半导体层和设置在衬底和第一半导体层之间的第一电介质层。在第一电介质层中形成第一沟槽，其暴露衬底的一部分，并且在第一沟槽中形成第一注入区域。阴极和阳极区域形成在第一植入区域中。

10. 发明授权

US5068200A Method of manufacturing DRAM cell 失效
标题翻译：制造DRAM单元的方法
公开(公告)号：US5068200A
公开(公告)日：1991-11-26
申请号：US490326
申请日：1990-03-08
申请人： Laegu Kang , Kyungtae Kim
发明人： Laegu Kang , Kyungtae Kim
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/78
CPC分类号： H01L27/10852 , H01L27/10808
摘要： This invention relates to a method of manufacturing a DRAM cell which has a stacked capacitor and forming drain and source polycrystalline silicon regions on surface of a semiconductor substrate. The invention is directed to: a first step for forming a field oxide film and channel stopper as well as a polycrystalline silicon oxide film doped with impurities; a second step for dividing said silicon into a drain and source polycrystalline silicon region and forming a gate oxide film between the two silicon regions simultaneously with the drain and source diffusion regions and a gate electrode on the gate nitride film; a third step for forming an insulating film on the upper surface of the nitride film and a window on the source polycrystalline silicon region, a storage poly contacting with the same through the window; a fourth step for forming a dielectric layer and a plate poly of the stacked capacitor; and a fifth step forming another insulating film thereon and forming a window on the drain polycrystalline silicon region and also forming a bit line contacting with the exposed drain polycrystalline silicon region through that window. This invention can prevent the generation of leakage current resulting from the damage caused by the drain and source diffusion polycrystalline silicon regions when an etching process is used for the formation of the storage poly and the bit line.
摘要翻译：本发明涉及一种具有堆叠电容器并在半导体衬底的表面上形成漏极和源极多晶硅区域的DRAM单元的制造方法。本发明涉及：形成场氧化物膜和通道阻挡物的第一步骤以及掺杂有杂质的多晶氧化硅膜; 将所述硅分成漏极和源极多晶硅区域并在所述两个硅区域之间与所述漏极和源极扩散区域同时形成栅极氧化膜以及所述栅极氮化物膜上的栅电极的第二步骤; 用于在氮化物膜的上表面上形成绝缘膜的第三步骤和源多晶硅区域上的窗口，通过窗口与其接触的储存器; 用于形成叠层电容器的电介质层和板状多晶硅的第四步骤; 以及在其上形成另一绝缘膜并在漏极多晶硅区域上形成窗口的第五步骤，并且还形成通过该窗口与暴露的漏极多晶硅区域接触的位线。本发明可以防止当使用蚀刻工艺形成存储多晶硅和位线时由漏极和源极扩散多晶硅区域引起的损坏产生漏电流。

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