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1. 发明授权

US07673270B1 Method and apparatus for compensating an integrated circuit layout for mechanical stress effects 有权
标题翻译：用于补偿机械应力影响的集成电路布局的方法和装置
公开(公告)号：US07673270B1
公开(公告)日：2010-03-02
申请号：US11717811
申请日：2007-03-13
申请人： Yan Wang , Nui Chong , Hong-Tsz Pan , Bang-Thu Nguyen , Jonathan Jung-Ching Ho , Qi Lin , Yuhao Luo , Hing Yee Angela Wong , Xin X. Wu , Yuezhen Fan
发明人： Yan Wang , Nui Chong , Hong-Tsz Pan , Bang-Thu Nguyen , Jonathan Jung-Ching Ho , Qi Lin , Yuhao Luo , Hing Yee Angela Wong , Xin X. Wu , Yuezhen Fan
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： Method and apparatus for compensating an integrated circuit design for mechanical stress effects. One aspect of the invention relates to designing an integrated circuit. Layout data is obtained that describes layers of the integrated circuit. At least one of the layers is analyzed to detect at least one structure susceptible to damage from mechanical stress. A bias is automatically added to each of the at least one structure to reduce mechanical stress of the at least one structure as fabricated. Augmented layout data is then provided for the integrated circuit.
摘要翻译：用于补偿机械应力作用的集成电路设计的方法和装置。本发明的一个方面涉及集成电路的设计。获得描述集成电路层的布局数据。分析至少一层以检测易受机械应力破坏的至少一种结构。偏置被自动地添加到至少一个结构中的每个结构中，以减少所制造的至少一个结构的机械应力。然后为集成电路提供增强的布局数据。

2. 发明授权

US08194372B1 Systems and methods for electrostatic discharge protection 有权
标题翻译：静电放电保护系统和方法
公开(公告)号：US08194372B1
公开(公告)日：2012-06-05
申请号：US12424810
申请日：2009-04-16
申请人： Nui Chong , Hong-Tsz Pan
发明人： Nui Chong , Hong-Tsz Pan
IPC分类号： H02H9/00
CPC分类号： H01L27/0274
摘要： A system for protecting an integrated circuit (IC) from electrostatic discharge (ESD) events includes a sensing circuit that detects an occurrence of an ESD event on one of a plurality of power supply rails of the IC and, in response, outputs an alert signal identifying the occurrence of the ESD event. The system includes a driver circuit that, responsive to receiving the alert signal, outputs an enable signal, and a cascaded switch. The cascaded switch includes first and second gates disposed upon a channel located between a drain of the cascaded switch coupled to a first power supply rail and a source of the cascaded switch coupled to a second power supply rail. Each of the two gates receives the enable signal and, responsive to the enable signal, the cascaded switch closes to establish a coupling between the first power supply rail and the second power supply rail.
摘要翻译：用于保护集成电路（IC）免受静电放电（ESD）事件的系统包括感测电路，其检测IC的多个电源轨道中的一个上的ESD事件的发生，并且作为响应，输出警报信号识别ESD事件的发生。该系统包括响应于接收到警报信号而输出使能信号和级联开关的驱动器电路。级联开关包括设置在耦合到第一电源轨的级联开关的漏极和耦合到第二电源轨的级联开关的源之间的通道的第一和第二门。两个门中的每一个接收使能信号，响应于使能信号，级联开关闭合以建立第一电源轨和第二电源轨之间的耦合。

3. 发明授权

US08068004B1 Embedded inductor 有权
标题翻译：嵌入式电感
公开(公告)号：US08068004B1
公开(公告)日：2011-11-29
申请号：US12699734
申请日：2010-02-03
申请人： Nui Chong , Hong-Tsz Pan
发明人： Nui Chong , Hong-Tsz Pan
IPC分类号： H01F27/28 , H01F27/29 , H01F5/00 , H01F7/06
CPC分类号： H01L23/5227 , H01F17/0013 , H01L2924/0002 , Y10T29/4902 , Y10T29/49071 , Y10T29/49073 , H01L2924/00
摘要： An embedded inductor and a method for forming an inductor are described. Spaced apart first stripes are formed substantially parallel with respect to one another as part of a first metal layer. First contacts, second contacts, and third contacts in respective combination provide at least portions of posts. Spaced apart second stripes substantially parallel with respect to one another and to the first stripes are formed as part of a second metal layer located between the first metal layer and the second metal layer. The first stripes, the posts, and the second stripes in combination provide turns of a coil.
摘要翻译：描述了嵌入式电感器和形成电感器的方法。间隔开的第一条纹形成为相对于彼此大致平行，作为第一金属层的一部分。相应组合中的第一个联系人，第二个联系人和第三个联系人至少提供部分帖子。基本上相对于彼此平行并且与第一条纹相隔的间隔开的第二条纹被形成为位于第一金属层和第二金属层之间的第二金属层的一部分。组合的第一条纹，柱和第二条纹提供线圈的转弯。

4. 发明申请

US20050213271A1 Electrostatic discharge protection circuits 审中-公开
标题翻译：静电放电保护电路
公开(公告)号：US20050213271A1
公开(公告)日：2005-09-29
申请号：US10808627
申请日：2004-03-24
申请人： Nui Chong , Aaron Rogers , Kerry Ilgenstein
发明人： Nui Chong , Aaron Rogers , Kerry Ilgenstein
IPC分类号： H02H9/00 , H02H9/04
CPC分类号： H02H9/046
摘要： Systems and methods disclosed provide electrostatic discharge protection. For example, in accordance with an embodiment of the present invention, a circuit is disclosed having a diode string and a transistor in a cascode configuration that provides electrostatic discharge (ESD) protection and can operate in a mixed voltage environment.
摘要翻译：所公开的系统和方法提供静电放电保护。例如，根据本发明的实施例，公开了一种电路，其具有二极管串和提供静电放电（ESD）保护并可在混合电压环境中工作的共源共栅配置中的晶体管。

5. 发明申请

US20060125014A1 Diode with low junction capacitance 审中-公开
标题翻译：具有低结电容的二极管
公开(公告)号：US20060125014A1
公开(公告)日：2006-06-15
申请号：US11012466
申请日：2004-12-14
申请人： Nui Chong , Chun Jiang , Loc Nguyen
发明人： Nui Chong , Chun Jiang , Loc Nguyen
IPC分类号： H01L23/62
CPC分类号： H01L29/861 , H01L27/0255 , H01L27/0811 , H01L27/0814
摘要： A diode is comprised of a doped region formed with a first dopant of a first conductivity type. In addition, the diode further comprises a substrate doped with a second dopant of a second conductivity type opposite of the first conductivity type. The lightly doped substrate, instead of a well, abuts the doped region for minimizing a junction capacitance of the diode. Such a diode is especially advantageous for ESD (electro-static discharge) protection of high speed integrated circuits.
摘要翻译：二极管由形成有第一导电类型的第一掺杂剂的掺杂区组成。此外，二极管还包括掺杂有与第一导电类型相反的第二导电类型的第二掺杂剂的衬底。轻掺杂衬底（而不是阱）邻接掺杂区域以最小化二极管的结电容。这种二极管对于高速集成电路的ESD（静电放电）保护是特别有利的。

6. 发明授权

US07307319B1 High-voltage protection device and process 有权
标题翻译：高压保护装置及工艺
公开(公告)号：US07307319B1
公开(公告)日：2007-12-11
申请号：US10837086
申请日：2004-04-30
申请人： Nui Chong , Farrokh Omid-Zohoor
发明人： Nui Chong , Farrokh Omid-Zohoor
IPC分类号： H01L23/62
CPC分类号： H01L29/8611 , H01L27/0255 , H01L29/6656 , H01L29/66659 , H01L29/7391 , H01L29/78
摘要： A high-voltage circuit protection device includes a p-n junction in a semiconductor substrate that is spaced apart from a first electrode region by a diode region. A semiconductor layer overlies the diode region and is separated therefrom by a dielectric layer. A shallow-doped region resides in the diode region spaced apart from the p-n junction by a predetermined distance. The predetermined distance preferably ranges from about 0 to about 50% of the length of the diode region. A process for fabricating the high-voltage device includes forming the shallow-doped region using a threshold adjustment mask followed by formation of the first electrode region using the semiconductor layer in a self-aligned doping process. The shallow-doped region functions to reduce the clamping voltage of the device.
摘要翻译：高电压电路保护装置包括在半导体衬底中的通过二极管区与第一电极区间隔开的p-n结。半导体层覆盖二极管区域，并通过介电层与其分离。浅掺杂区域位于与p-n结隔开预定距离的二极管区域中。预定距离优选在二极管区域的长度的约0至约50％的范围内。一种用于制造高压器件的工艺包括使用阈值调节掩模形成浅掺杂区域，随后在自对准掺杂工艺中使用半导体层形成第一电极区域。浅掺杂区域用于降低器件的钳位电压。

7. 发明申请

US20060157748A1 Metal junction diode and process 审中-公开
标题翻译：金属结二极管和工艺
公开(公告)号：US20060157748A1
公开(公告)日：2006-07-20
申请号：US11038998
申请日：2005-01-20
申请人： Nui Chong , Farrokh Omid-Zohoor
发明人： Nui Chong , Farrokh Omid-Zohoor
IPC分类号： H01L29/76
CPC分类号： H01L29/66136 , H01L29/861 , H01L29/872 , H01L29/93
摘要： A junction diode includes a substrate having first and second cathode regions separated by an anode region. Metal silicide layers contact the first and second cathode regions and the anode regions. The anode region has a doping concentration sufficient to create a depletion region in the anode region adjacent to the metal silicide layer contacting the anode region. A fabrication process includes forming the anode region to have a doping concentration that increases in a direction into the anode region away from the substrate surface.
摘要翻译：结二极管包括具有由阳极区分开的第一和第二阴极区的衬底。金属硅化物层接触第一和第二阴极区域和阳极区域。阳极区域具有足以在与阳极区域接触的金属硅化物层相邻的阳极区域中产生耗尽区的掺杂浓度。一种制造工艺包括形成阳极区域以使得在朝向衬底表面的阳极区域的方向上增加的掺杂浓度。

8. 发明授权

US07024646B2 Electrostatic discharge simulation 有权
标题翻译：静电放电模拟
公开(公告)号：US07024646B2
公开(公告)日：2006-04-04
申请号：US10769174
申请日：2004-01-29
申请人： Stewart Logie , Farrokh Kia Omid-Zohoor , Nui Chong
发明人： Stewart Logie , Farrokh Kia Omid-Zohoor , Nui Chong
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Systems and methods provide electrostatic discharge simulation techniques. For example, a method in accordance with an embodiment of the present invention provides a simulation of electrostatic discharge in integrated circuits. The method may allow for the design of protection circuits and simulating electrostatic discharge events concurrently with the design of the associated electrical circuit.
摘要翻译：系统和方法提供静电放电模拟技术。例如，根据本发明的实施例的方法提供了集成电路中的静电放电的模拟。该方法可以允许保护电路的设计和与相关电路的设计同时模拟静电放电事件。

9. 发明申请

US20050172246A1 Electrostatic discharge simulation 有权
标题翻译：静电放电模拟
公开(公告)号：US20050172246A1
公开(公告)日：2005-08-04
申请号：US10769174
申请日：2004-01-29
申请人： Stewart Logie , Farrokh Omid-Zohoor , Nui Chong
发明人： Stewart Logie , Farrokh Omid-Zohoor , Nui Chong
IPC分类号： G06F17/50 , H01F27/28
CPC分类号： G06F17/5036
摘要： Systems and methods provide electrostatic discharge simulation techniques. For example, a method in accordance with an embodiment of the present invention provides a simulation of electrostatic discharge in integrated circuits. The method may allow for the design of protection circuits and simulating electrostatic discharge events concurrently with the design of the associated electrical circuit.
摘要翻译：系统和方法提供静电放电模拟技术。例如，根据本发明的实施例的方法提供了集成电路中的静电放电的模拟。该方法可以允许保护电路的设计和与相关电路的设计同时模拟静电放电事件。

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