专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07024646B2 Electrostatic discharge simulation 有权
标题翻译：静电放电模拟
公开(公告)号：US07024646B2
公开(公告)日：2006-04-04
申请号：US10769174
申请日：2004-01-29
申请人： Stewart Logie , Farrokh Kia Omid-Zohoor , Nui Chong
发明人： Stewart Logie , Farrokh Kia Omid-Zohoor , Nui Chong
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Systems and methods provide electrostatic discharge simulation techniques. For example, a method in accordance with an embodiment of the present invention provides a simulation of electrostatic discharge in integrated circuits. The method may allow for the design of protection circuits and simulating electrostatic discharge events concurrently with the design of the associated electrical circuit.
摘要翻译：系统和方法提供静电放电模拟技术。例如，根据本发明的实施例的方法提供了集成电路中的静电放电的模拟。该方法可以允许保护电路的设计和与相关电路的设计同时模拟静电放电事件。

2. 发明申请

US20050172246A1 Electrostatic discharge simulation 有权
标题翻译：静电放电模拟
公开(公告)号：US20050172246A1
公开(公告)日：2005-08-04
申请号：US10769174
申请日：2004-01-29
申请人： Stewart Logie , Farrokh Omid-Zohoor , Nui Chong
发明人： Stewart Logie , Farrokh Omid-Zohoor , Nui Chong
IPC分类号： G06F17/50 , H01F27/28
CPC分类号： G06F17/5036
摘要： Systems and methods provide electrostatic discharge simulation techniques. For example, a method in accordance with an embodiment of the present invention provides a simulation of electrostatic discharge in integrated circuits. The method may allow for the design of protection circuits and simulating electrostatic discharge events concurrently with the design of the associated electrical circuit.
摘要翻译：系统和方法提供静电放电模拟技术。例如，根据本发明的实施例的方法提供了集成电路中的静电放电的模拟。该方法可以允许保护电路的设计和与相关电路的设计同时模拟静电放电事件。

3. 发明授权

US06627947B1 Compact single-poly two transistor EEPROM cell 有权
标题翻译：紧凑型单晶双晶体管EEPROM单元
公开(公告)号：US06627947B1
公开(公告)日：2003-09-30
申请号：US09643279
申请日：2000-08-22
申请人： Yongzhong Hu , Jein Chen Young , Stewart Logie
发明人： Yongzhong Hu , Jein Chen Young , Stewart Logie
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , G11C16/0433 , H01L27/115 , H01L29/7885
摘要： A non-volatile memory cell at least partially formed in a semiconductor substrate. The cell comprises a first transistor comprising a high voltage NMOS transistor having a first active region and a second active region; a second transistor sharing said second active region and having a third active region in said substrate; an active control gate region formed in said substrate; a polysilicon layer having a first portion forming a gate for said first transistor, and a second portion forming gate for said second transistor and a floating gate overlying said active control gate region. In one embodiment, an oxynitride separates said second portion and said active control gate region.
摘要翻译：至少部分地形成在半导体衬底中的非易失性存储单元。该单元包括第一晶体管，其包括具有第一有源区和第二有源区的高电压NMOS晶体管; 共享所述第二有源区并在所述衬底中具有第三有源区的第二晶体管; 形成在所述基板中的有源控制栅极区域; 多晶硅层，具有形成所述第一晶体管的栅极的第一部分，以及形成所述第二晶体管的栅极的第二部分和覆盖所述有源控制栅极区域的浮动栅极。在一个实施例中，氧氮化物分离所述第二部分和所述主动控制栅极区域。

4. 发明授权

US5742542A Non-volatile memory cells using only positive charge to store data 失效
标题翻译：非易失性存储单元仅使用正电荷来存储数据
公开(公告)号：US5742542A
公开(公告)日：1998-04-21
申请号：US497992
申请日：1995-07-03
申请人： Jonathan Lin , Stewart Logie
发明人： Jonathan Lin , Stewart Logie
IPC分类号： G11C16/04 , H01L27/115 , H01L29/78
CPC分类号： H01L27/115 , G11C16/0433 , G11C16/0441
摘要： An improved EEPROM structure is provided which has a longer data retention period. This is achieved by utilizing only positive charges to store data on the floating gate. The EEPROM structure includes a write select transistor (112), a read select transistor (120), and a floating gate sense transistor (126). The source of the write select transistor is capacitively coupled to the floating gate of the floating gate sense transistor via a tunnel oxide layer (145). The floating gate of the floating gate sense transistor is also capacitively coupled to a control gate line (CG) via a gate oxide layer (153). The sense transistor is formed as an enhancement transistor so as to allow the EEPROM structure to be operated in a region where the floating gate potential is positive for both programmed and erased conditions, thereby using only the positive charges to store data.
摘要翻译：提供了一种改进的EEPROM结构，其具有较长的数据保留期。这通过仅利用正电荷将数据存储在浮动栅极上来实现。 EEPROM结构包括写选择晶体管（112），读选晶体管（120）和浮栅读出晶体管（126）。写选择晶体管的源极经由隧道氧化物层（145）电容耦合到浮置栅极检测晶体管的浮置栅极。浮置栅极检测晶体管的浮置栅极也经由栅极氧化物层（153）电容耦合到控制栅极线（CG）。感测晶体管形成为增强型晶体管，以使得EEPROM结构在编程和擦除条件下的浮置栅极电位为正的区域中工作，从而仅使用正电荷来存储数据。

5. 发明授权

US4924278A EEPROM using a merged source and control gate 失效
标题翻译： EEPROM使用合并源和控制门
公开(公告)号：US4924278A
公开(公告)日：1990-05-08
申请号：US274633
申请日：1988-11-15
申请人： Stewart Logie
发明人： Stewart Logie
IPC分类号： G11C16/04 , H01L27/115
CPC分类号： G11C16/0433 , H01L27/115 , G11C16/0441 , G11C2216/10
摘要： A single layer of polycrystalline silicon (poly-Si) is used in an EEPROM structure, which obviates the need to form a separate control gate and floating gate. The EEPROM utilizes three separate NMOS transistors: a write transistor, a read transistor, and a sense transistor. A thin tunnel oxide layer separates the N+ source region of the write transistor from an N doped poly-Si layer and capacitively couples the source region to the poly-Si layer. The poly-Si layer extends over the N+ source region of the sense transistor and is capacitively coupled to the source region of the sense transistor via a thin gate oxide insulating layer which is thicker than the oxide layer comprising the tunnel oxide layer. This poly-Si layer continues to extend over a channel region separating the N+ source and N+ drain regions of the sense transistor, the poly-Si layer being separated from the channel via the thin gate oxide insulating layer. The drain of the sense transistor also acts as the source of the read transistor. In the above structure, the poly-Si layer acts as the floating gate over the channel of the sense transistor. Since the poly-Si floating gate is both capacitively coupled to the source of the sense transistor and to the source of the write transistor, no separate control gate or control gate electrode is needed (the source of the sense transistor acts as the control gate). The structure, inter alia, enables a higher coupling ratio during erasing, thus allowing faster erase times by coupling a higher voltage onto the poly-Si floating gate.
摘要翻译：在EEPROM结构中使用单层多晶硅（poly-Si），这消除了形成单独的控制栅极和浮动栅极的需要。 EEPROM使用三个独立的NMOS晶体管：写晶体管，读晶体管和检测晶体管。薄隧道氧化物层将写入晶体管的N +源极区域与N掺杂多晶硅层分离，并将源极区域电容耦合到多晶硅层。多晶硅层在感测晶体管的N +源极区域上延伸，并且通过比包含隧道氧化物层的氧化物层厚的薄栅极氧化物绝缘层电容耦合到读出晶体管的源极区域。该多晶硅层继续在分离感测晶体管的N +源极和N +漏极区域的沟道区域上延伸，多晶硅层通过薄栅极氧化物绝缘层与沟道分离。读出晶体管的漏极也用作读取晶体管的源极。在上述结构中，多晶硅层用作感测晶体管的沟道上的浮栅。由于多晶硅浮置栅极电容耦合到感测晶体管的源极和写入晶体管的源极，因此不需要单独的控制栅极或控制栅电极（感测晶体管的源极用作控制栅极）。该结构尤其能够在擦除期间实现更高的耦合比，从而通过将更高电压耦合到多晶硅浮栅上而允许更快的擦除时间。

6. 发明授权

US07989911B1 Shallow trench isolation (STI) with trench liner of increased thickness 有权
标题翻译：浅沟槽隔离（STI），沟槽衬垫厚度增加
公开(公告)号：US07989911B1
公开(公告)日：2011-08-02
申请号：US12607868
申请日：2009-10-28
申请人： Sunil Mehta , Stewart Logie , Steven Fong
发明人： Sunil Mehta , Stewart Logie , Steven Fong
IPC分类号： H01L21/70
CPC分类号： H01L21/76224
摘要： In one embodiment, an integrated circuit includes a substrate having high voltage transistor regions and low voltage transistor regions. The substrate includes a first trench between and adjacent to the high voltage transistor regions, a second trench between and adjacent to the low voltage transistor regions, and a third trench between the first and second trenches and between and adjacent to a high voltage transistor region and a low voltage transistor region. A thicker silicon dioxide layer lines the first trench and a first portion of the third trench adjacent to a high voltage transistor region. A thinner silicon dioxide layer lines the second trench and a second portion of the third trench adjacent to a low voltage transistor region. A silicon nitride layer is present on the thinner silicon dioxide layer and lines the second trench and the second portion of the third trench but is not present on the thicker silicon dioxide layer and does not line the first trench and the first portion of the third trench.
摘要翻译：在一个实施例中，集成电路包括具有高电压晶体管区域和低压晶体管区域的衬底。衬底包括在高电压晶体管区域之间和之间相邻的第一沟槽，在低电压晶体管区域之间和之间的第二沟槽，以及在第一和第二沟槽之间并且在高压晶体管区域之间和之间的第三沟槽，以及低压晶体管区域。较厚的二氧化硅层将第一沟槽和第三沟槽的与高压晶体管区域相邻的第一部分排列。更薄的二氧化硅层将第二沟槽和第三沟槽的与低压晶体管区域相邻的第二部分排列。氮化硅层存在于较薄的二氧化硅层上，并且使第二沟槽和第三沟槽的第二部分排列，但是不存在于较厚的二氧化硅层上，并且不使第一沟槽和第三沟槽的第一部分。

7. 发明申请

US20050093069A1 Lateral high-voltage junction device 有权
标题翻译：横向高压接线装置
公开(公告)号：US20050093069A1
公开(公告)日：2005-05-05
申请号：US10699321
申请日：2003-10-31
申请人： Stewart Logie
发明人： Stewart Logie
IPC分类号： H01L20060101 , H01L23/62 , H01L27/01 , H01L27/02 , H01L27/12 , H01L29/735 , H01L29/78 , H01L31/0392 , H01L31/119
CPC分类号： H01L27/0266 , H01L29/735 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A lateral high-voltage junction device for over-voltage protection of an MOS circuit includes a substrate having a first junction region separated from a second junction region by a substrate region. An MOS gate electrode overlies the substrate region and is separated therefrom by a gate dielectric layer. Sidewall spacers reside adjacent to opposing sides of the MOS gate electrode and overlie the substrate region. The substrate region is defined by a junction-free semiconductor region between the first and second junction regions. An input protection circuit employs the lateral high-voltage junction device to transfer voltage transients to a ground node.
摘要翻译：用于MOS电路的过电压保护的横向高压结装置包括具有通过衬底区域与第二接合区域分离的第一结区域的衬底。 MOS栅电极覆盖在衬底区域上，并由栅介电层分离。侧壁间隔件邻近MOS栅电极的相对侧并且覆盖在衬底区域上。衬底区域由第一和第二结区域之间的无结半导体区域限定。输入保护电路采用横向高压接合装置将电压瞬变转移到接地节点。

8. 发明授权

US06841447B1 EEPROM device having an isolation-bounded tunnel capacitor and fabrication process 失效
标题翻译： EEPROM器件具有隔离有限的隧道电容器和制造工艺
公开(公告)号：US06841447B1
公开(公告)日：2005-01-11
申请号：US10232912
申请日：2002-08-30
申请人： Stewart Logie , Sunil D. Mehta
发明人： Stewart Logie , Sunil D. Mehta
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11558
摘要： A semiconductor device having an EEPROM memory cell includes a substrate having a principal surface and an isolation region having an inner edge surface bounding the tunnel region at the principal surface. The isolation region forms a perimeter of the tunnel region. A capacitor plate overlies the tunnel region and substantially the entire perimeter of the tunnel region. A tunnel dielectric layer overlies the tunnel region and separates the capacitor plate from the tunnel dielectric layer. The edges of the capacitor plate are displaced away from the tunnel dielectric layer to avoid a loss of tunneling current as a result of edge degradation with repeated programming and erasing of the EEPROM memory device. A process for fabrication of the device is also provided.
摘要翻译：具有EEPROM存储单元的半导体器件包括具有主表面的衬底和具有限定主表面处的隧道区域的内边缘表面的隔离区域。隔离区域形成隧道区域的周长。电容器板覆盖隧道区域和基本上隧道区域的整个周边。隧道介电层覆盖隧道区域，并将电容器板与隧道介电层分开。电容器板的边缘从隧道介电层移开，以避免由于EEPROM存储器件的重复编程和擦除而引起边缘劣化的结果，隧道电流的损失。还提供了该装置的制造工艺。

9. 发明授权

US06660579B1 Zero power memory cell with improved data retention 有权
标题翻译：零功率存储单元，具有改进的数据保留
公开(公告)号：US06660579B1
公开(公告)日：2003-12-09
申请号：US10128943
申请日：2002-04-24
申请人： Chun Jiang , Sunil Mehta , Stewart Logie
发明人： Chun Jiang , Sunil Mehta , Stewart Logie
IPC分类号： H01L218238
CPC分类号： H01L27/11521 , H01L21/823807 , H01L21/823892 , H01L27/115 , H01L27/11558
摘要： A method for forming a three transistor zero power memory cell including a p-channel sense transistor, an n-channel write transistor, and an n-channel sense transistor including: implanting a p-type impurity into a p-type substrate in which a n-channel high voltage transistor will be formed; implanting an n-type impurity into an n-type well in a p-type substrate in which a p-channel high voltage transistor will be formed; forming a mask to allow implants to occur to p-channel devices; performing a series of n-type dopant implants into the substrate where the p-channel transistors will be formed; growing a high voltage gate oxide; forming a mask to allow implants to occur to n-channel devices, said mask blocking implants to said n-channel sense transistor; and performing a series of p-type implants into the substrate where the n-channel devices will be formed. In addition, a memory cell which may include a first NMOS transistor having a source, drain and gate, and a first PMOS transistor is disclosed. The memory cell includes a first and second NMOS transistors, and a PMOS transistor, wherein the first NMOS transistor and first PMOS transistor each include a three implant channel region, and wherein the second NMOS transistor further includes a two implant channel region.
摘要翻译：一种用于形成包括p沟道读出晶体管，n沟道写晶体管和n沟道读出晶体管的三晶体管零功率存储单元的方法，包括：p型杂质注入到p型衬底中，其中将形成n沟道高压晶体管; 在其中将形成p沟道高压晶体管的p型衬底中将n型杂质注入到n型阱中; 形成掩模以允许植入物对p沟道器件发生; 在其中将形成p沟道晶体管的衬底中执行一系列n型掺杂剂注入; 生长高压栅氧化物; 形成掩模以允许对n沟道器件发生植入物，所述掩模阻挡对所述n沟道感测晶体管的注入; 并在其中将形成n沟道器件的衬底中执行一系列p型注入。此外，公开了一种存储单元，其可以包括具有源极，漏极和栅极的第一NMOS晶体管和第一PMOS晶体管。存储单元包括第一和第二NMOS晶体管和PMOS晶体管，其中第一NMOS晶体管和第一PMOS晶体管各自包括三个注入沟道区，并且其中第二NMOS晶体管还包括两个注入沟道区。

10. 发明授权

US06570212B1 Complementary avalanche injection EEPROM cell 失效
标题翻译：互补雪崩注入EEPROM单元
公开(公告)号：US06570212B1
公开(公告)日：2003-05-27
申请号：US09578086
申请日：2000-05-24
申请人： Sunil D. Mehta , Steven Fong , Stewart Logie
发明人： Sunil D. Mehta , Steven Fong , Stewart Logie
IPC分类号： H01L27108
CPC分类号： H01L27/11526 , G11C16/0441 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11529 , H01L27/11558 , H01L29/66825
摘要： A non-volatile memory cell at least partially formed in a semiconductor substrate, comprising a first avalanche injection element having a first active region of a first conductivity type and a second active region of a second conductivity type, separated by a channel region of said second conductivity type; a second avalanche injection element having a third active region of said second conductivity type and sharing said second active region with said first avalanche injection element, the second avalanche injection element having a channel region of said first conductivity type; and a common floating gate at least partially overlying said first and second avalanche injection elements. In a further embodiment, the first avalanche element has an N+/P junction, the second avalanche element has a P+/N junction, and the floating gate capacitively coupled to the first and second avalanche elements.
摘要翻译：至少部分地形成在半导体衬底中的非易失性存储单元，包括具有第一导电类型的第一有源区和第二导电类型的第二有源区的第一雪崩注入元件，由所述第二导电类型的沟道区分隔开导电型; 第二雪崩注入元件，具有所述第二导电类型的第三有源区，并且与所述第一雪崩注入元件共享所述第二有源区，所述第二雪崩注入元件具有所述第一导电类型的沟道区; 以及至少部分地覆盖所述第一和第二雪崩注入元件的公共浮动栅极。在另一实施例中，第一雪崩元件具有N + / P结，第二雪崩元件具有P + / N结，并且浮动栅极电容耦合到第一和第二雪崩元件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式